MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 21 #include "ioport.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #define IRQ_RISE_POSITION 1
sahilmgandhi 18:6a4db94011d3 24 #define IRQ_FALL_POSITION 2
sahilmgandhi 18:6a4db94011d3 25 #define CHANNEL_NUM 48
sahilmgandhi 18:6a4db94011d3 26 #define MAX_PINS_IN_PORT 32
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 29 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 30 extern uint8_t g_sys_init;
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 static IRQn_Type pin_to_irq (uint32_t pin);
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 void gpio_irq_common_handler(uint32_t port_id)
sahilmgandhi 18:6a4db94011d3 35 {
sahilmgandhi 18:6a4db94011d3 36 uint32_t i = 0, status = 0, mask = 0, temp = 0;
sahilmgandhi 18:6a4db94011d3 37 gpio_irq_event event;
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 Pio* pio_base = arch_ioport_port_to_base(port_id);
sahilmgandhi 18:6a4db94011d3 40 mask = pio_base->PIO_IMR;
sahilmgandhi 18:6a4db94011d3 41 status = pio_base->PIO_ISR;
sahilmgandhi 18:6a4db94011d3 42 status = status & mask;
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 for (i = 0; i < MAX_PINS_IN_PORT ; i++) {
sahilmgandhi 18:6a4db94011d3 45 temp = (1 << i );
sahilmgandhi 18:6a4db94011d3 46 if (status & temp ) {
sahilmgandhi 18:6a4db94011d3 47 if((pio_base->PIO_PDSR) & temp) {
sahilmgandhi 18:6a4db94011d3 48 event = IRQ_RISE;
sahilmgandhi 18:6a4db94011d3 49 } else {
sahilmgandhi 18:6a4db94011d3 50 event = IRQ_FALL;
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52 if(irq_handler) {
sahilmgandhi 18:6a4db94011d3 53 irq_handler(channel_ids[(port_id * 32) + i], event);
sahilmgandhi 18:6a4db94011d3 54 }
sahilmgandhi 18:6a4db94011d3 55 }
sahilmgandhi 18:6a4db94011d3 56 }
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 void gpio_irq_porta(void)
sahilmgandhi 18:6a4db94011d3 60 {
sahilmgandhi 18:6a4db94011d3 61 gpio_irq_common_handler(IOPORT_PIOA);
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 void gpio_irq_portb(void)
sahilmgandhi 18:6a4db94011d3 65 {
sahilmgandhi 18:6a4db94011d3 66 gpio_irq_common_handler(IOPORT_PIOB);
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 70 {
sahilmgandhi 18:6a4db94011d3 71 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 72 if (pin == NC)
sahilmgandhi 18:6a4db94011d3 73 return -1;
sahilmgandhi 18:6a4db94011d3 74 if (g_sys_init == 0) {
sahilmgandhi 18:6a4db94011d3 75 sysclk_init();
sahilmgandhi 18:6a4db94011d3 76 system_board_init();
sahilmgandhi 18:6a4db94011d3 77 g_sys_init = 1;
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 IRQn_Type irq_n = (IRQn_Type)0;
sahilmgandhi 18:6a4db94011d3 81 uint32_t port_id;
sahilmgandhi 18:6a4db94011d3 82 uint32_t vector = 0;
sahilmgandhi 18:6a4db94011d3 83 uint8_t int_channel = 0;
sahilmgandhi 18:6a4db94011d3 84 Pio* pio_base;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 irq_handler = handler; // assuming the usage of these apis in mbed layer only
sahilmgandhi 18:6a4db94011d3 87 int_channel = ((pin / 32) * 32) + (pin % 32); /*to get the channel to be used*/
sahilmgandhi 18:6a4db94011d3 88 channel_ids[int_channel] = id;
sahilmgandhi 18:6a4db94011d3 89 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 90 port_id = ioport_pin_to_port_id(pin);
sahilmgandhi 18:6a4db94011d3 91 pio_base = arch_ioport_port_to_base(port_id);
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 ioport_set_pin_dir(pin, IOPORT_DIR_INPUT); /*Pin to be configured input for GPIO Interrupt*/
sahilmgandhi 18:6a4db94011d3 94 ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP);
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 irq_n = pin_to_irq(pin);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 switch (port_id) {
sahilmgandhi 18:6a4db94011d3 99 /*only 2 ports for SAMG55*/ /*Setting up the vectors*/
sahilmgandhi 18:6a4db94011d3 100 case IOPORT_PIOA :
sahilmgandhi 18:6a4db94011d3 101 vector = (uint32_t)gpio_irq_porta;
sahilmgandhi 18:6a4db94011d3 102 break;
sahilmgandhi 18:6a4db94011d3 103 case IOPORT_PIOB :
sahilmgandhi 18:6a4db94011d3 104 vector = (uint32_t)gpio_irq_portb;
sahilmgandhi 18:6a4db94011d3 105 break;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107 pio_base->PIO_ISR; /*To read and clear status register*/
sahilmgandhi 18:6a4db94011d3 108 NVIC_SetVector(irq_n, vector);
sahilmgandhi 18:6a4db94011d3 109 NVIC_EnableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 return 0;
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 void gpio_irq_free(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 115 {
sahilmgandhi 18:6a4db94011d3 116 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 117 channel_ids[((obj->pin / 32) * 32) + (obj->pin % 32)] = 0;
sahilmgandhi 18:6a4db94011d3 118 }
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 121 {
sahilmgandhi 18:6a4db94011d3 122 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 123 uint32_t mask = 0;
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 Pio* pio_base = arch_ioport_port_to_base(arch_ioport_pin_to_port_id(obj->pin));
sahilmgandhi 18:6a4db94011d3 126 mask = (1 << (obj->pin % 32));
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 if (enable) {
sahilmgandhi 18:6a4db94011d3 129 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 130 obj->irqmask |= IRQ_RISE_POSITION;
sahilmgandhi 18:6a4db94011d3 131 } else if (event == IRQ_FALL) {
sahilmgandhi 18:6a4db94011d3 132 obj->irqmask |= IRQ_FALL_POSITION;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134 } else {
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 137 obj->irqmask &= ~IRQ_RISE_POSITION;
sahilmgandhi 18:6a4db94011d3 138 } else if (event == IRQ_FALL) {
sahilmgandhi 18:6a4db94011d3 139 obj->irqmask &= ~IRQ_FALL_POSITION;
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 pio_base->PIO_ISR; /*To read and clear status register*/
sahilmgandhi 18:6a4db94011d3 143 if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) { /*both edge detection*/
sahilmgandhi 18:6a4db94011d3 144 pio_base->PIO_AIMDR = mask;
sahilmgandhi 18:6a4db94011d3 145 pio_base->PIO_IER = mask;
sahilmgandhi 18:6a4db94011d3 146 } else if (obj->irqmask == IRQ_RISE_POSITION) { /*rising detection*/
sahilmgandhi 18:6a4db94011d3 147 pio_base->PIO_ESR = mask;
sahilmgandhi 18:6a4db94011d3 148 pio_base->PIO_REHLSR = mask;
sahilmgandhi 18:6a4db94011d3 149 pio_base->PIO_AIMER = mask;
sahilmgandhi 18:6a4db94011d3 150 pio_base->PIO_IER = mask;
sahilmgandhi 18:6a4db94011d3 151 } else if (obj->irqmask == IRQ_FALL_POSITION) { /*falling detection*/
sahilmgandhi 18:6a4db94011d3 152 pio_base->PIO_ESR = mask;
sahilmgandhi 18:6a4db94011d3 153 pio_base->PIO_FELLSR = mask;
sahilmgandhi 18:6a4db94011d3 154 pio_base->PIO_AIMER = mask;
sahilmgandhi 18:6a4db94011d3 155 pio_base->PIO_IER = mask;
sahilmgandhi 18:6a4db94011d3 156 } else { /*none and disable*/
sahilmgandhi 18:6a4db94011d3 157 pio_base->PIO_IDR = mask;
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 static IRQn_Type pin_to_irq (uint32_t pin)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 uint32_t port_id;
sahilmgandhi 18:6a4db94011d3 164 IRQn_Type irq_n = (IRQn_Type)0;
sahilmgandhi 18:6a4db94011d3 165 port_id = ioport_pin_to_port_id(pin);
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 switch (port_id) {
sahilmgandhi 18:6a4db94011d3 168 case IOPORT_PIOA :
sahilmgandhi 18:6a4db94011d3 169 irq_n = PIOA_IRQn;
sahilmgandhi 18:6a4db94011d3 170 break;
sahilmgandhi 18:6a4db94011d3 171 case IOPORT_PIOB :
sahilmgandhi 18:6a4db94011d3 172 irq_n = PIOB_IRQn;
sahilmgandhi 18:6a4db94011d3 173 break;
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175 return irq_n;
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 void gpio_irq_enable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 179 {
sahilmgandhi 18:6a4db94011d3 180 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 181 NVIC_EnableIRQ(pin_to_irq(obj->pin));
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 void gpio_irq_disable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 185 {
sahilmgandhi 18:6a4db94011d3 186 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 187 NVIC_DisableIRQ(pin_to_irq(obj->pin));
sahilmgandhi 18:6a4db94011d3 188 }