MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief Two-Wire Interface (TWI) driver for SAM.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #ifndef TWI_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 48 #define TWI_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #include "compiler.h"
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /// @cond 0
sahilmgandhi 18:6a4db94011d3 53 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 54 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 55 extern "C" {
sahilmgandhi 18:6a4db94011d3 56 #endif
sahilmgandhi 18:6a4db94011d3 57 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 58 /// @endcond
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /** Time-out value (number of attempts). */
sahilmgandhi 18:6a4db94011d3 61 #define TWI_TIMEOUT 15000
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * \brief Return codes for TWI APIs.
sahilmgandhi 18:6a4db94011d3 65 * @{
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define TWI_SUCCESS 0
sahilmgandhi 18:6a4db94011d3 68 #define TWI_INVALID_ARGUMENT 1
sahilmgandhi 18:6a4db94011d3 69 #define TWI_ARBITRATION_LOST 2
sahilmgandhi 18:6a4db94011d3 70 #define TWI_NO_CHIP_FOUND 3
sahilmgandhi 18:6a4db94011d3 71 #define TWI_RECEIVE_OVERRUN 4
sahilmgandhi 18:6a4db94011d3 72 #define TWI_RECEIVE_NACK 5
sahilmgandhi 18:6a4db94011d3 73 #define TWI_SEND_OVERRUN 6
sahilmgandhi 18:6a4db94011d3 74 #define TWI_SEND_NACK 7
sahilmgandhi 18:6a4db94011d3 75 #define TWI_BUSY 8
sahilmgandhi 18:6a4db94011d3 76 #define TWI_ERROR_TIMEOUT 9
sahilmgandhi 18:6a4db94011d3 77 /**
sahilmgandhi 18:6a4db94011d3 78 * @}
sahilmgandhi 18:6a4db94011d3 79 */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * \brief Input parameters when initializing the TWI module mode.
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 typedef struct twi_options {
sahilmgandhi 18:6a4db94011d3 85 //! MCK for TWI.
sahilmgandhi 18:6a4db94011d3 86 uint32_t master_clk;
sahilmgandhi 18:6a4db94011d3 87 //! The baud rate of the TWI bus.
sahilmgandhi 18:6a4db94011d3 88 uint32_t speed;
sahilmgandhi 18:6a4db94011d3 89 //! The desired address.
sahilmgandhi 18:6a4db94011d3 90 uint8_t chip;
sahilmgandhi 18:6a4db94011d3 91 //! SMBUS mode (set 1 to use SMBUS quick command, otherwise don't).
sahilmgandhi 18:6a4db94011d3 92 uint8_t smbus;
sahilmgandhi 18:6a4db94011d3 93 } twi_options_t;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /**
sahilmgandhi 18:6a4db94011d3 96 * \brief Information concerning the data transmission.
sahilmgandhi 18:6a4db94011d3 97 */
sahilmgandhi 18:6a4db94011d3 98 typedef struct twi_packet {
sahilmgandhi 18:6a4db94011d3 99 //! TWI address/commands to issue to the other chip (node).
sahilmgandhi 18:6a4db94011d3 100 uint8_t addr[3];
sahilmgandhi 18:6a4db94011d3 101 //! Length of the TWI data address segment (1-3 bytes).
sahilmgandhi 18:6a4db94011d3 102 uint32_t addr_length;
sahilmgandhi 18:6a4db94011d3 103 //! Where to find the data to be transferred.
sahilmgandhi 18:6a4db94011d3 104 void *buffer;
sahilmgandhi 18:6a4db94011d3 105 //! How many bytes do we want to transfer.
sahilmgandhi 18:6a4db94011d3 106 uint32_t length;
sahilmgandhi 18:6a4db94011d3 107 //! TWI chip address to communicate with.
sahilmgandhi 18:6a4db94011d3 108 uint8_t chip;
sahilmgandhi 18:6a4db94011d3 109 } twi_packet_t;
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 #if SAMG55
sahilmgandhi 18:6a4db94011d3 112 enum twi_source_clock {
sahilmgandhi 18:6a4db94011d3 113 TWI_SOURCE_PERIPH_CLK = TWI_CWGR_BRSRCCLK_PERIPH_CLK,
sahilmgandhi 18:6a4db94011d3 114 TWI_SOURCE_PCK_CLK = TWI_CWGR_BRSRCCLK_PMC_PCK,
sahilmgandhi 18:6a4db94011d3 115 };
sahilmgandhi 18:6a4db94011d3 116 #endif
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 void twi_enable_master_mode(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 119 void twi_disable_master_mode(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 120 uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt);
sahilmgandhi 18:6a4db94011d3 121 uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 122 uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr);
sahilmgandhi 18:6a4db94011d3 123 uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet);
sahilmgandhi 18:6a4db94011d3 124 uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet);
sahilmgandhi 18:6a4db94011d3 125 void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources);
sahilmgandhi 18:6a4db94011d3 126 void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources);
sahilmgandhi 18:6a4db94011d3 127 uint32_t twi_get_interrupt_status(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 128 uint32_t twi_get_interrupt_mask(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 129 uint8_t twi_read_byte(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 130 void twi_write_byte(Twi *p_twi, uint8_t uc_byte);
sahilmgandhi 18:6a4db94011d3 131 void twi_enable_slave_mode(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 132 void twi_disable_slave_mode(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 133 void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr);
sahilmgandhi 18:6a4db94011d3 134 void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr);
sahilmgandhi 18:6a4db94011d3 135 uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data);
sahilmgandhi 18:6a4db94011d3 136 uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data);
sahilmgandhi 18:6a4db94011d3 137 void twi_reset(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 138 Pdc *twi_get_pdc_base(Twi *p_twi);
sahilmgandhi 18:6a4db94011d3 139 #if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
sahilmgandhi 18:6a4db94011d3 140 void twi_set_write_protection(Twi *p_twi, bool flag);
sahilmgandhi 18:6a4db94011d3 141 void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status);
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #if SAMG55
sahilmgandhi 18:6a4db94011d3 145 void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing);
sahilmgandhi 18:6a4db94011d3 146 void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd);
sahilmgandhi 18:6a4db94011d3 147 void twi_set_filter(Twi *p_twi, uint32_t ul_filter);
sahilmgandhi 18:6a4db94011d3 148 void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask);
sahilmgandhi 18:6a4db94011d3 149 void twi_set_sleepwalking(Twi *p_twi,
sahilmgandhi 18:6a4db94011d3 150 uint32_t ul_matching_addr1, bool flag1,
sahilmgandhi 18:6a4db94011d3 151 uint32_t ul_matching_addr2, bool flag2,
sahilmgandhi 18:6a4db94011d3 152 uint32_t ul_matching_addr3, bool flag3,
sahilmgandhi 18:6a4db94011d3 153 uint32_t ul_matching_data, bool flag);
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /**
sahilmgandhi 18:6a4db94011d3 156 * \brief Enable high speed mode.
sahilmgandhi 18:6a4db94011d3 157 *
sahilmgandhi 18:6a4db94011d3 158 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 159 */
sahilmgandhi 18:6a4db94011d3 160 static inline void twi_enable_highspeed(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 161 {
sahilmgandhi 18:6a4db94011d3 162 p_twi->TWI_CR = TWI_CR_HSEN;
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /**
sahilmgandhi 18:6a4db94011d3 166 * \brief Disable high speed mode.
sahilmgandhi 18:6a4db94011d3 167 *
sahilmgandhi 18:6a4db94011d3 168 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170 static inline void twi_disable_highspeed(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 171 {
sahilmgandhi 18:6a4db94011d3 172 p_twi->TWI_CR = TWI_CR_HSDIS;
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /**
sahilmgandhi 18:6a4db94011d3 176 * \brief Enable SMBus mode.
sahilmgandhi 18:6a4db94011d3 177 *
sahilmgandhi 18:6a4db94011d3 178 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 179 */
sahilmgandhi 18:6a4db94011d3 180 static inline void twi_enable_smbus(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 181 {
sahilmgandhi 18:6a4db94011d3 182 p_twi->TWI_CR = TWI_CR_SMBEN;
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /**
sahilmgandhi 18:6a4db94011d3 186 * \brief Disable SMBus mode.
sahilmgandhi 18:6a4db94011d3 187 *
sahilmgandhi 18:6a4db94011d3 188 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 static inline void twi_disable_smbus(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 p_twi->TWI_CR = TWI_CR_SMBDIS;
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * \brief Enable packet error checking.
sahilmgandhi 18:6a4db94011d3 197 *
sahilmgandhi 18:6a4db94011d3 198 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200 static inline void twi_enable_pec(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 201 {
sahilmgandhi 18:6a4db94011d3 202 p_twi->TWI_CR = TWI_CR_PECEN;
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * \brief Disable packet error checking.
sahilmgandhi 18:6a4db94011d3 207 *
sahilmgandhi 18:6a4db94011d3 208 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 209 */
sahilmgandhi 18:6a4db94011d3 210 static inline void twi_disable_pec(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 211 {
sahilmgandhi 18:6a4db94011d3 212 p_twi->TWI_CR = TWI_CR_PECDIS;
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /**
sahilmgandhi 18:6a4db94011d3 216 * \brief Request a packet error checking.
sahilmgandhi 18:6a4db94011d3 217 *
sahilmgandhi 18:6a4db94011d3 218 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220 static inline void twi_request_pec(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 221 {
sahilmgandhi 18:6a4db94011d3 222 p_twi->TWI_CR = TWI_CR_PECRQ;
sahilmgandhi 18:6a4db94011d3 223 }
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 /**
sahilmgandhi 18:6a4db94011d3 226 * \brief If master mode is enabled, send a bus clear command.
sahilmgandhi 18:6a4db94011d3 227 *
sahilmgandhi 18:6a4db94011d3 228 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 static inline void twi_send_clear(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 p_twi->TWI_CR = TWI_CR_CLEAR;
sahilmgandhi 18:6a4db94011d3 233 }
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /**
sahilmgandhi 18:6a4db94011d3 236 * \brief Enable alternative command mode.
sahilmgandhi 18:6a4db94011d3 237 *
sahilmgandhi 18:6a4db94011d3 238 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240 static inline void twi_enable_alternative_command(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 p_twi->TWI_CR = TWI_CR_ACMEN;
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /**
sahilmgandhi 18:6a4db94011d3 246 * \brief Enable alternative command mode.
sahilmgandhi 18:6a4db94011d3 247 *
sahilmgandhi 18:6a4db94011d3 248 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 249 */
sahilmgandhi 18:6a4db94011d3 250 static inline void twi_disable_alternative_command(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 251 {
sahilmgandhi 18:6a4db94011d3 252 p_twi->TWI_CR = TWI_CR_ACMDIS;
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * \brief Clear the Transmit Holding Register and set TXRDY, TXCOMP flags.
sahilmgandhi 18:6a4db94011d3 257 *
sahilmgandhi 18:6a4db94011d3 258 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 259 */
sahilmgandhi 18:6a4db94011d3 260 static inline void twi_thr_clear(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 261 {
sahilmgandhi 18:6a4db94011d3 262 p_twi->TWI_CR = TWI_CR_THRCLR;
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /**
sahilmgandhi 18:6a4db94011d3 266 * \brief Clear the TWI FSM lock.
sahilmgandhi 18:6a4db94011d3 267 *
sahilmgandhi 18:6a4db94011d3 268 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 269 */
sahilmgandhi 18:6a4db94011d3 270 static inline void twi_lock_clear(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 271 {
sahilmgandhi 18:6a4db94011d3 272 p_twi->TWI_CR = TWI_CR_LOCKCLR;
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /**
sahilmgandhi 18:6a4db94011d3 276 * \brief Normal value to be returned in the ACK cycle of the data phase in slave receiver mode.
sahilmgandhi 18:6a4db94011d3 277 *
sahilmgandhi 18:6a4db94011d3 278 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 279 */
sahilmgandhi 18:6a4db94011d3 280 static inline void twi_disable_slave_nack(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 281 {
sahilmgandhi 18:6a4db94011d3 282 p_twi->TWI_SMR &= ~TWI_SMR_NACKEN;
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /**
sahilmgandhi 18:6a4db94011d3 286 * \brief NACK value to be returned in the ACK cycle of the data phase in slave receiver mode.
sahilmgandhi 18:6a4db94011d3 287 *
sahilmgandhi 18:6a4db94011d3 288 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290 static inline void twi_enable_slave_nack(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 p_twi->TWI_SMR |= TWI_SMR_NACKEN;
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * \brief Acknowledge of the SMBus Default Address disabled.
sahilmgandhi 18:6a4db94011d3 297 *
sahilmgandhi 18:6a4db94011d3 298 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 299 */
sahilmgandhi 18:6a4db94011d3 300 static inline void twi_disable_slave_default_addr(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 301 {
sahilmgandhi 18:6a4db94011d3 302 p_twi->TWI_SMR &= ~TWI_SMR_SMDA;
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /**
sahilmgandhi 18:6a4db94011d3 306 * \brief Acknowledge of the SMBus Default Address enabled.
sahilmgandhi 18:6a4db94011d3 307 *
sahilmgandhi 18:6a4db94011d3 308 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 309 */
sahilmgandhi 18:6a4db94011d3 310 static inline void twi_enable_slave_default_addr(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 p_twi->TWI_SMR |= TWI_SMR_SMDA;
sahilmgandhi 18:6a4db94011d3 313 }
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /**
sahilmgandhi 18:6a4db94011d3 316 * \brief Acknowledge of the SMBus Host Header disabled.
sahilmgandhi 18:6a4db94011d3 317 *
sahilmgandhi 18:6a4db94011d3 318 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 319 */
sahilmgandhi 18:6a4db94011d3 320 static inline void twi_disable_smbus_host_header(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 p_twi->TWI_SMR &= ~TWI_SMR_SMHH;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /**
sahilmgandhi 18:6a4db94011d3 326 * \brief Acknowledge of the SMBus Host Header enabled.
sahilmgandhi 18:6a4db94011d3 327 *
sahilmgandhi 18:6a4db94011d3 328 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 329 */
sahilmgandhi 18:6a4db94011d3 330 static inline void twi_enable_smbus_host_header(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 331 {
sahilmgandhi 18:6a4db94011d3 332 p_twi->TWI_SMR |= TWI_SMR_SMHH;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /**
sahilmgandhi 18:6a4db94011d3 336 * \brief Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun.
sahilmgandhi 18:6a4db94011d3 337 *
sahilmgandhi 18:6a4db94011d3 338 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 static inline void twi_disable_clock_wait_state(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 341 {
sahilmgandhi 18:6a4db94011d3 342 p_twi->TWI_SMR |= TWI_SMR_SCLWSDIS;
sahilmgandhi 18:6a4db94011d3 343 }
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /**
sahilmgandhi 18:6a4db94011d3 346 * \brief Clear clock wait state disable mode.
sahilmgandhi 18:6a4db94011d3 347 *
sahilmgandhi 18:6a4db94011d3 348 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 349 */
sahilmgandhi 18:6a4db94011d3 350 static inline void twi_clear_disable_clock_wait_state(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 351 {
sahilmgandhi 18:6a4db94011d3 352 p_twi->TWI_SMR &= ~TWI_SMR_SCLWSDIS;
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /**
sahilmgandhi 18:6a4db94011d3 356 * \brief Slave Address 1 matching disabled.
sahilmgandhi 18:6a4db94011d3 357 *
sahilmgandhi 18:6a4db94011d3 358 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 359 */
sahilmgandhi 18:6a4db94011d3 360 static inline void twi_disable_slave_addr1_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 361 {
sahilmgandhi 18:6a4db94011d3 362 p_twi->TWI_SMR &= ~TWI_SMR_SADR1EN;
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /**
sahilmgandhi 18:6a4db94011d3 366 * \brief Slave Address 1 matching enabled.
sahilmgandhi 18:6a4db94011d3 367 *
sahilmgandhi 18:6a4db94011d3 368 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 369 */
sahilmgandhi 18:6a4db94011d3 370 static inline void twi_enable_slave_addr1_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 371 {
sahilmgandhi 18:6a4db94011d3 372 p_twi->TWI_SMR |= TWI_SMR_SADR1EN;
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /**
sahilmgandhi 18:6a4db94011d3 376 * \brief Slave Address 2 matching disabled.
sahilmgandhi 18:6a4db94011d3 377 *
sahilmgandhi 18:6a4db94011d3 378 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380 static inline void twi_disable_slave_addr2_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 381 {
sahilmgandhi 18:6a4db94011d3 382 p_twi->TWI_SMR &= ~TWI_SMR_SADR2EN;
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * \brief Slave Address 2 matching enabled.
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390 static inline void twi_enable_slave_addr2_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 391 {
sahilmgandhi 18:6a4db94011d3 392 p_twi->TWI_SMR |= TWI_SMR_SADR2EN;
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 /**
sahilmgandhi 18:6a4db94011d3 396 * \brief Slave Address 3 matching disabled.
sahilmgandhi 18:6a4db94011d3 397 *
sahilmgandhi 18:6a4db94011d3 398 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 399 */
sahilmgandhi 18:6a4db94011d3 400 static inline void twi_disable_slave_addr3_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 401 {
sahilmgandhi 18:6a4db94011d3 402 p_twi->TWI_SMR &= ~TWI_SMR_SADR3EN;
sahilmgandhi 18:6a4db94011d3 403 }
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 /**
sahilmgandhi 18:6a4db94011d3 406 * \brief Slave Address 3 matching enabled.
sahilmgandhi 18:6a4db94011d3 407 *
sahilmgandhi 18:6a4db94011d3 408 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 409 */
sahilmgandhi 18:6a4db94011d3 410 static inline void twi_enable_slave_addr3_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 411 {
sahilmgandhi 18:6a4db94011d3 412 p_twi->TWI_SMR |= TWI_SMR_SADR3EN;
sahilmgandhi 18:6a4db94011d3 413 }
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /**
sahilmgandhi 18:6a4db94011d3 416 * \brief First received data matching disabled.
sahilmgandhi 18:6a4db94011d3 417 *
sahilmgandhi 18:6a4db94011d3 418 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 419 */
sahilmgandhi 18:6a4db94011d3 420 static inline void twi_disable_slave_data_matching(Twi *p_twi)
sahilmgandhi 18:6a4db94011d3 421 {
sahilmgandhi 18:6a4db94011d3 422 p_twi->TWI_SMR &= ~TWI_SMR_DATAMEN;
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /**
sahilmgandhi 18:6a4db94011d3 426 * \brief Select the souce clock for the bit rate generation.
sahilmgandhi 18:6a4db94011d3 427 *
sahilmgandhi 18:6a4db94011d3 428 * \param p_twi Base address of the TWI instance.
sahilmgandhi 18:6a4db94011d3 429 * \param src_clk Source clock.
sahilmgandhi 18:6a4db94011d3 430 */
sahilmgandhi 18:6a4db94011d3 431 static inline void twi_select_source_clock(Twi *p_twi, enum twi_source_clock src_clk)
sahilmgandhi 18:6a4db94011d3 432 {
sahilmgandhi 18:6a4db94011d3 433 p_twi->TWI_CWGR &= ~TWI_CWGR_BRSRCCLK;
sahilmgandhi 18:6a4db94011d3 434 p_twi->TWI_CWGR |= src_clk;
sahilmgandhi 18:6a4db94011d3 435 }
sahilmgandhi 18:6a4db94011d3 436 #endif
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 /// @cond 0
sahilmgandhi 18:6a4db94011d3 439 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 440 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442 #endif
sahilmgandhi 18:6a4db94011d3 443 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 444 /// @endcond
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 #endif /* TWI_H_INCLUDED */