MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief Parallel Input/Output (PIO) Controller driver for SAM.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #include "pio.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 #ifndef PIO_WPMR_WPKEY_PASSWD
sahilmgandhi 18:6a4db94011d3 50 # define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu)
sahilmgandhi 18:6a4db94011d3 51 #endif
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /**
sahilmgandhi 18:6a4db94011d3 54 * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller
sahilmgandhi 18:6a4db94011d3 55 *
sahilmgandhi 18:6a4db94011d3 56 * \par Purpose
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * The Parallel Input/Output Controller (PIO) manages up to 32 fully
sahilmgandhi 18:6a4db94011d3 59 * programmable input/output lines. Each I/O line may be dedicated as a
sahilmgandhi 18:6a4db94011d3 60 * general-purpose I/O or be assigned to a function of an embedded peripheral.
sahilmgandhi 18:6a4db94011d3 61 * This assures effective optimization of the pins of a product.
sahilmgandhi 18:6a4db94011d3 62 *
sahilmgandhi 18:6a4db94011d3 63 * @{
sahilmgandhi 18:6a4db94011d3 64 */
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #ifndef FREQ_SLOW_CLOCK_EXT
sahilmgandhi 18:6a4db94011d3 67 /* External slow clock frequency (hz) */
sahilmgandhi 18:6a4db94011d3 68 #define FREQ_SLOW_CLOCK_EXT 32768
sahilmgandhi 18:6a4db94011d3 69 #endif
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /**
sahilmgandhi 18:6a4db94011d3 72 * \brief Configure PIO internal pull-up.
sahilmgandhi 18:6a4db94011d3 73 *
sahilmgandhi 18:6a4db94011d3 74 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 75 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 76 * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be
sahilmgandhi 18:6a4db94011d3 77 * configured.
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 80 const uint32_t ul_pull_up_enable)
sahilmgandhi 18:6a4db94011d3 81 {
sahilmgandhi 18:6a4db94011d3 82 /* Enable the pull-up(s) if necessary */
sahilmgandhi 18:6a4db94011d3 83 if (ul_pull_up_enable) {
sahilmgandhi 18:6a4db94011d3 84 p_pio->PIO_PUER = ul_mask;
sahilmgandhi 18:6a4db94011d3 85 } else {
sahilmgandhi 18:6a4db94011d3 86 p_pio->PIO_PUDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88 }
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /**
sahilmgandhi 18:6a4db94011d3 91 * \brief Configure Glitch or Debouncing filter for the specified input(s).
sahilmgandhi 18:6a4db94011d3 92 *
sahilmgandhi 18:6a4db94011d3 93 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 94 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 95 * \param ul_cut_off Cuts off frequency for debouncing filter.
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97 void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 98 const uint32_t ul_cut_off)
sahilmgandhi 18:6a4db94011d3 99 {
sahilmgandhi 18:6a4db94011d3 100 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 101 /* Set Debouncing, 0 bit field no effect */
sahilmgandhi 18:6a4db94011d3 102 p_pio->PIO_IFSCER = ul_mask;
sahilmgandhi 18:6a4db94011d3 103 #elif (SAM3XA || SAM3U)
sahilmgandhi 18:6a4db94011d3 104 /* Set Debouncing, 0 bit field no effect */
sahilmgandhi 18:6a4db94011d3 105 p_pio->PIO_DIFSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 106 #else
sahilmgandhi 18:6a4db94011d3 107 #error "Unsupported device"
sahilmgandhi 18:6a4db94011d3 108 #endif
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /*
sahilmgandhi 18:6a4db94011d3 111 * The debouncing filter can filter a pulse of less than 1/2 Period of a
sahilmgandhi 18:6a4db94011d3 112 * programmable Divided Slow Clock:
sahilmgandhi 18:6a4db94011d3 113 * Tdiv_slclk = ((DIV+1)*2).Tslow_clock
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115 p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /
sahilmgandhi 18:6a4db94011d3 116 (2 * (ul_cut_off))) - 1);
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /**
sahilmgandhi 18:6a4db94011d3 120 * \brief Set a high output level on all the PIOs defined in ul_mask.
sahilmgandhi 18:6a4db94011d3 121 * This has no immediate effects on PIOs that are not output, but the PIO
sahilmgandhi 18:6a4db94011d3 122 * controller will save the value if they are changed to outputs.
sahilmgandhi 18:6a4db94011d3 123 *
sahilmgandhi 18:6a4db94011d3 124 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 125 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127 void pio_set(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 128 {
sahilmgandhi 18:6a4db94011d3 129 p_pio->PIO_SODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /**
sahilmgandhi 18:6a4db94011d3 133 * \brief Set a low output level on all the PIOs defined in ul_mask.
sahilmgandhi 18:6a4db94011d3 134 * This has no immediate effects on PIOs that are not output, but the PIO
sahilmgandhi 18:6a4db94011d3 135 * controller will save the value if they are changed to outputs.
sahilmgandhi 18:6a4db94011d3 136 *
sahilmgandhi 18:6a4db94011d3 137 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 138 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 void pio_clear(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 141 {
sahilmgandhi 18:6a4db94011d3 142 p_pio->PIO_CODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /**
sahilmgandhi 18:6a4db94011d3 146 * \brief Return 1 if one or more PIOs of the given Pin instance currently have
sahilmgandhi 18:6a4db94011d3 147 * a high level; otherwise returns 0. This method returns the actual value that
sahilmgandhi 18:6a4db94011d3 148 * is being read on the pin. To return the supposed output value of a pin, use
sahilmgandhi 18:6a4db94011d3 149 * pio_get_output_data_status() instead.
sahilmgandhi 18:6a4db94011d3 150 *
sahilmgandhi 18:6a4db94011d3 151 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 152 * \param ul_type PIO type.
sahilmgandhi 18:6a4db94011d3 153 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 154 *
sahilmgandhi 18:6a4db94011d3 155 * \retval 1 at least one PIO currently has a high level.
sahilmgandhi 18:6a4db94011d3 156 * \retval 0 all PIOs have a low level.
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,
sahilmgandhi 18:6a4db94011d3 159 const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 160 {
sahilmgandhi 18:6a4db94011d3 161 uint32_t ul_reg;
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {
sahilmgandhi 18:6a4db94011d3 164 ul_reg = p_pio->PIO_ODSR;
sahilmgandhi 18:6a4db94011d3 165 } else {
sahilmgandhi 18:6a4db94011d3 166 ul_reg = p_pio->PIO_PDSR;
sahilmgandhi 18:6a4db94011d3 167 }
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 if ((ul_reg & ul_mask) == 0) {
sahilmgandhi 18:6a4db94011d3 170 return 0;
sahilmgandhi 18:6a4db94011d3 171 } else {
sahilmgandhi 18:6a4db94011d3 172 return 1;
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /**
sahilmgandhi 18:6a4db94011d3 177 * \brief Configure IO of a PIO controller as being controlled by a specific
sahilmgandhi 18:6a4db94011d3 178 * peripheral.
sahilmgandhi 18:6a4db94011d3 179 *
sahilmgandhi 18:6a4db94011d3 180 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 181 * \param ul_type PIO type.
sahilmgandhi 18:6a4db94011d3 182 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 183 */
sahilmgandhi 18:6a4db94011d3 184 void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,
sahilmgandhi 18:6a4db94011d3 185 const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 186 {
sahilmgandhi 18:6a4db94011d3 187 uint32_t ul_sr;
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /* Disable interrupts on the pin(s) */
sahilmgandhi 18:6a4db94011d3 190 p_pio->PIO_IDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 193 switch (ul_type) {
sahilmgandhi 18:6a4db94011d3 194 case PIO_PERIPH_A:
sahilmgandhi 18:6a4db94011d3 195 ul_sr = p_pio->PIO_ABCDSR[0];
sahilmgandhi 18:6a4db94011d3 196 p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 ul_sr = p_pio->PIO_ABCDSR[1];
sahilmgandhi 18:6a4db94011d3 199 p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
sahilmgandhi 18:6a4db94011d3 200 break;
sahilmgandhi 18:6a4db94011d3 201 case PIO_PERIPH_B:
sahilmgandhi 18:6a4db94011d3 202 ul_sr = p_pio->PIO_ABCDSR[0];
sahilmgandhi 18:6a4db94011d3 203 p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 ul_sr = p_pio->PIO_ABCDSR[1];
sahilmgandhi 18:6a4db94011d3 206 p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
sahilmgandhi 18:6a4db94011d3 207 break;
sahilmgandhi 18:6a4db94011d3 208 #if (!SAMG)
sahilmgandhi 18:6a4db94011d3 209 case PIO_PERIPH_C:
sahilmgandhi 18:6a4db94011d3 210 ul_sr = p_pio->PIO_ABCDSR[0];
sahilmgandhi 18:6a4db94011d3 211 p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 ul_sr = p_pio->PIO_ABCDSR[1];
sahilmgandhi 18:6a4db94011d3 214 p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
sahilmgandhi 18:6a4db94011d3 215 break;
sahilmgandhi 18:6a4db94011d3 216 case PIO_PERIPH_D:
sahilmgandhi 18:6a4db94011d3 217 ul_sr = p_pio->PIO_ABCDSR[0];
sahilmgandhi 18:6a4db94011d3 218 p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 ul_sr = p_pio->PIO_ABCDSR[1];
sahilmgandhi 18:6a4db94011d3 221 p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
sahilmgandhi 18:6a4db94011d3 222 break;
sahilmgandhi 18:6a4db94011d3 223 #endif
sahilmgandhi 18:6a4db94011d3 224 /* Other types are invalid in this function */
sahilmgandhi 18:6a4db94011d3 225 case PIO_INPUT:
sahilmgandhi 18:6a4db94011d3 226 case PIO_OUTPUT_0:
sahilmgandhi 18:6a4db94011d3 227 case PIO_OUTPUT_1:
sahilmgandhi 18:6a4db94011d3 228 case PIO_NOT_A_PIN:
sahilmgandhi 18:6a4db94011d3 229 return;
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231 #elif (SAM3XA|| SAM3U)
sahilmgandhi 18:6a4db94011d3 232 switch (ul_type) {
sahilmgandhi 18:6a4db94011d3 233 case PIO_PERIPH_A:
sahilmgandhi 18:6a4db94011d3 234 ul_sr = p_pio->PIO_ABSR;
sahilmgandhi 18:6a4db94011d3 235 p_pio->PIO_ABSR &= (~ul_mask & ul_sr);
sahilmgandhi 18:6a4db94011d3 236 break;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 case PIO_PERIPH_B:
sahilmgandhi 18:6a4db94011d3 239 ul_sr = p_pio->PIO_ABSR;
sahilmgandhi 18:6a4db94011d3 240 p_pio->PIO_ABSR = (ul_mask | ul_sr);
sahilmgandhi 18:6a4db94011d3 241 break;
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 // other types are invalid in this function
sahilmgandhi 18:6a4db94011d3 244 case PIO_INPUT:
sahilmgandhi 18:6a4db94011d3 245 case PIO_OUTPUT_0:
sahilmgandhi 18:6a4db94011d3 246 case PIO_OUTPUT_1:
sahilmgandhi 18:6a4db94011d3 247 case PIO_NOT_A_PIN:
sahilmgandhi 18:6a4db94011d3 248 return;
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250 #else
sahilmgandhi 18:6a4db94011d3 251 #error "Unsupported device"
sahilmgandhi 18:6a4db94011d3 252 #endif
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* Remove the pins from under the control of PIO */
sahilmgandhi 18:6a4db94011d3 255 p_pio->PIO_PDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /**
sahilmgandhi 18:6a4db94011d3 259 * \brief Configure one or more pin(s) or a PIO controller as inputs.
sahilmgandhi 18:6a4db94011d3 260 * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can
sahilmgandhi 18:6a4db94011d3 261 * be enabled.
sahilmgandhi 18:6a4db94011d3 262 *
sahilmgandhi 18:6a4db94011d3 263 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 264 * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).
sahilmgandhi 18:6a4db94011d3 265 * \param ul_attribute PIO attribute(s).
sahilmgandhi 18:6a4db94011d3 266 */
sahilmgandhi 18:6a4db94011d3 267 void pio_set_input(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 268 const uint32_t ul_attribute)
sahilmgandhi 18:6a4db94011d3 269 {
sahilmgandhi 18:6a4db94011d3 270 pio_disable_interrupt(p_pio, ul_mask);
sahilmgandhi 18:6a4db94011d3 271 pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 /* Enable Input Filter if necessary */
sahilmgandhi 18:6a4db94011d3 274 if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {
sahilmgandhi 18:6a4db94011d3 275 p_pio->PIO_IFER = ul_mask;
sahilmgandhi 18:6a4db94011d3 276 } else {
sahilmgandhi 18:6a4db94011d3 277 p_pio->PIO_IFDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 281 /* Enable de-glitch or de-bounce if necessary */
sahilmgandhi 18:6a4db94011d3 282 if (ul_attribute & PIO_DEGLITCH) {
sahilmgandhi 18:6a4db94011d3 283 p_pio->PIO_IFSCDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 284 } else {
sahilmgandhi 18:6a4db94011d3 285 if (ul_attribute & PIO_DEBOUNCE) {
sahilmgandhi 18:6a4db94011d3 286 p_pio->PIO_IFSCER = ul_mask;
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289 #elif (SAM3XA|| SAM3U)
sahilmgandhi 18:6a4db94011d3 290 /* Enable de-glitch or de-bounce if necessary */
sahilmgandhi 18:6a4db94011d3 291 if (ul_attribute & PIO_DEGLITCH) {
sahilmgandhi 18:6a4db94011d3 292 p_pio->PIO_SCIFSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 293 } else {
sahilmgandhi 18:6a4db94011d3 294 if (ul_attribute & PIO_DEBOUNCE) {
sahilmgandhi 18:6a4db94011d3 295 p_pio->PIO_DIFSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 296 }
sahilmgandhi 18:6a4db94011d3 297 }
sahilmgandhi 18:6a4db94011d3 298 #else
sahilmgandhi 18:6a4db94011d3 299 #error "Unsupported device"
sahilmgandhi 18:6a4db94011d3 300 #endif
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /* Configure pin as input */
sahilmgandhi 18:6a4db94011d3 303 p_pio->PIO_ODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 304 p_pio->PIO_PER = ul_mask;
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /**
sahilmgandhi 18:6a4db94011d3 308 * \brief Configure one or more pin(s) of a PIO controller as outputs, with
sahilmgandhi 18:6a4db94011d3 309 * the given default value. Optionally, the multi-drive feature can be enabled
sahilmgandhi 18:6a4db94011d3 310 * on the pin(s).
sahilmgandhi 18:6a4db94011d3 311 *
sahilmgandhi 18:6a4db94011d3 312 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 313 * \param ul_mask Bitmask indicating which pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 314 * \param ul_default_level Default level on the pin(s).
sahilmgandhi 18:6a4db94011d3 315 * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as
sahilmgandhi 18:6a4db94011d3 316 * open-drain.
sahilmgandhi 18:6a4db94011d3 317 * \param ul_pull_up_enable Indicates if the pin shall have its pull-up
sahilmgandhi 18:6a4db94011d3 318 * activated.
sahilmgandhi 18:6a4db94011d3 319 */
sahilmgandhi 18:6a4db94011d3 320 void pio_set_output(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 321 const uint32_t ul_default_level,
sahilmgandhi 18:6a4db94011d3 322 const uint32_t ul_multidrive_enable,
sahilmgandhi 18:6a4db94011d3 323 const uint32_t ul_pull_up_enable)
sahilmgandhi 18:6a4db94011d3 324 {
sahilmgandhi 18:6a4db94011d3 325 pio_disable_interrupt(p_pio, ul_mask);
sahilmgandhi 18:6a4db94011d3 326 pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /* Enable multi-drive if necessary */
sahilmgandhi 18:6a4db94011d3 329 if (ul_multidrive_enable) {
sahilmgandhi 18:6a4db94011d3 330 p_pio->PIO_MDER = ul_mask;
sahilmgandhi 18:6a4db94011d3 331 } else {
sahilmgandhi 18:6a4db94011d3 332 p_pio->PIO_MDDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /* Set default value */
sahilmgandhi 18:6a4db94011d3 336 if (ul_default_level) {
sahilmgandhi 18:6a4db94011d3 337 p_pio->PIO_SODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 338 } else {
sahilmgandhi 18:6a4db94011d3 339 p_pio->PIO_CODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* Configure pin(s) as output(s) */
sahilmgandhi 18:6a4db94011d3 343 p_pio->PIO_OER = ul_mask;
sahilmgandhi 18:6a4db94011d3 344 p_pio->PIO_PER = ul_mask;
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /**
sahilmgandhi 18:6a4db94011d3 348 * \brief Perform complete pin(s) configuration; general attributes and PIO init
sahilmgandhi 18:6a4db94011d3 349 * if necessary.
sahilmgandhi 18:6a4db94011d3 350 *
sahilmgandhi 18:6a4db94011d3 351 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 352 * \param ul_type PIO type.
sahilmgandhi 18:6a4db94011d3 353 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 354 * \param ul_attribute Pins attributes.
sahilmgandhi 18:6a4db94011d3 355 *
sahilmgandhi 18:6a4db94011d3 356 * \return Whether the pin(s) have been configured properly.
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358 uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,
sahilmgandhi 18:6a4db94011d3 359 const uint32_t ul_mask, const uint32_t ul_attribute)
sahilmgandhi 18:6a4db94011d3 360 {
sahilmgandhi 18:6a4db94011d3 361 /* Configure pins */
sahilmgandhi 18:6a4db94011d3 362 switch (ul_type) {
sahilmgandhi 18:6a4db94011d3 363 case PIO_PERIPH_A:
sahilmgandhi 18:6a4db94011d3 364 case PIO_PERIPH_B:
sahilmgandhi 18:6a4db94011d3 365 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 366 case PIO_PERIPH_C:
sahilmgandhi 18:6a4db94011d3 367 case PIO_PERIPH_D:
sahilmgandhi 18:6a4db94011d3 368 #endif
sahilmgandhi 18:6a4db94011d3 369 pio_set_peripheral(p_pio, ul_type, ul_mask);
sahilmgandhi 18:6a4db94011d3 370 pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 371 break;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 case PIO_INPUT:
sahilmgandhi 18:6a4db94011d3 374 pio_set_input(p_pio, ul_mask, ul_attribute);
sahilmgandhi 18:6a4db94011d3 375 break;
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 case PIO_OUTPUT_0:
sahilmgandhi 18:6a4db94011d3 378 case PIO_OUTPUT_1:
sahilmgandhi 18:6a4db94011d3 379 pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),
sahilmgandhi 18:6a4db94011d3 380 (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,
sahilmgandhi 18:6a4db94011d3 381 (ul_attribute & PIO_PULLUP) ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 382 break;
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 default:
sahilmgandhi 18:6a4db94011d3 385 return 0;
sahilmgandhi 18:6a4db94011d3 386 }
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 return 1;
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /**
sahilmgandhi 18:6a4db94011d3 392 * \brief Return 1 if one or more PIOs of the given Pin are configured to
sahilmgandhi 18:6a4db94011d3 393 * output a high level (even if they are not output).
sahilmgandhi 18:6a4db94011d3 394 * To get the actual value of the pin, use PIO_Get() instead.
sahilmgandhi 18:6a4db94011d3 395 *
sahilmgandhi 18:6a4db94011d3 396 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 397 * \param ul_mask Bitmask of one or more pin(s).
sahilmgandhi 18:6a4db94011d3 398 *
sahilmgandhi 18:6a4db94011d3 399 * \retval 1 At least one PIO is configured to output a high level.
sahilmgandhi 18:6a4db94011d3 400 * \retval 0 All PIOs are configured to output a low level.
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402 uint32_t pio_get_output_data_status(const Pio *p_pio,
sahilmgandhi 18:6a4db94011d3 403 const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 404 {
sahilmgandhi 18:6a4db94011d3 405 if ((p_pio->PIO_ODSR & ul_mask) == 0) {
sahilmgandhi 18:6a4db94011d3 406 return 0;
sahilmgandhi 18:6a4db94011d3 407 } else {
sahilmgandhi 18:6a4db94011d3 408 return 1;
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410 }
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /**
sahilmgandhi 18:6a4db94011d3 413 * \brief Configure PIO pin multi-driver.
sahilmgandhi 18:6a4db94011d3 414 *
sahilmgandhi 18:6a4db94011d3 415 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 416 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 417 * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be
sahilmgandhi 18:6a4db94011d3 418 * configured.
sahilmgandhi 18:6a4db94011d3 419 */
sahilmgandhi 18:6a4db94011d3 420 void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 421 const uint32_t ul_multi_driver_enable)
sahilmgandhi 18:6a4db94011d3 422 {
sahilmgandhi 18:6a4db94011d3 423 /* Enable the multi-driver if necessary */
sahilmgandhi 18:6a4db94011d3 424 if (ul_multi_driver_enable) {
sahilmgandhi 18:6a4db94011d3 425 p_pio->PIO_MDER = ul_mask;
sahilmgandhi 18:6a4db94011d3 426 } else {
sahilmgandhi 18:6a4db94011d3 427 p_pio->PIO_MDDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 428 }
sahilmgandhi 18:6a4db94011d3 429 }
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 /**
sahilmgandhi 18:6a4db94011d3 432 * \brief Get multi-driver status.
sahilmgandhi 18:6a4db94011d3 433 *
sahilmgandhi 18:6a4db94011d3 434 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 435 *
sahilmgandhi 18:6a4db94011d3 436 * \return The multi-driver mask value.
sahilmgandhi 18:6a4db94011d3 437 */
sahilmgandhi 18:6a4db94011d3 438 uint32_t pio_get_multi_driver_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 439 {
sahilmgandhi 18:6a4db94011d3 440 return p_pio->PIO_MDSR;
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 445 /**
sahilmgandhi 18:6a4db94011d3 446 * \brief Configure PIO pin internal pull-down.
sahilmgandhi 18:6a4db94011d3 447 *
sahilmgandhi 18:6a4db94011d3 448 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 449 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 450 * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall
sahilmgandhi 18:6a4db94011d3 451 * be configured.
sahilmgandhi 18:6a4db94011d3 452 */
sahilmgandhi 18:6a4db94011d3 453 void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 454 const uint32_t ul_pull_down_enable)
sahilmgandhi 18:6a4db94011d3 455 {
sahilmgandhi 18:6a4db94011d3 456 /* Enable the pull-down if necessary */
sahilmgandhi 18:6a4db94011d3 457 if (ul_pull_down_enable) {
sahilmgandhi 18:6a4db94011d3 458 p_pio->PIO_PPDER = ul_mask;
sahilmgandhi 18:6a4db94011d3 459 } else {
sahilmgandhi 18:6a4db94011d3 460 p_pio->PIO_PPDDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 461 }
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463 #endif
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /**
sahilmgandhi 18:6a4db94011d3 466 * \brief Enable PIO output write for synchronous data output.
sahilmgandhi 18:6a4db94011d3 467 *
sahilmgandhi 18:6a4db94011d3 468 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 469 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 470 */
sahilmgandhi 18:6a4db94011d3 471 void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 472 {
sahilmgandhi 18:6a4db94011d3 473 p_pio->PIO_OWER = ul_mask;
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /**
sahilmgandhi 18:6a4db94011d3 477 * \brief Disable PIO output write.
sahilmgandhi 18:6a4db94011d3 478 *
sahilmgandhi 18:6a4db94011d3 479 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 480 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482 void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 483 {
sahilmgandhi 18:6a4db94011d3 484 p_pio->PIO_OWDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 485 }
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /**
sahilmgandhi 18:6a4db94011d3 488 * \brief Read PIO output write status.
sahilmgandhi 18:6a4db94011d3 489 *
sahilmgandhi 18:6a4db94011d3 490 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 491 *
sahilmgandhi 18:6a4db94011d3 492 * \return The output write mask value.
sahilmgandhi 18:6a4db94011d3 493 */
sahilmgandhi 18:6a4db94011d3 494 uint32_t pio_get_output_write_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 495 {
sahilmgandhi 18:6a4db94011d3 496 return p_pio->PIO_OWSR;
sahilmgandhi 18:6a4db94011d3 497 }
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /**
sahilmgandhi 18:6a4db94011d3 500 * \brief Synchronously write on output pins.
sahilmgandhi 18:6a4db94011d3 501 * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are
sahilmgandhi 18:6a4db94011d3 502 * written.
sahilmgandhi 18:6a4db94011d3 503 *
sahilmgandhi 18:6a4db94011d3 504 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 505 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 506 */
sahilmgandhi 18:6a4db94011d3 507 void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 p_pio->PIO_ODSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 513 /**
sahilmgandhi 18:6a4db94011d3 514 * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is
sahilmgandhi 18:6a4db94011d3 515 * active.
sahilmgandhi 18:6a4db94011d3 516 * Disabling the Schmitt Trigger is requested when using the QTouch Library.
sahilmgandhi 18:6a4db94011d3 517 *
sahilmgandhi 18:6a4db94011d3 518 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 519 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 520 */
sahilmgandhi 18:6a4db94011d3 521 void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 522 {
sahilmgandhi 18:6a4db94011d3 523 p_pio->PIO_SCHMITT = ul_mask;
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 /**
sahilmgandhi 18:6a4db94011d3 527 * \brief Get PIO pin schmitt trigger status.
sahilmgandhi 18:6a4db94011d3 528 *
sahilmgandhi 18:6a4db94011d3 529 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 530 *
sahilmgandhi 18:6a4db94011d3 531 * \return The schmitt trigger mask value.
sahilmgandhi 18:6a4db94011d3 532 */
sahilmgandhi 18:6a4db94011d3 533 uint32_t pio_get_schmitt_trigger(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 534 {
sahilmgandhi 18:6a4db94011d3 535 return p_pio->PIO_SCHMITT;
sahilmgandhi 18:6a4db94011d3 536 }
sahilmgandhi 18:6a4db94011d3 537 #endif
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 /**
sahilmgandhi 18:6a4db94011d3 540 * \brief Configure the given interrupt source.
sahilmgandhi 18:6a4db94011d3 541 * Interrupt can be configured to trigger on rising edge, falling edge,
sahilmgandhi 18:6a4db94011d3 542 * high level, low level or simply on level change.
sahilmgandhi 18:6a4db94011d3 543 *
sahilmgandhi 18:6a4db94011d3 544 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 545 * \param ul_mask Interrupt source bit map.
sahilmgandhi 18:6a4db94011d3 546 * \param ul_attr Interrupt source attributes.
sahilmgandhi 18:6a4db94011d3 547 */
sahilmgandhi 18:6a4db94011d3 548 void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,
sahilmgandhi 18:6a4db94011d3 549 const uint32_t ul_attr)
sahilmgandhi 18:6a4db94011d3 550 {
sahilmgandhi 18:6a4db94011d3 551 /* Configure additional interrupt mode registers. */
sahilmgandhi 18:6a4db94011d3 552 if (ul_attr & PIO_IT_AIME) {
sahilmgandhi 18:6a4db94011d3 553 /* Enable additional interrupt mode. */
sahilmgandhi 18:6a4db94011d3 554 p_pio->PIO_AIMER = ul_mask;
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* If bit field of the selected pin is 1, set as
sahilmgandhi 18:6a4db94011d3 557 Rising Edge/High level detection event. */
sahilmgandhi 18:6a4db94011d3 558 if (ul_attr & PIO_IT_RE_OR_HL) {
sahilmgandhi 18:6a4db94011d3 559 /* Rising Edge or High Level */
sahilmgandhi 18:6a4db94011d3 560 p_pio->PIO_REHLSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 561 } else {
sahilmgandhi 18:6a4db94011d3 562 /* Falling Edge or Low Level */
sahilmgandhi 18:6a4db94011d3 563 p_pio->PIO_FELLSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 564 }
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* If bit field of the selected pin is 1, set as
sahilmgandhi 18:6a4db94011d3 567 edge detection source. */
sahilmgandhi 18:6a4db94011d3 568 if (ul_attr & PIO_IT_EDGE) {
sahilmgandhi 18:6a4db94011d3 569 /* Edge select */
sahilmgandhi 18:6a4db94011d3 570 p_pio->PIO_ESR = ul_mask;
sahilmgandhi 18:6a4db94011d3 571 } else {
sahilmgandhi 18:6a4db94011d3 572 /* Level select */
sahilmgandhi 18:6a4db94011d3 573 p_pio->PIO_LSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 574 }
sahilmgandhi 18:6a4db94011d3 575 } else {
sahilmgandhi 18:6a4db94011d3 576 /* Disable additional interrupt mode. */
sahilmgandhi 18:6a4db94011d3 577 p_pio->PIO_AIMDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /**
sahilmgandhi 18:6a4db94011d3 582 * \brief Enable the given interrupt source.
sahilmgandhi 18:6a4db94011d3 583 * The PIO must be configured as an NVIC interrupt source as well.
sahilmgandhi 18:6a4db94011d3 584 * The status register of the corresponding PIO controller is cleared
sahilmgandhi 18:6a4db94011d3 585 * prior to enabling the interrupt.
sahilmgandhi 18:6a4db94011d3 586 *
sahilmgandhi 18:6a4db94011d3 587 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 588 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 589 */
sahilmgandhi 18:6a4db94011d3 590 void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 591 {
sahilmgandhi 18:6a4db94011d3 592 p_pio->PIO_ISR;
sahilmgandhi 18:6a4db94011d3 593 p_pio->PIO_IER = ul_mask;
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /**
sahilmgandhi 18:6a4db94011d3 597 * \brief Disable a given interrupt source, with no added side effects.
sahilmgandhi 18:6a4db94011d3 598 *
sahilmgandhi 18:6a4db94011d3 599 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 600 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 601 */
sahilmgandhi 18:6a4db94011d3 602 void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 p_pio->PIO_IDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /**
sahilmgandhi 18:6a4db94011d3 608 * \brief Read PIO interrupt status.
sahilmgandhi 18:6a4db94011d3 609 *
sahilmgandhi 18:6a4db94011d3 610 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 611 *
sahilmgandhi 18:6a4db94011d3 612 * \return The interrupt status mask value.
sahilmgandhi 18:6a4db94011d3 613 */
sahilmgandhi 18:6a4db94011d3 614 uint32_t pio_get_interrupt_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 615 {
sahilmgandhi 18:6a4db94011d3 616 return p_pio->PIO_ISR;
sahilmgandhi 18:6a4db94011d3 617 }
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 /**
sahilmgandhi 18:6a4db94011d3 620 * \brief Read PIO interrupt mask.
sahilmgandhi 18:6a4db94011d3 621 *
sahilmgandhi 18:6a4db94011d3 622 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 623 *
sahilmgandhi 18:6a4db94011d3 624 * \return The interrupt mask value.
sahilmgandhi 18:6a4db94011d3 625 */
sahilmgandhi 18:6a4db94011d3 626 uint32_t pio_get_interrupt_mask(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 627 {
sahilmgandhi 18:6a4db94011d3 628 return p_pio->PIO_IMR;
sahilmgandhi 18:6a4db94011d3 629 }
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 /**
sahilmgandhi 18:6a4db94011d3 632 * \brief Set additional interrupt mode.
sahilmgandhi 18:6a4db94011d3 633 *
sahilmgandhi 18:6a4db94011d3 634 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 635 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 636 * \param ul_attribute Pin(s) attributes.
sahilmgandhi 18:6a4db94011d3 637 */
sahilmgandhi 18:6a4db94011d3 638 void pio_set_additional_interrupt_mode(Pio *p_pio,
sahilmgandhi 18:6a4db94011d3 639 const uint32_t ul_mask, const uint32_t ul_attribute)
sahilmgandhi 18:6a4db94011d3 640 {
sahilmgandhi 18:6a4db94011d3 641 /* Enables additional interrupt mode if needed */
sahilmgandhi 18:6a4db94011d3 642 if (ul_attribute & PIO_IT_AIME) {
sahilmgandhi 18:6a4db94011d3 643 /* Enables additional interrupt mode */
sahilmgandhi 18:6a4db94011d3 644 p_pio->PIO_AIMER = ul_mask;
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /* Configures the Polarity of the event detection */
sahilmgandhi 18:6a4db94011d3 647 /* (Rising/Falling Edge or High/Low Level) */
sahilmgandhi 18:6a4db94011d3 648 if (ul_attribute & PIO_IT_RE_OR_HL) {
sahilmgandhi 18:6a4db94011d3 649 /* Rising Edge or High Level */
sahilmgandhi 18:6a4db94011d3 650 p_pio->PIO_REHLSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 651 } else {
sahilmgandhi 18:6a4db94011d3 652 /* Falling Edge or Low Level */
sahilmgandhi 18:6a4db94011d3 653 p_pio->PIO_FELLSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /* Configures the type of event detection (Edge or Level) */
sahilmgandhi 18:6a4db94011d3 657 if (ul_attribute & PIO_IT_EDGE) {
sahilmgandhi 18:6a4db94011d3 658 /* Edge select */
sahilmgandhi 18:6a4db94011d3 659 p_pio->PIO_ESR = ul_mask;
sahilmgandhi 18:6a4db94011d3 660 } else {
sahilmgandhi 18:6a4db94011d3 661 /* Level select */
sahilmgandhi 18:6a4db94011d3 662 p_pio->PIO_LSR = ul_mask;
sahilmgandhi 18:6a4db94011d3 663 }
sahilmgandhi 18:6a4db94011d3 664 } else {
sahilmgandhi 18:6a4db94011d3 665 /* Disable additional interrupt mode */
sahilmgandhi 18:6a4db94011d3 666 p_pio->PIO_AIMDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 667 }
sahilmgandhi 18:6a4db94011d3 668 }
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 #ifndef PIO_WPMR_WPKEY_PASSWD
sahilmgandhi 18:6a4db94011d3 671 #define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU)
sahilmgandhi 18:6a4db94011d3 672 #endif
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /**
sahilmgandhi 18:6a4db94011d3 675 * \brief Enable or disable write protect of PIO registers.
sahilmgandhi 18:6a4db94011d3 676 *
sahilmgandhi 18:6a4db94011d3 677 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 678 * \param ul_enable 1 to enable, 0 to disable.
sahilmgandhi 18:6a4db94011d3 679 */
sahilmgandhi 18:6a4db94011d3 680 void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN);
sahilmgandhi 18:6a4db94011d3 683 }
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /**
sahilmgandhi 18:6a4db94011d3 686 * \brief Read write protect status.
sahilmgandhi 18:6a4db94011d3 687 *
sahilmgandhi 18:6a4db94011d3 688 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 689 *
sahilmgandhi 18:6a4db94011d3 690 * \return Return write protect status.
sahilmgandhi 18:6a4db94011d3 691 */
sahilmgandhi 18:6a4db94011d3 692 uint32_t pio_get_writeprotect_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 return p_pio->PIO_WPSR;
sahilmgandhi 18:6a4db94011d3 695 }
sahilmgandhi 18:6a4db94011d3 696
sahilmgandhi 18:6a4db94011d3 697 /**
sahilmgandhi 18:6a4db94011d3 698 * \brief Return the value of a pin.
sahilmgandhi 18:6a4db94011d3 699 *
sahilmgandhi 18:6a4db94011d3 700 * \param ul_pin The pin number.
sahilmgandhi 18:6a4db94011d3 701 *
sahilmgandhi 18:6a4db94011d3 702 * \return The pin value.
sahilmgandhi 18:6a4db94011d3 703 *
sahilmgandhi 18:6a4db94011d3 704 * \note If pin is output: a pull-up or pull-down could hide the actual value.
sahilmgandhi 18:6a4db94011d3 705 * The function \ref pio_get can be called to get the actual pin output
sahilmgandhi 18:6a4db94011d3 706 * level.
sahilmgandhi 18:6a4db94011d3 707 * \note If pin is input: PIOx must be clocked to sample the signal.
sahilmgandhi 18:6a4db94011d3 708 * See PMC driver.
sahilmgandhi 18:6a4db94011d3 709 */
sahilmgandhi 18:6a4db94011d3 710 uint32_t pio_get_pin_value(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 711 {
sahilmgandhi 18:6a4db94011d3 712 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /**
sahilmgandhi 18:6a4db94011d3 718 * \brief Drive a GPIO pin to 1.
sahilmgandhi 18:6a4db94011d3 719 *
sahilmgandhi 18:6a4db94011d3 720 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 721 *
sahilmgandhi 18:6a4db94011d3 722 * \note The function \ref pio_configure_pin must be called beforehand.
sahilmgandhi 18:6a4db94011d3 723 */
sahilmgandhi 18:6a4db94011d3 724 void pio_set_pin_high(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 725 {
sahilmgandhi 18:6a4db94011d3 726 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 /* Value to be driven on the I/O line: 1. */
sahilmgandhi 18:6a4db94011d3 729 p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /**
sahilmgandhi 18:6a4db94011d3 733 * \brief Drive a GPIO pin to 0.
sahilmgandhi 18:6a4db94011d3 734 *
sahilmgandhi 18:6a4db94011d3 735 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 736 *
sahilmgandhi 18:6a4db94011d3 737 * \note The function \ref pio_configure_pin must be called before.
sahilmgandhi 18:6a4db94011d3 738 */
sahilmgandhi 18:6a4db94011d3 739 void pio_set_pin_low(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 740 {
sahilmgandhi 18:6a4db94011d3 741 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 /* Value to be driven on the I/O line: 0. */
sahilmgandhi 18:6a4db94011d3 744 p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 745 }
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 /**
sahilmgandhi 18:6a4db94011d3 748 * \brief Toggle a GPIO pin.
sahilmgandhi 18:6a4db94011d3 749 *
sahilmgandhi 18:6a4db94011d3 750 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 751 *
sahilmgandhi 18:6a4db94011d3 752 * \note The function \ref pio_configure_pin must be called before.
sahilmgandhi 18:6a4db94011d3 753 */
sahilmgandhi 18:6a4db94011d3 754 void pio_toggle_pin(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 755 {
sahilmgandhi 18:6a4db94011d3 756 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {
sahilmgandhi 18:6a4db94011d3 759 /* Value to be driven on the I/O line: 0. */
sahilmgandhi 18:6a4db94011d3 760 p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 761 } else {
sahilmgandhi 18:6a4db94011d3 762 /* Value to be driven on the I/O line: 1. */
sahilmgandhi 18:6a4db94011d3 763 p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765 }
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /**
sahilmgandhi 18:6a4db94011d3 768 * \brief Perform complete pin(s) configuration; general attributes and PIO init
sahilmgandhi 18:6a4db94011d3 769 * if necessary.
sahilmgandhi 18:6a4db94011d3 770 *
sahilmgandhi 18:6a4db94011d3 771 * \param ul_pin Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 772 * \param ul_flags Pins attributes.
sahilmgandhi 18:6a4db94011d3 773 *
sahilmgandhi 18:6a4db94011d3 774 * \return Whether the pin(s) have been configured properly.
sahilmgandhi 18:6a4db94011d3 775 */
sahilmgandhi 18:6a4db94011d3 776 uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)
sahilmgandhi 18:6a4db94011d3 777 {
sahilmgandhi 18:6a4db94011d3 778 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 /* Configure pins */
sahilmgandhi 18:6a4db94011d3 781 switch (ul_flags & PIO_TYPE_Msk) {
sahilmgandhi 18:6a4db94011d3 782 case PIO_TYPE_PIO_PERIPH_A:
sahilmgandhi 18:6a4db94011d3 783 pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));
sahilmgandhi 18:6a4db94011d3 784 pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
sahilmgandhi 18:6a4db94011d3 785 (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 786 break;
sahilmgandhi 18:6a4db94011d3 787 case PIO_TYPE_PIO_PERIPH_B:
sahilmgandhi 18:6a4db94011d3 788 pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));
sahilmgandhi 18:6a4db94011d3 789 pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
sahilmgandhi 18:6a4db94011d3 790 (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 791 break;
sahilmgandhi 18:6a4db94011d3 792 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 793 case PIO_TYPE_PIO_PERIPH_C:
sahilmgandhi 18:6a4db94011d3 794 pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));
sahilmgandhi 18:6a4db94011d3 795 pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
sahilmgandhi 18:6a4db94011d3 796 (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 797 break;
sahilmgandhi 18:6a4db94011d3 798 case PIO_TYPE_PIO_PERIPH_D:
sahilmgandhi 18:6a4db94011d3 799 pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));
sahilmgandhi 18:6a4db94011d3 800 pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
sahilmgandhi 18:6a4db94011d3 801 (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 802 break;
sahilmgandhi 18:6a4db94011d3 803 #endif
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 case PIO_TYPE_PIO_INPUT:
sahilmgandhi 18:6a4db94011d3 806 pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);
sahilmgandhi 18:6a4db94011d3 807 break;
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 case PIO_TYPE_PIO_OUTPUT_0:
sahilmgandhi 18:6a4db94011d3 810 case PIO_TYPE_PIO_OUTPUT_1:
sahilmgandhi 18:6a4db94011d3 811 pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),
sahilmgandhi 18:6a4db94011d3 812 ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
sahilmgandhi 18:6a4db94011d3 813 == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
sahilmgandhi 18:6a4db94011d3 814 (ul_flags & PIO_OPENDRAIN) ? 1 : 0,
sahilmgandhi 18:6a4db94011d3 815 (ul_flags & PIO_PULLUP) ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 816 break;
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 default:
sahilmgandhi 18:6a4db94011d3 819 return 0;
sahilmgandhi 18:6a4db94011d3 820 }
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 return 1;
sahilmgandhi 18:6a4db94011d3 823 }
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 /**
sahilmgandhi 18:6a4db94011d3 826 * \brief Drive a GPIO port to 1.
sahilmgandhi 18:6a4db94011d3 827 *
sahilmgandhi 18:6a4db94011d3 828 * \param p_pio Base address of the PIO port.
sahilmgandhi 18:6a4db94011d3 829 * \param ul_mask Bitmask of one or more pin(s) to toggle.
sahilmgandhi 18:6a4db94011d3 830 */
sahilmgandhi 18:6a4db94011d3 831 void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 832 {
sahilmgandhi 18:6a4db94011d3 833 /* Value to be driven on the I/O line: 1. */
sahilmgandhi 18:6a4db94011d3 834 p_pio->PIO_SODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 835 }
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 /**
sahilmgandhi 18:6a4db94011d3 838 * \brief Drive a GPIO port to 0.
sahilmgandhi 18:6a4db94011d3 839 *
sahilmgandhi 18:6a4db94011d3 840 * \param p_pio Base address of the PIO port.
sahilmgandhi 18:6a4db94011d3 841 * \param ul_mask Bitmask of one or more pin(s) to toggle.
sahilmgandhi 18:6a4db94011d3 842 */
sahilmgandhi 18:6a4db94011d3 843 void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 844 {
sahilmgandhi 18:6a4db94011d3 845 /* Value to be driven on the I/O line: 0. */
sahilmgandhi 18:6a4db94011d3 846 p_pio->PIO_CODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 847 }
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 /**
sahilmgandhi 18:6a4db94011d3 850 * \brief Toggle a GPIO group.
sahilmgandhi 18:6a4db94011d3 851 *
sahilmgandhi 18:6a4db94011d3 852 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 853 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 854 */
sahilmgandhi 18:6a4db94011d3 855 void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 856 {
sahilmgandhi 18:6a4db94011d3 857 if (p_pio->PIO_ODSR & ul_mask) {
sahilmgandhi 18:6a4db94011d3 858 /* Value to be driven on the I/O line: 0. */
sahilmgandhi 18:6a4db94011d3 859 p_pio->PIO_CODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 860 } else {
sahilmgandhi 18:6a4db94011d3 861 /* Value to be driven on the I/O line: 1. */
sahilmgandhi 18:6a4db94011d3 862 p_pio->PIO_SODR = ul_mask;
sahilmgandhi 18:6a4db94011d3 863 }
sahilmgandhi 18:6a4db94011d3 864 }
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /**
sahilmgandhi 18:6a4db94011d3 867 * \brief Perform complete pin(s) configuration; general attributes and PIO init
sahilmgandhi 18:6a4db94011d3 868 * if necessary.
sahilmgandhi 18:6a4db94011d3 869 *
sahilmgandhi 18:6a4db94011d3 870 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 871 * \param ul_mask Bitmask of one or more pin(s) to configure.
sahilmgandhi 18:6a4db94011d3 872 * \param ul_flags Pin(s) attributes.
sahilmgandhi 18:6a4db94011d3 873 *
sahilmgandhi 18:6a4db94011d3 874 * \return Whether the pin(s) have been configured properly.
sahilmgandhi 18:6a4db94011d3 875 */
sahilmgandhi 18:6a4db94011d3 876 uint32_t pio_configure_pin_group(Pio *p_pio,
sahilmgandhi 18:6a4db94011d3 877 uint32_t ul_mask, const uint32_t ul_flags)
sahilmgandhi 18:6a4db94011d3 878 {
sahilmgandhi 18:6a4db94011d3 879 /* Configure pins */
sahilmgandhi 18:6a4db94011d3 880 switch (ul_flags & PIO_TYPE_Msk) {
sahilmgandhi 18:6a4db94011d3 881 case PIO_TYPE_PIO_PERIPH_A:
sahilmgandhi 18:6a4db94011d3 882 pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);
sahilmgandhi 18:6a4db94011d3 883 pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 884 break;
sahilmgandhi 18:6a4db94011d3 885 case PIO_TYPE_PIO_PERIPH_B:
sahilmgandhi 18:6a4db94011d3 886 pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);
sahilmgandhi 18:6a4db94011d3 887 pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 888 break;
sahilmgandhi 18:6a4db94011d3 889 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 890 case PIO_TYPE_PIO_PERIPH_C:
sahilmgandhi 18:6a4db94011d3 891 pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);
sahilmgandhi 18:6a4db94011d3 892 pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 893 break;
sahilmgandhi 18:6a4db94011d3 894 case PIO_TYPE_PIO_PERIPH_D:
sahilmgandhi 18:6a4db94011d3 895 pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);
sahilmgandhi 18:6a4db94011d3 896 pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
sahilmgandhi 18:6a4db94011d3 897 break;
sahilmgandhi 18:6a4db94011d3 898 #endif
sahilmgandhi 18:6a4db94011d3 899
sahilmgandhi 18:6a4db94011d3 900 case PIO_TYPE_PIO_INPUT:
sahilmgandhi 18:6a4db94011d3 901 pio_set_input(p_pio, ul_mask, ul_flags);
sahilmgandhi 18:6a4db94011d3 902 break;
sahilmgandhi 18:6a4db94011d3 903
sahilmgandhi 18:6a4db94011d3 904 case PIO_TYPE_PIO_OUTPUT_0:
sahilmgandhi 18:6a4db94011d3 905 case PIO_TYPE_PIO_OUTPUT_1:
sahilmgandhi 18:6a4db94011d3 906 pio_set_output(p_pio, ul_mask,
sahilmgandhi 18:6a4db94011d3 907 ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
sahilmgandhi 18:6a4db94011d3 908 == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
sahilmgandhi 18:6a4db94011d3 909 (ul_flags & PIO_OPENDRAIN) ? 1 : 0,
sahilmgandhi 18:6a4db94011d3 910 (ul_flags & PIO_PULLUP) ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 911 break;
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 default:
sahilmgandhi 18:6a4db94011d3 914 return 0;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 return 1;
sahilmgandhi 18:6a4db94011d3 918 }
sahilmgandhi 18:6a4db94011d3 919
sahilmgandhi 18:6a4db94011d3 920 /**
sahilmgandhi 18:6a4db94011d3 921 * \brief Enable interrupt for a GPIO pin.
sahilmgandhi 18:6a4db94011d3 922 *
sahilmgandhi 18:6a4db94011d3 923 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 924 *
sahilmgandhi 18:6a4db94011d3 925 * \note The function \ref gpio_configure_pin must be called before.
sahilmgandhi 18:6a4db94011d3 926 */
sahilmgandhi 18:6a4db94011d3 927 void pio_enable_pin_interrupt(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 928 {
sahilmgandhi 18:6a4db94011d3 929 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 p_pio->PIO_IER = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934
sahilmgandhi 18:6a4db94011d3 935 /**
sahilmgandhi 18:6a4db94011d3 936 * \brief Disable interrupt for a GPIO pin.
sahilmgandhi 18:6a4db94011d3 937 *
sahilmgandhi 18:6a4db94011d3 938 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 939 *
sahilmgandhi 18:6a4db94011d3 940 * \note The function \ref gpio_configure_pin must be called before.
sahilmgandhi 18:6a4db94011d3 941 */
sahilmgandhi 18:6a4db94011d3 942 void pio_disable_pin_interrupt(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 943 {
sahilmgandhi 18:6a4db94011d3 944 Pio *p_pio = pio_get_pin_group(ul_pin);
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946 p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 947 }
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949
sahilmgandhi 18:6a4db94011d3 950 /**
sahilmgandhi 18:6a4db94011d3 951 * \brief Return GPIO port for a GPIO pin.
sahilmgandhi 18:6a4db94011d3 952 *
sahilmgandhi 18:6a4db94011d3 953 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 954 *
sahilmgandhi 18:6a4db94011d3 955 * \return Pointer to \ref Pio struct for GPIO port.
sahilmgandhi 18:6a4db94011d3 956 */
sahilmgandhi 18:6a4db94011d3 957 Pio *pio_get_pin_group(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 Pio *p_pio;
sahilmgandhi 18:6a4db94011d3 960
sahilmgandhi 18:6a4db94011d3 961 #if (SAM4C || SAM4CP)
sahilmgandhi 18:6a4db94011d3 962 # ifdef ID_PIOD
sahilmgandhi 18:6a4db94011d3 963 if (ul_pin > PIO_PC9_IDX) {
sahilmgandhi 18:6a4db94011d3 964 p_pio = PIOD;
sahilmgandhi 18:6a4db94011d3 965 } else if (ul_pin > PIO_PB31_IDX) {
sahilmgandhi 18:6a4db94011d3 966 # else
sahilmgandhi 18:6a4db94011d3 967 if (ul_pin > PIO_PB31_IDX) {
sahilmgandhi 18:6a4db94011d3 968 # endif
sahilmgandhi 18:6a4db94011d3 969 p_pio = PIOC;
sahilmgandhi 18:6a4db94011d3 970 } else {
sahilmgandhi 18:6a4db94011d3 971 p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
sahilmgandhi 18:6a4db94011d3 972 }
sahilmgandhi 18:6a4db94011d3 973 #elif (SAM4CM)
sahilmgandhi 18:6a4db94011d3 974 if (ul_pin > PIO_PB21_IDX) {
sahilmgandhi 18:6a4db94011d3 975 p_pio = PIOC;
sahilmgandhi 18:6a4db94011d3 976 } else {
sahilmgandhi 18:6a4db94011d3 977 p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
sahilmgandhi 18:6a4db94011d3 978 }
sahilmgandhi 18:6a4db94011d3 979 #else
sahilmgandhi 18:6a4db94011d3 980 p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
sahilmgandhi 18:6a4db94011d3 981 #endif
sahilmgandhi 18:6a4db94011d3 982 return p_pio;
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 /**
sahilmgandhi 18:6a4db94011d3 986 * \brief Return GPIO port peripheral ID for a GPIO pin.
sahilmgandhi 18:6a4db94011d3 987 *
sahilmgandhi 18:6a4db94011d3 988 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 989 *
sahilmgandhi 18:6a4db94011d3 990 * \return GPIO port peripheral ID.
sahilmgandhi 18:6a4db94011d3 991 */
sahilmgandhi 18:6a4db94011d3 992 uint32_t pio_get_pin_group_id(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 993 {
sahilmgandhi 18:6a4db94011d3 994 uint32_t ul_id;
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 #if (SAM4C || SAM4CP)
sahilmgandhi 18:6a4db94011d3 997 # ifdef ID_PIOD
sahilmgandhi 18:6a4db94011d3 998 if (ul_pin > PIO_PC9_IDX) {
sahilmgandhi 18:6a4db94011d3 999 ul_id = ID_PIOD;
sahilmgandhi 18:6a4db94011d3 1000 } else if (ul_pin > PIO_PB31_IDX) {
sahilmgandhi 18:6a4db94011d3 1001 # else
sahilmgandhi 18:6a4db94011d3 1002 if (ul_pin > PIO_PB31_IDX) {
sahilmgandhi 18:6a4db94011d3 1003 # endif
sahilmgandhi 18:6a4db94011d3 1004 ul_id = ID_PIOC;
sahilmgandhi 18:6a4db94011d3 1005 } else {
sahilmgandhi 18:6a4db94011d3 1006 ul_id = ID_PIOA + (ul_pin >> 5);
sahilmgandhi 18:6a4db94011d3 1007 }
sahilmgandhi 18:6a4db94011d3 1008 #elif (SAM4CM)
sahilmgandhi 18:6a4db94011d3 1009 if (ul_pin > PIO_PB21_IDX) {
sahilmgandhi 18:6a4db94011d3 1010 ul_id = ID_PIOC;
sahilmgandhi 18:6a4db94011d3 1011 } else {
sahilmgandhi 18:6a4db94011d3 1012 ul_id = ID_PIOA + (ul_pin >> 5);
sahilmgandhi 18:6a4db94011d3 1013 }
sahilmgandhi 18:6a4db94011d3 1014 #else
sahilmgandhi 18:6a4db94011d3 1015 ul_id = ID_PIOA + (ul_pin >> 5);
sahilmgandhi 18:6a4db94011d3 1016 #endif
sahilmgandhi 18:6a4db94011d3 1017 return ul_id;
sahilmgandhi 18:6a4db94011d3 1018 }
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 /**
sahilmgandhi 18:6a4db94011d3 1022 * \brief Return GPIO port pin mask for a GPIO pin.
sahilmgandhi 18:6a4db94011d3 1023 *
sahilmgandhi 18:6a4db94011d3 1024 * \param ul_pin The pin index.
sahilmgandhi 18:6a4db94011d3 1025 *
sahilmgandhi 18:6a4db94011d3 1026 * \return GPIO port pin mask.
sahilmgandhi 18:6a4db94011d3 1027 */
sahilmgandhi 18:6a4db94011d3 1028 uint32_t pio_get_pin_group_mask(uint32_t ul_pin)
sahilmgandhi 18:6a4db94011d3 1029 {
sahilmgandhi 18:6a4db94011d3 1030 uint32_t ul_mask = 1 << (ul_pin & 0x1F);
sahilmgandhi 18:6a4db94011d3 1031 return ul_mask;
sahilmgandhi 18:6a4db94011d3 1032 }
sahilmgandhi 18:6a4db94011d3 1033
sahilmgandhi 18:6a4db94011d3 1034 #if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1035 /* Capture mode enable flag */
sahilmgandhi 18:6a4db94011d3 1036 uint32_t pio_capture_enable_flag;
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 /**
sahilmgandhi 18:6a4db94011d3 1039 * \brief Configure PIO capture mode.
sahilmgandhi 18:6a4db94011d3 1040 * \note PIO capture mode will be disabled automatically.
sahilmgandhi 18:6a4db94011d3 1041 *
sahilmgandhi 18:6a4db94011d3 1042 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1043 * \param ul_mode Bitmask of one or more modes.
sahilmgandhi 18:6a4db94011d3 1044 */
sahilmgandhi 18:6a4db94011d3 1045 void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)
sahilmgandhi 18:6a4db94011d3 1046 {
sahilmgandhi 18:6a4db94011d3 1047 ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */
sahilmgandhi 18:6a4db94011d3 1048 p_pio->PIO_PCMR = ul_mode;
sahilmgandhi 18:6a4db94011d3 1049 }
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 /**
sahilmgandhi 18:6a4db94011d3 1052 * \brief Enable PIO capture mode.
sahilmgandhi 18:6a4db94011d3 1053 *
sahilmgandhi 18:6a4db94011d3 1054 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1055 */
sahilmgandhi 18:6a4db94011d3 1056 void pio_capture_enable(Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 p_pio->PIO_PCMR |= PIO_PCMR_PCEN;
sahilmgandhi 18:6a4db94011d3 1059 pio_capture_enable_flag = true;
sahilmgandhi 18:6a4db94011d3 1060 }
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /**
sahilmgandhi 18:6a4db94011d3 1063 * \brief Disable PIO capture mode.
sahilmgandhi 18:6a4db94011d3 1064 *
sahilmgandhi 18:6a4db94011d3 1065 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1066 */
sahilmgandhi 18:6a4db94011d3 1067 void pio_capture_disable(Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1068 {
sahilmgandhi 18:6a4db94011d3 1069 p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);
sahilmgandhi 18:6a4db94011d3 1070 pio_capture_enable_flag = false;
sahilmgandhi 18:6a4db94011d3 1071 }
sahilmgandhi 18:6a4db94011d3 1072
sahilmgandhi 18:6a4db94011d3 1073 /**
sahilmgandhi 18:6a4db94011d3 1074 * \brief Read from Capture Reception Holding Register.
sahilmgandhi 18:6a4db94011d3 1075 * \note Data presence should be tested before any read attempt.
sahilmgandhi 18:6a4db94011d3 1076 *
sahilmgandhi 18:6a4db94011d3 1077 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1078 * \param pul_data Pointer to store the data.
sahilmgandhi 18:6a4db94011d3 1079 *
sahilmgandhi 18:6a4db94011d3 1080 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 1081 * \retval 1 I/O Failure, Capture data is not ready.
sahilmgandhi 18:6a4db94011d3 1082 */
sahilmgandhi 18:6a4db94011d3 1083 uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)
sahilmgandhi 18:6a4db94011d3 1084 {
sahilmgandhi 18:6a4db94011d3 1085 /* Check if the data is ready */
sahilmgandhi 18:6a4db94011d3 1086 if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {
sahilmgandhi 18:6a4db94011d3 1087 return 1;
sahilmgandhi 18:6a4db94011d3 1088 }
sahilmgandhi 18:6a4db94011d3 1089
sahilmgandhi 18:6a4db94011d3 1090 /* Read data */
sahilmgandhi 18:6a4db94011d3 1091 *pul_data = p_pio->PIO_PCRHR;
sahilmgandhi 18:6a4db94011d3 1092 return 0;
sahilmgandhi 18:6a4db94011d3 1093 }
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /**
sahilmgandhi 18:6a4db94011d3 1096 * \brief Enable the given interrupt source of PIO capture. The status
sahilmgandhi 18:6a4db94011d3 1097 * register of the corresponding PIO capture controller is cleared prior
sahilmgandhi 18:6a4db94011d3 1098 * to enabling the interrupt.
sahilmgandhi 18:6a4db94011d3 1099 *
sahilmgandhi 18:6a4db94011d3 1100 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1101 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1102 */
sahilmgandhi 18:6a4db94011d3 1103 void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 1104 {
sahilmgandhi 18:6a4db94011d3 1105 p_pio->PIO_PCISR;
sahilmgandhi 18:6a4db94011d3 1106 p_pio->PIO_PCIER = ul_mask;
sahilmgandhi 18:6a4db94011d3 1107 }
sahilmgandhi 18:6a4db94011d3 1108
sahilmgandhi 18:6a4db94011d3 1109 /**
sahilmgandhi 18:6a4db94011d3 1110 * \brief Disable a given interrupt source of PIO capture.
sahilmgandhi 18:6a4db94011d3 1111 *
sahilmgandhi 18:6a4db94011d3 1112 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1113 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1114 */
sahilmgandhi 18:6a4db94011d3 1115 void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 1116 {
sahilmgandhi 18:6a4db94011d3 1117 p_pio->PIO_PCIDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /**
sahilmgandhi 18:6a4db94011d3 1121 * \brief Read PIO interrupt status of PIO capture.
sahilmgandhi 18:6a4db94011d3 1122 *
sahilmgandhi 18:6a4db94011d3 1123 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1124 *
sahilmgandhi 18:6a4db94011d3 1125 * \return The interrupt status mask value.
sahilmgandhi 18:6a4db94011d3 1126 */
sahilmgandhi 18:6a4db94011d3 1127 uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1128 {
sahilmgandhi 18:6a4db94011d3 1129 return p_pio->PIO_PCISR;
sahilmgandhi 18:6a4db94011d3 1130 }
sahilmgandhi 18:6a4db94011d3 1131
sahilmgandhi 18:6a4db94011d3 1132 /**
sahilmgandhi 18:6a4db94011d3 1133 * \brief Read PIO interrupt mask of PIO capture.
sahilmgandhi 18:6a4db94011d3 1134 *
sahilmgandhi 18:6a4db94011d3 1135 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1136 *
sahilmgandhi 18:6a4db94011d3 1137 * \return The interrupt mask value.
sahilmgandhi 18:6a4db94011d3 1138 */
sahilmgandhi 18:6a4db94011d3 1139 uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1140 {
sahilmgandhi 18:6a4db94011d3 1141 return p_pio->PIO_PCIMR;
sahilmgandhi 18:6a4db94011d3 1142 }
sahilmgandhi 18:6a4db94011d3 1143 #if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1144 /**
sahilmgandhi 18:6a4db94011d3 1145 * \brief Get PDC registers base address.
sahilmgandhi 18:6a4db94011d3 1146 *
sahilmgandhi 18:6a4db94011d3 1147 * \param p_pio Pointer to an PIO peripheral.
sahilmgandhi 18:6a4db94011d3 1148 *
sahilmgandhi 18:6a4db94011d3 1149 * \return PIOA PDC register base address.
sahilmgandhi 18:6a4db94011d3 1150 */
sahilmgandhi 18:6a4db94011d3 1151 Pdc *pio_capture_get_pdc_base(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1152 {
sahilmgandhi 18:6a4db94011d3 1153 UNUSED(p_pio); /* Stop warning */
sahilmgandhi 18:6a4db94011d3 1154 return PDC_PIOA;
sahilmgandhi 18:6a4db94011d3 1155 }
sahilmgandhi 18:6a4db94011d3 1156 #endif
sahilmgandhi 18:6a4db94011d3 1157 #endif
sahilmgandhi 18:6a4db94011d3 1158
sahilmgandhi 18:6a4db94011d3 1159 #if (SAM4C || SAM4CP || SAM4CM || SAMG55)
sahilmgandhi 18:6a4db94011d3 1160 /**
sahilmgandhi 18:6a4db94011d3 1161 * \brief Set PIO IO drive.
sahilmgandhi 18:6a4db94011d3 1162 *
sahilmgandhi 18:6a4db94011d3 1163 * \param p_pio Pointer to an PIO peripheral.
sahilmgandhi 18:6a4db94011d3 1164 * \param ul_line Line index (0..31).
sahilmgandhi 18:6a4db94011d3 1165 * \param mode IO drive mode.
sahilmgandhi 18:6a4db94011d3 1166 */
sahilmgandhi 18:6a4db94011d3 1167 void pio_set_io_drive(Pio *p_pio, uint32_t ul_line,
sahilmgandhi 18:6a4db94011d3 1168 enum pio_io_drive_mode mode)
sahilmgandhi 18:6a4db94011d3 1169 {
sahilmgandhi 18:6a4db94011d3 1170 p_pio->PIO_DRIVER &= ~(1 << ul_line);
sahilmgandhi 18:6a4db94011d3 1171 p_pio->PIO_DRIVER |= mode << ul_line;
sahilmgandhi 18:6a4db94011d3 1172 }
sahilmgandhi 18:6a4db94011d3 1173 #endif
sahilmgandhi 18:6a4db94011d3 1174
sahilmgandhi 18:6a4db94011d3 1175 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1176 /**
sahilmgandhi 18:6a4db94011d3 1177 * \brief Enable PIO keypad controller.
sahilmgandhi 18:6a4db94011d3 1178 *
sahilmgandhi 18:6a4db94011d3 1179 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1180 */
sahilmgandhi 18:6a4db94011d3 1181 void pio_keypad_enable(Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1182 {
sahilmgandhi 18:6a4db94011d3 1183 p_pio->PIO_KER |= PIO_KER_KCE;
sahilmgandhi 18:6a4db94011d3 1184 }
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 /**
sahilmgandhi 18:6a4db94011d3 1187 * \brief Disable PIO keypad controller.
sahilmgandhi 18:6a4db94011d3 1188 *
sahilmgandhi 18:6a4db94011d3 1189 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1190 */
sahilmgandhi 18:6a4db94011d3 1191 void pio_keypad_disable(Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1192 {
sahilmgandhi 18:6a4db94011d3 1193 p_pio->PIO_KER &= (~PIO_KER_KCE);
sahilmgandhi 18:6a4db94011d3 1194 }
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196 /**
sahilmgandhi 18:6a4db94011d3 1197 * \brief Set PIO keypad controller row number.
sahilmgandhi 18:6a4db94011d3 1198 *
sahilmgandhi 18:6a4db94011d3 1199 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1200 * \param num Number of row of the keypad matrix.
sahilmgandhi 18:6a4db94011d3 1201 */
sahilmgandhi 18:6a4db94011d3 1202 void pio_keypad_set_row_num(Pio *p_pio, uint8_t num)
sahilmgandhi 18:6a4db94011d3 1203 {
sahilmgandhi 18:6a4db94011d3 1204 p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk);
sahilmgandhi 18:6a4db94011d3 1205 p_pio->PIO_KRCR |= PIO_KRCR_NBR(num);
sahilmgandhi 18:6a4db94011d3 1206 }
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 /**
sahilmgandhi 18:6a4db94011d3 1209 * \brief Get PIO keypad controller row number.
sahilmgandhi 18:6a4db94011d3 1210 *
sahilmgandhi 18:6a4db94011d3 1211 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1212 *
sahilmgandhi 18:6a4db94011d3 1213 * \return Number of row of the keypad matrix.
sahilmgandhi 18:6a4db94011d3 1214 */
sahilmgandhi 18:6a4db94011d3 1215 uint8_t pio_keypad_get_row_num(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1216 {
sahilmgandhi 18:6a4db94011d3 1217 return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos);
sahilmgandhi 18:6a4db94011d3 1218 }
sahilmgandhi 18:6a4db94011d3 1219
sahilmgandhi 18:6a4db94011d3 1220 /**
sahilmgandhi 18:6a4db94011d3 1221 * \brief Set PIO keypad controller column number.
sahilmgandhi 18:6a4db94011d3 1222 *
sahilmgandhi 18:6a4db94011d3 1223 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1224 * \param num Number of column of the keypad matrix.
sahilmgandhi 18:6a4db94011d3 1225 */
sahilmgandhi 18:6a4db94011d3 1226 void pio_keypad_set_column_num(Pio *p_pio, uint8_t num)
sahilmgandhi 18:6a4db94011d3 1227 {
sahilmgandhi 18:6a4db94011d3 1228 p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk);
sahilmgandhi 18:6a4db94011d3 1229 p_pio->PIO_KRCR |= PIO_KRCR_NBC(num);
sahilmgandhi 18:6a4db94011d3 1230 }
sahilmgandhi 18:6a4db94011d3 1231
sahilmgandhi 18:6a4db94011d3 1232 /**
sahilmgandhi 18:6a4db94011d3 1233 * \brief Get PIO keypad controller column number.
sahilmgandhi 18:6a4db94011d3 1234 *
sahilmgandhi 18:6a4db94011d3 1235 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1236 *
sahilmgandhi 18:6a4db94011d3 1237 * \return Number of column of the keypad matrix.
sahilmgandhi 18:6a4db94011d3 1238 */
sahilmgandhi 18:6a4db94011d3 1239 uint8_t pio_keypad_get_column_num(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1240 {
sahilmgandhi 18:6a4db94011d3 1241 return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos);
sahilmgandhi 18:6a4db94011d3 1242 }
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 /**
sahilmgandhi 18:6a4db94011d3 1245 * \brief Set PIO keypad matrix debouncing value.
sahilmgandhi 18:6a4db94011d3 1246 *
sahilmgandhi 18:6a4db94011d3 1247 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1248 * \param num Number of debouncing value.
sahilmgandhi 18:6a4db94011d3 1249 */
sahilmgandhi 18:6a4db94011d3 1250 void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value)
sahilmgandhi 18:6a4db94011d3 1251 {
sahilmgandhi 18:6a4db94011d3 1252 p_pio->PIO_KDR = PIO_KDR_DBC(value);
sahilmgandhi 18:6a4db94011d3 1253 }
sahilmgandhi 18:6a4db94011d3 1254
sahilmgandhi 18:6a4db94011d3 1255 /**
sahilmgandhi 18:6a4db94011d3 1256 * \brief Get PIO keypad matrix debouncing value.
sahilmgandhi 18:6a4db94011d3 1257 *
sahilmgandhi 18:6a4db94011d3 1258 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1259 *
sahilmgandhi 18:6a4db94011d3 1260 * \return The keypad debouncing value.
sahilmgandhi 18:6a4db94011d3 1261 */
sahilmgandhi 18:6a4db94011d3 1262 uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1263 {
sahilmgandhi 18:6a4db94011d3 1264 return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos);
sahilmgandhi 18:6a4db94011d3 1265 }
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267 /**
sahilmgandhi 18:6a4db94011d3 1268 * \brief Enable the interrupt source of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1269 *
sahilmgandhi 18:6a4db94011d3 1270 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1271 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1272 */
sahilmgandhi 18:6a4db94011d3 1273 void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 1274 {
sahilmgandhi 18:6a4db94011d3 1275 p_pio->PIO_KIER = ul_mask;
sahilmgandhi 18:6a4db94011d3 1276 }
sahilmgandhi 18:6a4db94011d3 1277
sahilmgandhi 18:6a4db94011d3 1278 /**
sahilmgandhi 18:6a4db94011d3 1279 * \brief Disable the interrupt source of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1280 *
sahilmgandhi 18:6a4db94011d3 1281 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1282 * \param ul_mask Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1283 */
sahilmgandhi 18:6a4db94011d3 1284 void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask)
sahilmgandhi 18:6a4db94011d3 1285 {
sahilmgandhi 18:6a4db94011d3 1286 p_pio->PIO_KIDR = ul_mask;
sahilmgandhi 18:6a4db94011d3 1287 }
sahilmgandhi 18:6a4db94011d3 1288
sahilmgandhi 18:6a4db94011d3 1289 /**
sahilmgandhi 18:6a4db94011d3 1290 * \brief Get interrupt mask of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1291 *
sahilmgandhi 18:6a4db94011d3 1292 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1293 *
sahilmgandhi 18:6a4db94011d3 1294 * \return The interrupt mask value.
sahilmgandhi 18:6a4db94011d3 1295 */
sahilmgandhi 18:6a4db94011d3 1296 uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1297 {
sahilmgandhi 18:6a4db94011d3 1298 return p_pio->PIO_KIMR;
sahilmgandhi 18:6a4db94011d3 1299 }
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301 /**
sahilmgandhi 18:6a4db94011d3 1302 * \brief Get key press status of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1303 *
sahilmgandhi 18:6a4db94011d3 1304 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1305 *
sahilmgandhi 18:6a4db94011d3 1306 * \return The status of key press.
sahilmgandhi 18:6a4db94011d3 1307 * 0: No key press has been detected.
sahilmgandhi 18:6a4db94011d3 1308 * 1: At least one key press has been detected.
sahilmgandhi 18:6a4db94011d3 1309 */
sahilmgandhi 18:6a4db94011d3 1310 uint32_t pio_keypad_get_press_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1311 {
sahilmgandhi 18:6a4db94011d3 1312 if (p_pio->PIO_KSR & PIO_KSR_KPR) {
sahilmgandhi 18:6a4db94011d3 1313 return 1;
sahilmgandhi 18:6a4db94011d3 1314 } else {
sahilmgandhi 18:6a4db94011d3 1315 return 0;
sahilmgandhi 18:6a4db94011d3 1316 }
sahilmgandhi 18:6a4db94011d3 1317 }
sahilmgandhi 18:6a4db94011d3 1318
sahilmgandhi 18:6a4db94011d3 1319 /**
sahilmgandhi 18:6a4db94011d3 1320 * \brief Get key release status of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1321 *
sahilmgandhi 18:6a4db94011d3 1322 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1323 *
sahilmgandhi 18:6a4db94011d3 1324 * \return The status of key release.
sahilmgandhi 18:6a4db94011d3 1325 * 0 No key release has been detected.
sahilmgandhi 18:6a4db94011d3 1326 * 1 At least one key release has been detected.
sahilmgandhi 18:6a4db94011d3 1327 */
sahilmgandhi 18:6a4db94011d3 1328 uint32_t pio_keypad_get_release_status(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1329 {
sahilmgandhi 18:6a4db94011d3 1330 if (p_pio->PIO_KSR & PIO_KSR_KRL) {
sahilmgandhi 18:6a4db94011d3 1331 return 1;
sahilmgandhi 18:6a4db94011d3 1332 } else {
sahilmgandhi 18:6a4db94011d3 1333 return 0;
sahilmgandhi 18:6a4db94011d3 1334 }
sahilmgandhi 18:6a4db94011d3 1335 }
sahilmgandhi 18:6a4db94011d3 1336
sahilmgandhi 18:6a4db94011d3 1337 /**
sahilmgandhi 18:6a4db94011d3 1338 * \brief Get simultaneous key press number of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1339 *
sahilmgandhi 18:6a4db94011d3 1340 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1341 *
sahilmgandhi 18:6a4db94011d3 1342 * \return The number of simultaneous key press.
sahilmgandhi 18:6a4db94011d3 1343 */
sahilmgandhi 18:6a4db94011d3 1344 uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1345 {
sahilmgandhi 18:6a4db94011d3 1346 return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos);
sahilmgandhi 18:6a4db94011d3 1347 }
sahilmgandhi 18:6a4db94011d3 1348
sahilmgandhi 18:6a4db94011d3 1349 /**
sahilmgandhi 18:6a4db94011d3 1350 * \brief Get simultaneous key release number of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1351 *
sahilmgandhi 18:6a4db94011d3 1352 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1353 *
sahilmgandhi 18:6a4db94011d3 1354 * \return The number of simultaneous key release.
sahilmgandhi 18:6a4db94011d3 1355 */
sahilmgandhi 18:6a4db94011d3 1356 uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio)
sahilmgandhi 18:6a4db94011d3 1357 {
sahilmgandhi 18:6a4db94011d3 1358 return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos);
sahilmgandhi 18:6a4db94011d3 1359 }
sahilmgandhi 18:6a4db94011d3 1360
sahilmgandhi 18:6a4db94011d3 1361 /**
sahilmgandhi 18:6a4db94011d3 1362 * \brief Get detected key press row index of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1363 *
sahilmgandhi 18:6a4db94011d3 1364 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1365 * \param queue The queue of key press row
sahilmgandhi 18:6a4db94011d3 1366 *
sahilmgandhi 18:6a4db94011d3 1367 * \return The index of detected key press row.
sahilmgandhi 18:6a4db94011d3 1368 */
sahilmgandhi 18:6a4db94011d3 1369 uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue)
sahilmgandhi 18:6a4db94011d3 1370 {
sahilmgandhi 18:6a4db94011d3 1371 switch (queue) {
sahilmgandhi 18:6a4db94011d3 1372 case 0:
sahilmgandhi 18:6a4db94011d3 1373 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1374 case 1:
sahilmgandhi 18:6a4db94011d3 1375 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1376 case 2:
sahilmgandhi 18:6a4db94011d3 1377 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1378 case 3:
sahilmgandhi 18:6a4db94011d3 1379 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1380 default:
sahilmgandhi 18:6a4db94011d3 1381 return 0;
sahilmgandhi 18:6a4db94011d3 1382 }
sahilmgandhi 18:6a4db94011d3 1383 }
sahilmgandhi 18:6a4db94011d3 1384
sahilmgandhi 18:6a4db94011d3 1385 /**
sahilmgandhi 18:6a4db94011d3 1386 * \brief Get detected key press column index of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1387 *
sahilmgandhi 18:6a4db94011d3 1388 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1389 * \param queue The queue of key press column
sahilmgandhi 18:6a4db94011d3 1390 *
sahilmgandhi 18:6a4db94011d3 1391 * \return The index of detected key press column.
sahilmgandhi 18:6a4db94011d3 1392 */
sahilmgandhi 18:6a4db94011d3 1393 uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue)
sahilmgandhi 18:6a4db94011d3 1394 {
sahilmgandhi 18:6a4db94011d3 1395 switch (queue) {
sahilmgandhi 18:6a4db94011d3 1396 case 0:
sahilmgandhi 18:6a4db94011d3 1397 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos);
sahilmgandhi 18:6a4db94011d3 1398 case 1:
sahilmgandhi 18:6a4db94011d3 1399 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos);
sahilmgandhi 18:6a4db94011d3 1400 case 2:
sahilmgandhi 18:6a4db94011d3 1401 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos);
sahilmgandhi 18:6a4db94011d3 1402 case 3:
sahilmgandhi 18:6a4db94011d3 1403 return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos);
sahilmgandhi 18:6a4db94011d3 1404 default:
sahilmgandhi 18:6a4db94011d3 1405 return 0;
sahilmgandhi 18:6a4db94011d3 1406 }
sahilmgandhi 18:6a4db94011d3 1407 }
sahilmgandhi 18:6a4db94011d3 1408
sahilmgandhi 18:6a4db94011d3 1409 /**
sahilmgandhi 18:6a4db94011d3 1410 * \brief Get detected key release row index of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1411 *
sahilmgandhi 18:6a4db94011d3 1412 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1413 * \param queue The queue of key release row
sahilmgandhi 18:6a4db94011d3 1414 *
sahilmgandhi 18:6a4db94011d3 1415 * \return The index of detected key release row.
sahilmgandhi 18:6a4db94011d3 1416 */
sahilmgandhi 18:6a4db94011d3 1417 uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue)
sahilmgandhi 18:6a4db94011d3 1418 {
sahilmgandhi 18:6a4db94011d3 1419 switch (queue) {
sahilmgandhi 18:6a4db94011d3 1420 case 0:
sahilmgandhi 18:6a4db94011d3 1421 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1422 case 1:
sahilmgandhi 18:6a4db94011d3 1423 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1424 case 2:
sahilmgandhi 18:6a4db94011d3 1425 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1426 case 3:
sahilmgandhi 18:6a4db94011d3 1427 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos);
sahilmgandhi 18:6a4db94011d3 1428 default:
sahilmgandhi 18:6a4db94011d3 1429 return 0;
sahilmgandhi 18:6a4db94011d3 1430 }
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 /**
sahilmgandhi 18:6a4db94011d3 1434 * \brief Get detected key release column index of PIO keypad.
sahilmgandhi 18:6a4db94011d3 1435 *
sahilmgandhi 18:6a4db94011d3 1436 * \param p_pio Pointer to a PIO instance.
sahilmgandhi 18:6a4db94011d3 1437 * \param queue The queue of key release column
sahilmgandhi 18:6a4db94011d3 1438 *
sahilmgandhi 18:6a4db94011d3 1439 * \return The index of detected key release column.
sahilmgandhi 18:6a4db94011d3 1440 */
sahilmgandhi 18:6a4db94011d3 1441 uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue)
sahilmgandhi 18:6a4db94011d3 1442 {
sahilmgandhi 18:6a4db94011d3 1443 switch (queue) {
sahilmgandhi 18:6a4db94011d3 1444 case 0:
sahilmgandhi 18:6a4db94011d3 1445 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos);
sahilmgandhi 18:6a4db94011d3 1446 case 1:
sahilmgandhi 18:6a4db94011d3 1447 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos);
sahilmgandhi 18:6a4db94011d3 1448 case 2:
sahilmgandhi 18:6a4db94011d3 1449 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos);
sahilmgandhi 18:6a4db94011d3 1450 case 3:
sahilmgandhi 18:6a4db94011d3 1451 return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos);
sahilmgandhi 18:6a4db94011d3 1452 default:
sahilmgandhi 18:6a4db94011d3 1453 return 0;
sahilmgandhi 18:6a4db94011d3 1454 }
sahilmgandhi 18:6a4db94011d3 1455 }
sahilmgandhi 18:6a4db94011d3 1456
sahilmgandhi 18:6a4db94011d3 1457 #endif
sahilmgandhi 18:6a4db94011d3 1458
sahilmgandhi 18:6a4db94011d3 1459 //@}
sahilmgandhi 18:6a4db94011d3 1460