MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief SAM4 Peripheral DMA Controller (PDC) driver.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #include "pdc.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /// @cond
sahilmgandhi 18:6a4db94011d3 50 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 51 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 52 extern "C" {
sahilmgandhi 18:6a4db94011d3 53 #endif
sahilmgandhi 18:6a4db94011d3 54 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 55 /// @endcond
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /**
sahilmgandhi 18:6a4db94011d3 58 * \brief Configure PDC for data transmit.
sahilmgandhi 18:6a4db94011d3 59 *
sahilmgandhi 18:6a4db94011d3 60 * \param[out] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 61 * \param[in] p_packet Pointer to packet information for current buffer register
sahilmgandhi 18:6a4db94011d3 62 * set. Use NULL to leave unaltered.
sahilmgandhi 18:6a4db94011d3 63 * \param[in] p_next_packet Pointer to packet information for next buffer register
sahilmgandhi 18:6a4db94011d3 64 * set. Use NULL to leave unaltered.
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 void pdc_tx_init(
sahilmgandhi 18:6a4db94011d3 67 Pdc *p_pdc,
sahilmgandhi 18:6a4db94011d3 68 pdc_packet_t *p_packet,
sahilmgandhi 18:6a4db94011d3 69 pdc_packet_t *p_next_packet)
sahilmgandhi 18:6a4db94011d3 70 {
sahilmgandhi 18:6a4db94011d3 71 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 72 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 if (p_packet) {
sahilmgandhi 18:6a4db94011d3 75 p_pdc->PERIPH_TPR = p_packet->ul_addr;
sahilmgandhi 18:6a4db94011d3 76 p_pdc->PERIPH_TCR = p_packet->ul_size;
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78 if (p_next_packet) {
sahilmgandhi 18:6a4db94011d3 79 p_pdc->PERIPH_TNPR = p_next_packet->ul_addr;
sahilmgandhi 18:6a4db94011d3 80 p_pdc->PERIPH_TNCR = p_next_packet->ul_size;
sahilmgandhi 18:6a4db94011d3 81 }
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /**
sahilmgandhi 18:6a4db94011d3 85 * \brief Configure PDC for data receive.
sahilmgandhi 18:6a4db94011d3 86 *
sahilmgandhi 18:6a4db94011d3 87 * \param[out] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 88 * \param[in] p_packet Pointer to packet information for current buffer register
sahilmgandhi 18:6a4db94011d3 89 * set. Use NULL to leave unaltered.
sahilmgandhi 18:6a4db94011d3 90 * \param[in] p_next_packet Pointer to packet information for next buffer register
sahilmgandhi 18:6a4db94011d3 91 * set. Use NULL to leave unaltered.
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93 void pdc_rx_init(
sahilmgandhi 18:6a4db94011d3 94 Pdc *p_pdc,
sahilmgandhi 18:6a4db94011d3 95 pdc_packet_t *p_packet,
sahilmgandhi 18:6a4db94011d3 96 pdc_packet_t *p_next_packet)
sahilmgandhi 18:6a4db94011d3 97 {
sahilmgandhi 18:6a4db94011d3 98 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 99 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 if (p_packet) {
sahilmgandhi 18:6a4db94011d3 102 p_pdc->PERIPH_RPR = p_packet->ul_addr;
sahilmgandhi 18:6a4db94011d3 103 p_pdc->PERIPH_RCR = p_packet->ul_size;
sahilmgandhi 18:6a4db94011d3 104 }
sahilmgandhi 18:6a4db94011d3 105 if (p_next_packet) {
sahilmgandhi 18:6a4db94011d3 106 p_pdc->PERIPH_RNPR = p_next_packet->ul_addr;
sahilmgandhi 18:6a4db94011d3 107 p_pdc->PERIPH_RNCR = p_next_packet->ul_size;
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109 }
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /**
sahilmgandhi 18:6a4db94011d3 112 * \brief Clear PDC buffer receive counter.
sahilmgandhi 18:6a4db94011d3 113 *
sahilmgandhi 18:6a4db94011d3 114 * \param[out] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116 void pdc_rx_clear_cnt(
sahilmgandhi 18:6a4db94011d3 117 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 118 {
sahilmgandhi 18:6a4db94011d3 119 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 120 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 p_pdc->PERIPH_RNCR = 0;
sahilmgandhi 18:6a4db94011d3 123 p_pdc->PERIPH_RCR = 0;
sahilmgandhi 18:6a4db94011d3 124 }
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /**
sahilmgandhi 18:6a4db94011d3 127 * \brief Enable PDC transfers (TX and/or RX).
sahilmgandhi 18:6a4db94011d3 128 *
sahilmgandhi 18:6a4db94011d3 129 * \note It is forbidden to set both TXTEN and RXTEN for a half duplex
sahilmgandhi 18:6a4db94011d3 130 * peripheral.
sahilmgandhi 18:6a4db94011d3 131 *
sahilmgandhi 18:6a4db94011d3 132 * \param[out] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 133 * \param[in] ul_controls Transfer directions
sahilmgandhi 18:6a4db94011d3 134 * (bit PERIPH_PTCR_RXTEN and bit PERIPH_PTCR_TXTEN)
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 void pdc_enable_transfer(
sahilmgandhi 18:6a4db94011d3 137 Pdc *p_pdc,
sahilmgandhi 18:6a4db94011d3 138 uint32_t ul_controls)
sahilmgandhi 18:6a4db94011d3 139 {
sahilmgandhi 18:6a4db94011d3 140 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 141 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 p_pdc->PERIPH_PTCR =
sahilmgandhi 18:6a4db94011d3 144 ul_controls & (PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * \brief Disable PDC transfers (TX and/or RX).
sahilmgandhi 18:6a4db94011d3 149 *
sahilmgandhi 18:6a4db94011d3 150 * \param[out] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 151 * \param[in] ul_controls Transfer directions
sahilmgandhi 18:6a4db94011d3 152 * (bit PERIPH_PTCR_TXTDIS, bit PERIPH_PTCR_TXTDIS)
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 void pdc_disable_transfer(
sahilmgandhi 18:6a4db94011d3 155 Pdc *p_pdc,
sahilmgandhi 18:6a4db94011d3 156 uint32_t ul_controls)
sahilmgandhi 18:6a4db94011d3 157 {
sahilmgandhi 18:6a4db94011d3 158 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 159 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 p_pdc->PERIPH_PTCR =
sahilmgandhi 18:6a4db94011d3 162 ul_controls & (PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /**
sahilmgandhi 18:6a4db94011d3 166 * \brief Read PDC status.
sahilmgandhi 18:6a4db94011d3 167 *
sahilmgandhi 18:6a4db94011d3 168 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 169 *
sahilmgandhi 18:6a4db94011d3 170 * \return PDC status register bit map.
sahilmgandhi 18:6a4db94011d3 171 *
sahilmgandhi 18:6a4db94011d3 172 * <table>
sahilmgandhi 18:6a4db94011d3 173 * <tr>
sahilmgandhi 18:6a4db94011d3 174 * <th>Name</th>
sahilmgandhi 18:6a4db94011d3 175 * <th>Description</th>
sahilmgandhi 18:6a4db94011d3 176 * <th>Bit</th>
sahilmgandhi 18:6a4db94011d3 177 * </tr>
sahilmgandhi 18:6a4db94011d3 178 * <tr>
sahilmgandhi 18:6a4db94011d3 179 * <td>RXTEN</td>
sahilmgandhi 18:6a4db94011d3 180 * <td>Receiver Transfer Enabled</td>
sahilmgandhi 18:6a4db94011d3 181 * <td>8</td>
sahilmgandhi 18:6a4db94011d3 182 * </tr>
sahilmgandhi 18:6a4db94011d3 183 * <tr>
sahilmgandhi 18:6a4db94011d3 184 * <td>TXTEN</td>
sahilmgandhi 18:6a4db94011d3 185 * <td>Transmitter Transfer Enabled</td>
sahilmgandhi 18:6a4db94011d3 186 * <td>1</td>
sahilmgandhi 18:6a4db94011d3 187 * </tr>
sahilmgandhi 18:6a4db94011d3 188 * </table>
sahilmgandhi 18:6a4db94011d3 189 *
sahilmgandhi 18:6a4db94011d3 190 */
sahilmgandhi 18:6a4db94011d3 191 uint32_t pdc_read_status(
sahilmgandhi 18:6a4db94011d3 192 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 193 {
sahilmgandhi 18:6a4db94011d3 194 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 195 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 return p_pdc->PERIPH_PTSR;
sahilmgandhi 18:6a4db94011d3 198 }
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /**
sahilmgandhi 18:6a4db94011d3 201 * \brief Return Receive Pointer Register (RPR) value.
sahilmgandhi 18:6a4db94011d3 202 *
sahilmgandhi 18:6a4db94011d3 203 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 204 *
sahilmgandhi 18:6a4db94011d3 205 * \return Receive Pointer Register value.
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207 uint32_t pdc_read_rx_ptr(
sahilmgandhi 18:6a4db94011d3 208 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 209 {
sahilmgandhi 18:6a4db94011d3 210 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 211 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 return p_pdc->PERIPH_RPR;
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /**
sahilmgandhi 18:6a4db94011d3 217 * \brief Return Receive Counter Register (RCR) value.
sahilmgandhi 18:6a4db94011d3 218 *
sahilmgandhi 18:6a4db94011d3 219 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 220 *
sahilmgandhi 18:6a4db94011d3 221 * \return Receive Counter Register value.
sahilmgandhi 18:6a4db94011d3 222 */
sahilmgandhi 18:6a4db94011d3 223 uint32_t pdc_read_rx_counter(
sahilmgandhi 18:6a4db94011d3 224 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 225 {
sahilmgandhi 18:6a4db94011d3 226 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 227 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 return p_pdc->PERIPH_RCR;
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /**
sahilmgandhi 18:6a4db94011d3 233 * \brief Return Transmit Pointer Register (TPR) value.
sahilmgandhi 18:6a4db94011d3 234 *
sahilmgandhi 18:6a4db94011d3 235 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 236 *
sahilmgandhi 18:6a4db94011d3 237 * \return Transmit Pointer Register value.
sahilmgandhi 18:6a4db94011d3 238 */
sahilmgandhi 18:6a4db94011d3 239 uint32_t pdc_read_tx_ptr(
sahilmgandhi 18:6a4db94011d3 240 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 243 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 return p_pdc->PERIPH_TPR;
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * \brief Return Transmit Counter Register (TCR) value.
sahilmgandhi 18:6a4db94011d3 250 *
sahilmgandhi 18:6a4db94011d3 251 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 252 *
sahilmgandhi 18:6a4db94011d3 253 * \return Transmit Counter Register value.
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255 uint32_t pdc_read_tx_counter(
sahilmgandhi 18:6a4db94011d3 256 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 259 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 return p_pdc->PERIPH_TCR;
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /**
sahilmgandhi 18:6a4db94011d3 265 * \brief Return Receive Next Pointer Register (RNPR) value.
sahilmgandhi 18:6a4db94011d3 266 *
sahilmgandhi 18:6a4db94011d3 267 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 268 *
sahilmgandhi 18:6a4db94011d3 269 * \return Receive Next Pointer Register value.
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271 uint32_t pdc_read_rx_next_ptr(
sahilmgandhi 18:6a4db94011d3 272 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 275 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 return p_pdc->PERIPH_RNPR;
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /**
sahilmgandhi 18:6a4db94011d3 281 * \brief Return Receive Next Counter Register (RNCR) value.
sahilmgandhi 18:6a4db94011d3 282 *
sahilmgandhi 18:6a4db94011d3 283 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 284 *
sahilmgandhi 18:6a4db94011d3 285 * \return Receive Next Counter Register value.
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287 uint32_t pdc_read_rx_next_counter(
sahilmgandhi 18:6a4db94011d3 288 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 289 {
sahilmgandhi 18:6a4db94011d3 290 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 291 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 return p_pdc->PERIPH_RNCR;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /**
sahilmgandhi 18:6a4db94011d3 297 * \brief Return Transmit Next Pointer Register (TNPR) value.
sahilmgandhi 18:6a4db94011d3 298 *
sahilmgandhi 18:6a4db94011d3 299 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 300 *
sahilmgandhi 18:6a4db94011d3 301 * \return Transmit Next Pointer Register value.
sahilmgandhi 18:6a4db94011d3 302 */
sahilmgandhi 18:6a4db94011d3 303 uint32_t pdc_read_tx_next_ptr(
sahilmgandhi 18:6a4db94011d3 304 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 305 {
sahilmgandhi 18:6a4db94011d3 306 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 307 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 return p_pdc->PERIPH_TNPR;
sahilmgandhi 18:6a4db94011d3 310 }
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 /**
sahilmgandhi 18:6a4db94011d3 313 * \brief Return Transmit Next Counter Register (TNCR) value.
sahilmgandhi 18:6a4db94011d3 314 *
sahilmgandhi 18:6a4db94011d3 315 * \param[in] p_pdc Device structure pointer
sahilmgandhi 18:6a4db94011d3 316 *
sahilmgandhi 18:6a4db94011d3 317 * \return Transmit Next Counter Register value.
sahilmgandhi 18:6a4db94011d3 318 */
sahilmgandhi 18:6a4db94011d3 319 uint32_t pdc_read_tx_next_counter(
sahilmgandhi 18:6a4db94011d3 320 Pdc *p_pdc)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 /* Validate inputs. */
sahilmgandhi 18:6a4db94011d3 323 Assert(p_pdc);
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 return p_pdc->PERIPH_TNCR;
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /// @cond
sahilmgandhi 18:6a4db94011d3 329 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 330 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 331 }
sahilmgandhi 18:6a4db94011d3 332 #endif
sahilmgandhi 18:6a4db94011d3 333 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 334 /// @endcond