MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief ADC Controller driver.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #ifndef ADC2_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 48 #define ADC2_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #include "compiler.h"
sahilmgandhi 18:6a4db94011d3 51 #include "status_codes.h"
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #if (SAM4N)
sahilmgandhi 18:6a4db94011d3 54 #define TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 55 #define SLEEP_MODE_ADC SLEEPMGR_SLEEP_WFI
sahilmgandhi 18:6a4db94011d3 56 #endif
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 59 #define NO_TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 60 #define SLEEP_MODE_ADC SLEEPMGR_ACTIVE
sahilmgandhi 18:6a4db94011d3 61 #endif
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /** Write Protect Key */
sahilmgandhi 18:6a4db94011d3 64 #ifndef ADC_WPMR_WPKEY_PASSWD
sahilmgandhi 18:6a4db94011d3 65 #define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8)
sahilmgandhi 18:6a4db94011d3 66 #endif
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 /** Definitions for ADC resolution */
sahilmgandhi 18:6a4db94011d3 69 enum adc_resolution {
sahilmgandhi 18:6a4db94011d3 70 #if SAMG55
sahilmgandhi 18:6a4db94011d3 71 ADC_12_BITS = ADC_EMR_OSR_NO_AVERAGE, /* ADC 12-bit resolution */
sahilmgandhi 18:6a4db94011d3 72 ADC_13_BITS = ADC_EMR_OSR_OSR4, /* ADC 13-bit resolution */
sahilmgandhi 18:6a4db94011d3 73 ADC_14_BITS = ADC_EMR_OSR_OSR16, /* ADC 14-bit resolution */
sahilmgandhi 18:6a4db94011d3 74 ADC_15_BITS = ADC_EMR_OSR_OSR64, /* ADC 15-bit resolution */
sahilmgandhi 18:6a4db94011d3 75 ADC_16_BITS = ADC_EMR_OSR_OSR256, /* ADC 16-bit resolution */
sahilmgandhi 18:6a4db94011d3 76 #else
sahilmgandhi 18:6a4db94011d3 77 ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */
sahilmgandhi 18:6a4db94011d3 78 ADC_10_BITS = ADC_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */
sahilmgandhi 18:6a4db94011d3 79 ADC_11_BITS = ADC_EMR_OSR_OSR4, /* ADC 11-bit resolution */
sahilmgandhi 18:6a4db94011d3 80 ADC_12_BITS = ADC_EMR_OSR_OSR16 /* ADC 12-bit resolution */
sahilmgandhi 18:6a4db94011d3 81 #endif
sahilmgandhi 18:6a4db94011d3 82 };
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /** Definitions for ADC power mode */
sahilmgandhi 18:6a4db94011d3 85 enum adc_power_mode {
sahilmgandhi 18:6a4db94011d3 86 /* ADC core on and reference voltage circuitry on */
sahilmgandhi 18:6a4db94011d3 87 ADC_POWER_MODE_0 = 0,
sahilmgandhi 18:6a4db94011d3 88 /* ADC core off and reference voltage circuitry off */
sahilmgandhi 18:6a4db94011d3 89 ADC_POWER_MODE_1
sahilmgandhi 18:6a4db94011d3 90 };
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /** Definitions for ADC trigger */
sahilmgandhi 18:6a4db94011d3 93 enum adc_trigger {
sahilmgandhi 18:6a4db94011d3 94 /* Starting a conversion is only possible by software. */
sahilmgandhi 18:6a4db94011d3 95 ADC_TRIG_SW = ADC_MR_TRGEN_DIS,
sahilmgandhi 18:6a4db94011d3 96 /* External trigger */
sahilmgandhi 18:6a4db94011d3 97 ADC_TRIG_EXT = ADC_MR_TRGSEL_ADC_TRIG0 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 98 /* TIO Output of the Timer Counter Channel 0 */
sahilmgandhi 18:6a4db94011d3 99 ADC_TRIG_TIO_CH_0 = ADC_MR_TRGSEL_ADC_TRIG1 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 100 /* TIO Output of the Timer Counter Channel 1 */
sahilmgandhi 18:6a4db94011d3 101 ADC_TRIG_TIO_CH_1 = ADC_MR_TRGSEL_ADC_TRIG2 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 102 /* TIO Output of the Timer Counter Channel 2 */
sahilmgandhi 18:6a4db94011d3 103 ADC_TRIG_TIO_CH_2 = ADC_MR_TRGSEL_ADC_TRIG3 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 104 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 105 /* RTCOUT0 */
sahilmgandhi 18:6a4db94011d3 106 ADC_TRIG_RTC_0 = ADC_MR_TRGSEL_ADC_TRIG4 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 107 /* RTTINC */
sahilmgandhi 18:6a4db94011d3 108 ADC_TRIG_RTT = ADC_MR_TRGSEL_ADC_TRIG5 | ADC_MR_TRGEN,
sahilmgandhi 18:6a4db94011d3 109 #endif
sahilmgandhi 18:6a4db94011d3 110 /* Freerun mode conversion. */
sahilmgandhi 18:6a4db94011d3 111 ADC_TRIG_FREERUN = 0xFF
sahilmgandhi 18:6a4db94011d3 112 };
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /** Definitions for ADC channel number */
sahilmgandhi 18:6a4db94011d3 115 enum adc_channel_num {
sahilmgandhi 18:6a4db94011d3 116 ADC_CHANNEL_0 = 0,
sahilmgandhi 18:6a4db94011d3 117 ADC_CHANNEL_1,
sahilmgandhi 18:6a4db94011d3 118 ADC_CHANNEL_2,
sahilmgandhi 18:6a4db94011d3 119 ADC_CHANNEL_3,
sahilmgandhi 18:6a4db94011d3 120 ADC_CHANNEL_4,
sahilmgandhi 18:6a4db94011d3 121 ADC_CHANNEL_5,
sahilmgandhi 18:6a4db94011d3 122 ADC_CHANNEL_6,
sahilmgandhi 18:6a4db94011d3 123 ADC_CHANNEL_7,
sahilmgandhi 18:6a4db94011d3 124 #if (SAM4N)
sahilmgandhi 18:6a4db94011d3 125 ADC_CHANNEL_8,
sahilmgandhi 18:6a4db94011d3 126 ADC_CHANNEL_9,
sahilmgandhi 18:6a4db94011d3 127 ADC_CHANNEL_10,
sahilmgandhi 18:6a4db94011d3 128 ADC_CHANNEL_11,
sahilmgandhi 18:6a4db94011d3 129 ADC_CHANNEL_12,
sahilmgandhi 18:6a4db94011d3 130 ADC_CHANNEL_13,
sahilmgandhi 18:6a4db94011d3 131 ADC_CHANNEL_14,
sahilmgandhi 18:6a4db94011d3 132 ADC_CHANNEL_15,
sahilmgandhi 18:6a4db94011d3 133 #endif
sahilmgandhi 18:6a4db94011d3 134 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 135 ADC_TEMPERATURE_SENSOR,
sahilmgandhi 18:6a4db94011d3 136 #endif
sahilmgandhi 18:6a4db94011d3 137 ADC_CHANNEL_ALL = 0xFFFF
sahilmgandhi 18:6a4db94011d3 138 };
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /** Definitions for ADC Start Up Time */
sahilmgandhi 18:6a4db94011d3 141 enum adc_startup_time {
sahilmgandhi 18:6a4db94011d3 142 ADC_STARTUP_TIME_0 = ADC_MR_STARTUP_SUT0,
sahilmgandhi 18:6a4db94011d3 143 ADC_STARTUP_TIME_1 = ADC_MR_STARTUP_SUT8,
sahilmgandhi 18:6a4db94011d3 144 ADC_STARTUP_TIME_2 = ADC_MR_STARTUP_SUT16,
sahilmgandhi 18:6a4db94011d3 145 ADC_STARTUP_TIME_3 = ADC_MR_STARTUP_SUT24,
sahilmgandhi 18:6a4db94011d3 146 ADC_STARTUP_TIME_4 = ADC_MR_STARTUP_SUT64,
sahilmgandhi 18:6a4db94011d3 147 ADC_STARTUP_TIME_5 = ADC_MR_STARTUP_SUT80,
sahilmgandhi 18:6a4db94011d3 148 ADC_STARTUP_TIME_6 = ADC_MR_STARTUP_SUT96,
sahilmgandhi 18:6a4db94011d3 149 ADC_STARTUP_TIME_7 = ADC_MR_STARTUP_SUT112,
sahilmgandhi 18:6a4db94011d3 150 ADC_STARTUP_TIME_8 = ADC_MR_STARTUP_SUT512,
sahilmgandhi 18:6a4db94011d3 151 ADC_STARTUP_TIME_9 = ADC_MR_STARTUP_SUT576,
sahilmgandhi 18:6a4db94011d3 152 ADC_STARTUP_TIME_10 = ADC_MR_STARTUP_SUT640,
sahilmgandhi 18:6a4db94011d3 153 ADC_STARTUP_TIME_11 = ADC_MR_STARTUP_SUT704,
sahilmgandhi 18:6a4db94011d3 154 ADC_STARTUP_TIME_12 = ADC_MR_STARTUP_SUT768,
sahilmgandhi 18:6a4db94011d3 155 ADC_STARTUP_TIME_13 = ADC_MR_STARTUP_SUT832,
sahilmgandhi 18:6a4db94011d3 156 ADC_STARTUP_TIME_14 = ADC_MR_STARTUP_SUT896,
sahilmgandhi 18:6a4db94011d3 157 ADC_STARTUP_TIME_15 = ADC_MR_STARTUP_SUT960
sahilmgandhi 18:6a4db94011d3 158 };
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /** Definitions for Comparison Mode */
sahilmgandhi 18:6a4db94011d3 161 enum adc_cmp_mode {
sahilmgandhi 18:6a4db94011d3 162 ADC_CMP_MODE_0 = ADC_EMR_CMPMODE_LOW,
sahilmgandhi 18:6a4db94011d3 163 ADC_CMP_MODE_1 = ADC_EMR_CMPMODE_HIGH,
sahilmgandhi 18:6a4db94011d3 164 ADC_CMP_MODE_2 = ADC_EMR_CMPMODE_IN,
sahilmgandhi 18:6a4db94011d3 165 ADC_CMP_MODE_3 = ADC_EMR_CMPMODE_OUT
sahilmgandhi 18:6a4db94011d3 166 };
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 169 /** Definitions for Temperature Comparison Mode */
sahilmgandhi 18:6a4db94011d3 170 enum adc_temp_cmp_mode {
sahilmgandhi 18:6a4db94011d3 171 ADC_TEMP_CMP_MODE_0 = ADC_TEMPMR_TEMPCMPMOD_LOW,
sahilmgandhi 18:6a4db94011d3 172 ADC_TEMP_CMP_MODE_1 = ADC_TEMPMR_TEMPCMPMOD_HIGH,
sahilmgandhi 18:6a4db94011d3 173 ADC_TEMP_CMP_MODE_2 = ADC_TEMPMR_TEMPCMPMOD_IN,
sahilmgandhi 18:6a4db94011d3 174 ADC_TEMP_CMP_MODE_3 = ADC_TEMPMR_TEMPCMPMOD_OUT
sahilmgandhi 18:6a4db94011d3 175 };
sahilmgandhi 18:6a4db94011d3 176 #endif
sahilmgandhi 18:6a4db94011d3 177 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 178 /** Definitions for Last Channel Specific Measurement Comparison Mode */
sahilmgandhi 18:6a4db94011d3 179 enum adc_last_channel_cmp_mode {
sahilmgandhi 18:6a4db94011d3 180 ADC_LAST_CHANNEL_CMP_MODE_0 = ADC_LCTMR_CMPMOD_LOW,
sahilmgandhi 18:6a4db94011d3 181 ADC_LAST_CHANNEL_CMP_MODE_1 = ADC_LCTMR_CMPMOD_HIGH,
sahilmgandhi 18:6a4db94011d3 182 ADC_LAST_CHANNEL_CMP_MODE_2 = ADC_LCTMR_CMPMOD_IN,
sahilmgandhi 18:6a4db94011d3 183 ADC_LAST_CHANNEL_CMP_MODE_3 = ADC_LCTMR_CMPMOD_OUT
sahilmgandhi 18:6a4db94011d3 184 };
sahilmgandhi 18:6a4db94011d3 185 #endif
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /** Definitions for Reference Voltage Selection */
sahilmgandhi 18:6a4db94011d3 188 enum adc_refer_voltage_source {
sahilmgandhi 18:6a4db94011d3 189 ADC_REFER_VOL_EXTERNAL = 0,
sahilmgandhi 18:6a4db94011d3 190 ADC_REFER_VOL_STUCK_AT_MIN,
sahilmgandhi 18:6a4db94011d3 191 ADC_REFER_VOL_VDDANA,
sahilmgandhi 18:6a4db94011d3 192 ADC_REFER_VOL_IRVS
sahilmgandhi 18:6a4db94011d3 193 };
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * \brief ADC Enhanced configuration structure.
sahilmgandhi 18:6a4db94011d3 197 *
sahilmgandhi 18:6a4db94011d3 198 * Configuration structure for a ADC Enhanced instance.
sahilmgandhi 18:6a4db94011d3 199 * This structure could be initialized by the \ref ADC_get_config_defaults()
sahilmgandhi 18:6a4db94011d3 200 * function before being modified by the user application.
sahilmgandhi 18:6a4db94011d3 201 */
sahilmgandhi 18:6a4db94011d3 202 struct adc_config {
sahilmgandhi 18:6a4db94011d3 203 /** Resolution */
sahilmgandhi 18:6a4db94011d3 204 enum adc_resolution resolution;
sahilmgandhi 18:6a4db94011d3 205 /** Master Clock */
sahilmgandhi 18:6a4db94011d3 206 uint32_t mck;
sahilmgandhi 18:6a4db94011d3 207 /** ADC Clock */
sahilmgandhi 18:6a4db94011d3 208 uint32_t adc_clock;
sahilmgandhi 18:6a4db94011d3 209 /** Start Up Time */
sahilmgandhi 18:6a4db94011d3 210 enum adc_startup_time startup_time;
sahilmgandhi 18:6a4db94011d3 211 /** Tracking Time = (tracktim+1) / ADC clock */
sahilmgandhi 18:6a4db94011d3 212 uint8_t tracktim;
sahilmgandhi 18:6a4db94011d3 213 /** Transfer Period */
sahilmgandhi 18:6a4db94011d3 214 uint8_t transfer;
sahilmgandhi 18:6a4db94011d3 215 /** Use Sequence Enable */
sahilmgandhi 18:6a4db94011d3 216 bool useq;
sahilmgandhi 18:6a4db94011d3 217 /** TAG of ADC_LDCR register */
sahilmgandhi 18:6a4db94011d3 218 bool tag;
sahilmgandhi 18:6a4db94011d3 219 /** Averaging on Single Trigger Event */
sahilmgandhi 18:6a4db94011d3 220 bool aste;
sahilmgandhi 18:6a4db94011d3 221 };
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 224 /** ADC Temperature Sensor configuration structure.*/
sahilmgandhi 18:6a4db94011d3 225 struct adc_temp_sensor_config {
sahilmgandhi 18:6a4db94011d3 226 /** Temperature Sensor On */
sahilmgandhi 18:6a4db94011d3 227 bool tempon;
sahilmgandhi 18:6a4db94011d3 228 /** Temperature Comparison Mode */
sahilmgandhi 18:6a4db94011d3 229 enum adc_temp_cmp_mode mode;
sahilmgandhi 18:6a4db94011d3 230 /** Temperature Low Threshold */
sahilmgandhi 18:6a4db94011d3 231 uint16_t low_threshold;
sahilmgandhi 18:6a4db94011d3 232 /** Temperature High Threshold */
sahilmgandhi 18:6a4db94011d3 233 uint16_t high_threshold;
sahilmgandhi 18:6a4db94011d3 234 };
sahilmgandhi 18:6a4db94011d3 235 #endif
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 238 /** ADC Last Channel Specific Measurement configuration structure.*/
sahilmgandhi 18:6a4db94011d3 239 struct adc_last_channel_config {
sahilmgandhi 18:6a4db94011d3 240 /** Specific Measurement On */
sahilmgandhi 18:6a4db94011d3 241 bool dual_trig_on;
sahilmgandhi 18:6a4db94011d3 242 /** Specific Measurement Comparison Mode */
sahilmgandhi 18:6a4db94011d3 243 enum adc_last_channel_cmp_mode mode;
sahilmgandhi 18:6a4db94011d3 244 /** Specific Measurement Low Threshold */
sahilmgandhi 18:6a4db94011d3 245 uint16_t low_threshold;
sahilmgandhi 18:6a4db94011d3 246 /** Specific Measurement High Threshold */
sahilmgandhi 18:6a4db94011d3 247 uint16_t high_threshold;
sahilmgandhi 18:6a4db94011d3 248 };
sahilmgandhi 18:6a4db94011d3 249 #endif
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /** ADC interrupt source type */
sahilmgandhi 18:6a4db94011d3 252 enum adc_interrupt_source {
sahilmgandhi 18:6a4db94011d3 253 ADC_INTERRUPT_EOC_0 = 0,
sahilmgandhi 18:6a4db94011d3 254 ADC_INTERRUPT_EOC_1,
sahilmgandhi 18:6a4db94011d3 255 ADC_INTERRUPT_EOC_2,
sahilmgandhi 18:6a4db94011d3 256 ADC_INTERRUPT_EOC_3,
sahilmgandhi 18:6a4db94011d3 257 ADC_INTERRUPT_EOC_4,
sahilmgandhi 18:6a4db94011d3 258 ADC_INTERRUPT_EOC_5,
sahilmgandhi 18:6a4db94011d3 259 ADC_INTERRUPT_EOC_6,
sahilmgandhi 18:6a4db94011d3 260 ADC_INTERRUPT_EOC_7,
sahilmgandhi 18:6a4db94011d3 261 #if (SAM4N)
sahilmgandhi 18:6a4db94011d3 262 ADC_INTERRUPT_EOC_8,
sahilmgandhi 18:6a4db94011d3 263 ADC_INTERRUPT_EOC_9,
sahilmgandhi 18:6a4db94011d3 264 ADC_INTERRUPT_EOC_10,
sahilmgandhi 18:6a4db94011d3 265 ADC_INTERRUPT_EOC_11,
sahilmgandhi 18:6a4db94011d3 266 ADC_INTERRUPT_EOC_12,
sahilmgandhi 18:6a4db94011d3 267 ADC_INTERRUPT_EOC_13,
sahilmgandhi 18:6a4db94011d3 268 ADC_INTERRUPT_EOC_14,
sahilmgandhi 18:6a4db94011d3 269 ADC_INTERRUPT_EOC_15,
sahilmgandhi 18:6a4db94011d3 270 ADC_INTERRUPT_EOC_16,
sahilmgandhi 18:6a4db94011d3 271 #endif
sahilmgandhi 18:6a4db94011d3 272 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 273 ADC_INTERRUPT_TEMP_CHANGE,
sahilmgandhi 18:6a4db94011d3 274 #endif
sahilmgandhi 18:6a4db94011d3 275 ADC_INTERRUPT_END_CAL,
sahilmgandhi 18:6a4db94011d3 276 ADC_INTERRUPT_DATA_READY,
sahilmgandhi 18:6a4db94011d3 277 ADC_INTERRUPT_OVERRUN_ERROR,
sahilmgandhi 18:6a4db94011d3 278 ADC_INTERRUPT_COMP_ERROR,
sahilmgandhi 18:6a4db94011d3 279 ADC_INTERRUPT_END_RXBUF,
sahilmgandhi 18:6a4db94011d3 280 ADC_INTERRUPT_RXBUF_FULL,
sahilmgandhi 18:6a4db94011d3 281 ADC_INTERRUPT_ALL = 0xFFFFFFFF
sahilmgandhi 18:6a4db94011d3 282 };
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 typedef void (*adc_callback_t)(void);
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 void adc_get_config_defaults(struct adc_config *const cfg);
sahilmgandhi 18:6a4db94011d3 287 enum status_code adc_init(Adc *const adc, struct adc_config *const config);
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 290 void adc_temp_sensor_get_config_defaults(
sahilmgandhi 18:6a4db94011d3 291 struct adc_temp_sensor_config *const cfg);
sahilmgandhi 18:6a4db94011d3 292 void adc_temp_sensor_set_config(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 293 struct adc_temp_sensor_config *config);
sahilmgandhi 18:6a4db94011d3 294 #endif
sahilmgandhi 18:6a4db94011d3 295 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 296 void adc_last_channel_get_config_defaults(
sahilmgandhi 18:6a4db94011d3 297 struct adc_last_channel_config *const cfg);
sahilmgandhi 18:6a4db94011d3 298 void adc_last_channel_set_config(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 299 struct adc_last_channel_config *config);
sahilmgandhi 18:6a4db94011d3 300 #endif
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 void adc_configure_sequence(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 303 const enum adc_channel_num ch_list[], const uint8_t uc_num);
sahilmgandhi 18:6a4db94011d3 304 void adc_enable(void);
sahilmgandhi 18:6a4db94011d3 305 void adc_disable(void);
sahilmgandhi 18:6a4db94011d3 306 void adc_set_callback(Adc *const adc, enum adc_interrupt_source source,
sahilmgandhi 18:6a4db94011d3 307 adc_callback_t callback, uint8_t irq_level);
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /**
sahilmgandhi 18:6a4db94011d3 310 * \internal
sahilmgandhi 18:6a4db94011d3 311 * \brief ADC channel sanity check
sahilmgandhi 18:6a4db94011d3 312 *
sahilmgandhi 18:6a4db94011d3 313 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 314 * \param channel Adc channel number.
sahilmgandhi 18:6a4db94011d3 315 *
sahilmgandhi 18:6a4db94011d3 316 */
sahilmgandhi 18:6a4db94011d3 317 static inline void adc_ch_sanity_check(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 318 const enum adc_channel_num channel)
sahilmgandhi 18:6a4db94011d3 319 {
sahilmgandhi 18:6a4db94011d3 320 if (adc == ADC) {
sahilmgandhi 18:6a4db94011d3 321 Assert((channel < NB_CH_ADC)
sahilmgandhi 18:6a4db94011d3 322 #ifdef TEMP_SENSOR
sahilmgandhi 18:6a4db94011d3 323 ||(channel == ADC_TEMPERATURE_SENSOR)
sahilmgandhi 18:6a4db94011d3 324 #endif
sahilmgandhi 18:6a4db94011d3 325 );
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 UNUSED(channel);
sahilmgandhi 18:6a4db94011d3 329 }
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 #if (SAMG)
sahilmgandhi 18:6a4db94011d3 332 #if SAMG55
sahilmgandhi 18:6a4db94011d3 333 /**
sahilmgandhi 18:6a4db94011d3 334 * \brief Configure ADC clock to mck.
sahilmgandhi 18:6a4db94011d3 335 *
sahilmgandhi 18:6a4db94011d3 336 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 337 *
sahilmgandhi 18:6a4db94011d3 338 */
sahilmgandhi 18:6a4db94011d3 339 static inline void adc_select_clock_source_mck(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 340 {
sahilmgandhi 18:6a4db94011d3 341 uint32_t reg;
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 reg = adc->ADC_EMR;
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 reg &= ~ADC_EMR_SRCCLK_PMC_PCK;
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 adc->ADC_EMR = reg;
sahilmgandhi 18:6a4db94011d3 348 }
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /**
sahilmgandhi 18:6a4db94011d3 351 * \brief Configure ADC clock to pck.
sahilmgandhi 18:6a4db94011d3 352 *
sahilmgandhi 18:6a4db94011d3 353 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 354 *
sahilmgandhi 18:6a4db94011d3 355 */
sahilmgandhi 18:6a4db94011d3 356 static inline void adc_select_clock_source_pck(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 357 {
sahilmgandhi 18:6a4db94011d3 358 uint32_t reg;
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 reg = adc->ADC_EMR;
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 reg |= ADC_EMR_SRCCLK_PMC_PCK;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 adc->ADC_EMR = reg;
sahilmgandhi 18:6a4db94011d3 365 }
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 #else
sahilmgandhi 18:6a4db94011d3 368 /**
sahilmgandhi 18:6a4db94011d3 369 * \brief Configure ADC clock to MCK.
sahilmgandhi 18:6a4db94011d3 370 *
sahilmgandhi 18:6a4db94011d3 371 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 372 *
sahilmgandhi 18:6a4db94011d3 373 */
sahilmgandhi 18:6a4db94011d3 374 static inline void adc_set_clock_mck(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 375 {
sahilmgandhi 18:6a4db94011d3 376 uint32_t reg;
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 reg = adc->ADC_EMR;
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 reg |= ADC_MR_DIV1;
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 adc->ADC_MR = reg;
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * \brief Configure ADC clock to MCK/3.
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 389 *
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391 static inline void adc_set_clock_mck_div3(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 392 {
sahilmgandhi 18:6a4db94011d3 393 uint32_t reg;
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 reg = adc->ADC_MR;
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 reg &= ~ADC_MR_DIV1;
sahilmgandhi 18:6a4db94011d3 398 reg |= ADC_MR_DIV3;
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 adc->ADC_MR = reg;
sahilmgandhi 18:6a4db94011d3 401 }
sahilmgandhi 18:6a4db94011d3 402 #endif
sahilmgandhi 18:6a4db94011d3 403 #endif
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 /**
sahilmgandhi 18:6a4db94011d3 406 * \brief Configure conversion trigger and free run mode.
sahilmgandhi 18:6a4db94011d3 407 *
sahilmgandhi 18:6a4db94011d3 408 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 409 * \param trigger Conversion trigger.
sahilmgandhi 18:6a4db94011d3 410 *
sahilmgandhi 18:6a4db94011d3 411 */
sahilmgandhi 18:6a4db94011d3 412 static inline void adc_set_trigger(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 413 const enum adc_trigger trigger)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 uint32_t reg;
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 reg = adc->ADC_MR;
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 if (trigger == ADC_TRIG_FREERUN) {
sahilmgandhi 18:6a4db94011d3 420 reg |= ADC_MR_FREERUN_ON;
sahilmgandhi 18:6a4db94011d3 421 } else {
sahilmgandhi 18:6a4db94011d3 422 reg &= ~(ADC_MR_TRGSEL_Msk | ADC_MR_TRGEN | ADC_MR_FREERUN_ON);
sahilmgandhi 18:6a4db94011d3 423 reg |= trigger;
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 adc->ADC_MR = reg;
sahilmgandhi 18:6a4db94011d3 427 }
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 void adc_set_resolution(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 430 const enum adc_resolution res);
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 void adc_set_comparison_mode(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 433 const enum adc_cmp_mode mode,
sahilmgandhi 18:6a4db94011d3 434 const enum adc_channel_num channel,
sahilmgandhi 18:6a4db94011d3 435 uint8_t cmp_filter);
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /**
sahilmgandhi 18:6a4db94011d3 438 * \brief Get comparison mode.
sahilmgandhi 18:6a4db94011d3 439 *
sahilmgandhi 18:6a4db94011d3 440 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 441 *
sahilmgandhi 18:6a4db94011d3 442 * \retval Compare mode value.
sahilmgandhi 18:6a4db94011d3 443 */
sahilmgandhi 18:6a4db94011d3 444 static inline enum adc_cmp_mode adc_get_comparison_mode(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 445 {
sahilmgandhi 18:6a4db94011d3 446 return (enum adc_cmp_mode)(adc->ADC_EMR & ADC_EMR_CMPMODE_Msk);
sahilmgandhi 18:6a4db94011d3 447 }
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /**
sahilmgandhi 18:6a4db94011d3 450 * \brief Configure ADC compare window.
sahilmgandhi 18:6a4db94011d3 451 *
sahilmgandhi 18:6a4db94011d3 452 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 453 * \param us_low_threshold Low threshold of compare window.
sahilmgandhi 18:6a4db94011d3 454 * \param us_high_threshold High threshold of compare window.
sahilmgandhi 18:6a4db94011d3 455 */
sahilmgandhi 18:6a4db94011d3 456 static inline void adc_set_comparison_window(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 457 const uint16_t us_low_threshold,
sahilmgandhi 18:6a4db94011d3 458 const uint16_t us_high_threshold)
sahilmgandhi 18:6a4db94011d3 459 {
sahilmgandhi 18:6a4db94011d3 460 adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) |
sahilmgandhi 18:6a4db94011d3 461 ADC_CWR_HIGHTHRES(us_high_threshold);
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 /**
sahilmgandhi 18:6a4db94011d3 465 * \brief Enable or disable write protection of ADC registers.
sahilmgandhi 18:6a4db94011d3 466 *
sahilmgandhi 18:6a4db94011d3 467 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 468 * \param is_enable 1 to enable, 0 to disable.
sahilmgandhi 18:6a4db94011d3 469 */
sahilmgandhi 18:6a4db94011d3 470 static inline void adc_set_writeprotect(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 471 const bool is_enable)
sahilmgandhi 18:6a4db94011d3 472 {
sahilmgandhi 18:6a4db94011d3 473 if (is_enable) {
sahilmgandhi 18:6a4db94011d3 474 adc->ADC_WPMR = ADC_WPMR_WPEN | ADC_WPMR_WPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 475 } else {
sahilmgandhi 18:6a4db94011d3 476 adc->ADC_WPMR = ADC_WPMR_WPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 477 }
sahilmgandhi 18:6a4db94011d3 478 }
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /**
sahilmgandhi 18:6a4db94011d3 481 * \brief Indicate write protect status.
sahilmgandhi 18:6a4db94011d3 482 *
sahilmgandhi 18:6a4db94011d3 483 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 484 *
sahilmgandhi 18:6a4db94011d3 485 * \return 0 if no write protect violation occurred, or 16-bit write protect
sahilmgandhi 18:6a4db94011d3 486 * violation source.
sahilmgandhi 18:6a4db94011d3 487 */
sahilmgandhi 18:6a4db94011d3 488 static inline uint32_t adc_get_writeprotect_status(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 489 {
sahilmgandhi 18:6a4db94011d3 490 uint32_t reg_value;
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 reg_value = adc->ADC_WPSR;
sahilmgandhi 18:6a4db94011d3 493 if (reg_value & ADC_WPSR_WPVS) {
sahilmgandhi 18:6a4db94011d3 494 return (reg_value & ADC_WPSR_WPVSRC_Msk) >> ADC_WPSR_WPVSRC_Pos;
sahilmgandhi 18:6a4db94011d3 495 } else {
sahilmgandhi 18:6a4db94011d3 496 return 0;
sahilmgandhi 18:6a4db94011d3 497 }
sahilmgandhi 18:6a4db94011d3 498 }
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /**
sahilmgandhi 18:6a4db94011d3 501 * \brief Get ADC overrun error status.
sahilmgandhi 18:6a4db94011d3 502 *
sahilmgandhi 18:6a4db94011d3 503 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 504 *
sahilmgandhi 18:6a4db94011d3 505 * \return ADC overrun error status.
sahilmgandhi 18:6a4db94011d3 506 */
sahilmgandhi 18:6a4db94011d3 507 static inline uint32_t adc_get_overrun_status(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 return adc->ADC_OVER;
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 /**
sahilmgandhi 18:6a4db94011d3 513 * \brief Set ADC averaging on single trigger event
sahilmgandhi 18:6a4db94011d3 514 *
sahilmgandhi 18:6a4db94011d3 515 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 516 */
sahilmgandhi 18:6a4db94011d3 517 static inline void adc_average_on_single_trigger(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 adc->ADC_EMR |= ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE;
sahilmgandhi 18:6a4db94011d3 520 }
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 /**
sahilmgandhi 18:6a4db94011d3 523 * \brief Set ADC averaging on serval trigger events
sahilmgandhi 18:6a4db94011d3 524 *
sahilmgandhi 18:6a4db94011d3 525 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 526 */
sahilmgandhi 18:6a4db94011d3 527 static inline void adc_average_on_multi_trigger(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 528 {
sahilmgandhi 18:6a4db94011d3 529 adc->ADC_EMR &= ~ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE;
sahilmgandhi 18:6a4db94011d3 530 }
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /**
sahilmgandhi 18:6a4db94011d3 533 * \brief Start analog-to-digital conversion.
sahilmgandhi 18:6a4db94011d3 534 *
sahilmgandhi 18:6a4db94011d3 535 * \note If one of the hardware event is selected as ADC trigger,
sahilmgandhi 18:6a4db94011d3 536 * this function can NOT start analog to digital conversion.
sahilmgandhi 18:6a4db94011d3 537 *
sahilmgandhi 18:6a4db94011d3 538 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 539 */
sahilmgandhi 18:6a4db94011d3 540 static inline void adc_start_software_conversion(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 541 {
sahilmgandhi 18:6a4db94011d3 542 adc->ADC_CR = ADC_CR_START;
sahilmgandhi 18:6a4db94011d3 543 }
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 void adc_set_power_mode(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 546 const enum adc_power_mode mode);
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 /**
sahilmgandhi 18:6a4db94011d3 549 * \brief Enable the specified ADC channel.
sahilmgandhi 18:6a4db94011d3 550 *
sahilmgandhi 18:6a4db94011d3 551 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 552 * \param adc_ch Adc channel number.
sahilmgandhi 18:6a4db94011d3 553 */
sahilmgandhi 18:6a4db94011d3 554 static inline void adc_channel_enable(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 555 const enum adc_channel_num adc_ch)
sahilmgandhi 18:6a4db94011d3 556 {
sahilmgandhi 18:6a4db94011d3 557 if (adc_ch != ADC_CHANNEL_ALL) {
sahilmgandhi 18:6a4db94011d3 558 adc_ch_sanity_check(adc, adc_ch);
sahilmgandhi 18:6a4db94011d3 559 }
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 adc->ADC_CHER = (adc_ch == ADC_CHANNEL_ALL) ?
sahilmgandhi 18:6a4db94011d3 562 ADC_CHANNEL_ALL : 1 << adc_ch;
sahilmgandhi 18:6a4db94011d3 563 }
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * \brief Disable the specified ADC channel.
sahilmgandhi 18:6a4db94011d3 567 *
sahilmgandhi 18:6a4db94011d3 568 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 569 * \param adc_ch Adc channel number.
sahilmgandhi 18:6a4db94011d3 570 */
sahilmgandhi 18:6a4db94011d3 571 static inline void adc_channel_disable(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 572 const enum adc_channel_num adc_ch)
sahilmgandhi 18:6a4db94011d3 573 {
sahilmgandhi 18:6a4db94011d3 574 if (adc_ch != ADC_CHANNEL_ALL) {
sahilmgandhi 18:6a4db94011d3 575 adc_ch_sanity_check(adc, adc_ch);
sahilmgandhi 18:6a4db94011d3 576 }
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 adc->ADC_CHDR = (adc_ch == ADC_CHANNEL_ALL) ?
sahilmgandhi 18:6a4db94011d3 579 ADC_CHANNEL_ALL : 1 << adc_ch;
sahilmgandhi 18:6a4db94011d3 580 }
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 /**
sahilmgandhi 18:6a4db94011d3 583 * \brief Get the ADC channel status.
sahilmgandhi 18:6a4db94011d3 584 *
sahilmgandhi 18:6a4db94011d3 585 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 586 * \param adc_ch Adc channel number.
sahilmgandhi 18:6a4db94011d3 587 *
sahilmgandhi 18:6a4db94011d3 588 * \retval 1 if channel is enabled.
sahilmgandhi 18:6a4db94011d3 589 * \retval 0 if channel is disabled.
sahilmgandhi 18:6a4db94011d3 590 */
sahilmgandhi 18:6a4db94011d3 591 static inline uint32_t adc_channel_get_status(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 592 const enum adc_channel_num adc_ch)
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 adc_ch_sanity_check(adc, adc_ch);
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 return adc->ADC_CHSR & (1 << adc_ch);
sahilmgandhi 18:6a4db94011d3 597 }
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /**
sahilmgandhi 18:6a4db94011d3 600 * \brief Read the Converted Data of the selected channel.
sahilmgandhi 18:6a4db94011d3 601 *
sahilmgandhi 18:6a4db94011d3 602 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 603 * \param adc_ch Adc channel number.
sahilmgandhi 18:6a4db94011d3 604 *
sahilmgandhi 18:6a4db94011d3 605 * \return ADC converted value of the selected channel.
sahilmgandhi 18:6a4db94011d3 606 */
sahilmgandhi 18:6a4db94011d3 607 static inline uint32_t adc_channel_get_value(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 608 enum adc_channel_num adc_ch)
sahilmgandhi 18:6a4db94011d3 609 {
sahilmgandhi 18:6a4db94011d3 610 adc_ch_sanity_check(adc, adc_ch);
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 return adc->ADC_CDR[adc_ch];
sahilmgandhi 18:6a4db94011d3 613 }
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 /**
sahilmgandhi 18:6a4db94011d3 616 * \brief Get the Last Data Converted.
sahilmgandhi 18:6a4db94011d3 617 *
sahilmgandhi 18:6a4db94011d3 618 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 619 *
sahilmgandhi 18:6a4db94011d3 620 * \return ADC latest converted value.
sahilmgandhi 18:6a4db94011d3 621 */
sahilmgandhi 18:6a4db94011d3 622 static inline uint32_t adc_get_latest_value(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 623 {
sahilmgandhi 18:6a4db94011d3 624 return adc->ADC_LCDR & ADC_LCDR_LDATA_Msk;
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 /**
sahilmgandhi 18:6a4db94011d3 628 * \brief Get the Last Converted Channel Number.
sahilmgandhi 18:6a4db94011d3 629 *
sahilmgandhi 18:6a4db94011d3 630 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 631 *
sahilmgandhi 18:6a4db94011d3 632 * \return ADC Last Converted Channel Number.
sahilmgandhi 18:6a4db94011d3 633 */
sahilmgandhi 18:6a4db94011d3 634 static inline uint32_t adc_get_latest_chan_num(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 635 {
sahilmgandhi 18:6a4db94011d3 636 #if SAMG55
sahilmgandhi 18:6a4db94011d3 637 return (adc->ADC_LCDR & ADC_LCDR_CHNBOSR_Msk) >> ADC_LCDR_CHNBOSR_Pos;
sahilmgandhi 18:6a4db94011d3 638 #else
sahilmgandhi 18:6a4db94011d3 639 return (adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos;
sahilmgandhi 18:6a4db94011d3 640 #endif
sahilmgandhi 18:6a4db94011d3 641 }
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 void adc_enable_interrupt(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 644 enum adc_interrupt_source interrupt_source);
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 void adc_disable_interrupt(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 647 enum adc_interrupt_source interrupt_source);
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 /**
sahilmgandhi 18:6a4db94011d3 650 * \brief Get ADC interrupt status.
sahilmgandhi 18:6a4db94011d3 651 *
sahilmgandhi 18:6a4db94011d3 652 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 653 *
sahilmgandhi 18:6a4db94011d3 654 * \return The interrupt status value.
sahilmgandhi 18:6a4db94011d3 655 */
sahilmgandhi 18:6a4db94011d3 656 static inline uint32_t adc_get_interrupt_status(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 657 {
sahilmgandhi 18:6a4db94011d3 658 return adc->ADC_ISR;
sahilmgandhi 18:6a4db94011d3 659 }
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 /**
sahilmgandhi 18:6a4db94011d3 662 * \brief Get ADC interrupt mask.
sahilmgandhi 18:6a4db94011d3 663 *
sahilmgandhi 18:6a4db94011d3 664 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 665 *
sahilmgandhi 18:6a4db94011d3 666 * \return The interrupt mask value.
sahilmgandhi 18:6a4db94011d3 667 */
sahilmgandhi 18:6a4db94011d3 668 static inline uint32_t adc_get_interrupt_mask(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 return adc->ADC_IMR;
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /**
sahilmgandhi 18:6a4db94011d3 674 * \brief Get PDC registers base address.
sahilmgandhi 18:6a4db94011d3 675 *
sahilmgandhi 18:6a4db94011d3 676 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 677 *
sahilmgandhi 18:6a4db94011d3 678 * \return Adc Pdc register base address.
sahilmgandhi 18:6a4db94011d3 679 */
sahilmgandhi 18:6a4db94011d3 680 static inline Pdc *adc_get_pdc_base(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 Pdc *p_pdc_base = NULL;
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 if (adc == ADC) {
sahilmgandhi 18:6a4db94011d3 685 p_pdc_base = PDC_ADC;
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 return p_pdc_base;
sahilmgandhi 18:6a4db94011d3 689 }
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 /**
sahilmgandhi 18:6a4db94011d3 692 * \brief Launch an automatic calibration of the ADC on next sequence.
sahilmgandhi 18:6a4db94011d3 693 *
sahilmgandhi 18:6a4db94011d3 694 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 695 *
sahilmgandhi 18:6a4db94011d3 696 * \retval STATUS_OK An automatic calibration is launched.
sahilmgandhi 18:6a4db94011d3 697 * \retval STATUS_ERR_BUSY Automatic calibration can not be launched because
sahilmgandhi 18:6a4db94011d3 698 * the ADC is in freerun mode.
sahilmgandhi 18:6a4db94011d3 699 */
sahilmgandhi 18:6a4db94011d3 700 static inline enum status_code adc_start_calibration(Adc *const adc)
sahilmgandhi 18:6a4db94011d3 701 {
sahilmgandhi 18:6a4db94011d3 702 if ((adc->ADC_MR & ADC_MR_FREERUN) == ADC_MR_FREERUN_ON) {
sahilmgandhi 18:6a4db94011d3 703 return STATUS_ERR_BUSY;
sahilmgandhi 18:6a4db94011d3 704 }
sahilmgandhi 18:6a4db94011d3 705
sahilmgandhi 18:6a4db94011d3 706 adc->ADC_CR = ADC_CR_AUTOCAL;
sahilmgandhi 18:6a4db94011d3 707 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 708 }
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 #if (SAM4N)
sahilmgandhi 18:6a4db94011d3 711 /**
sahilmgandhi 18:6a4db94011d3 712 * \brief ADC Reference Voltage Selection
sahilmgandhi 18:6a4db94011d3 713 *
sahilmgandhi 18:6a4db94011d3 714 * \param adc Base address of the ADC.
sahilmgandhi 18:6a4db94011d3 715 * \param adc_ref_src The source selection for ADC reference voltage,
sahilmgandhi 18:6a4db94011d3 716 * ADC_REFER_VOL_EXTERNAL - the external pin ADVREF defines the voltage reference.
sahilmgandhi 18:6a4db94011d3 717 * ADC_REFER_VOL_STUCK_AT_MIN - the internal reference voltage is stuck at the minimum value
sahilmgandhi 18:6a4db94011d3 718 * ADC_REFER_VOL_VDDANA - the internal voltage reference is forced to VDDANA. Effective only if ONREF is 1.
sahilmgandhi 18:6a4db94011d3 719 * ADC_REFER_VOL_IRVS - the internal reference voltage is defined by field IRVS
sahilmgandhi 18:6a4db94011d3 720 * See the product electrical characteristics for further details.
sahilmgandhi 18:6a4db94011d3 721 * \param irvs Internal reference volatage selection, only be effective when
sahilmgandhi 18:6a4db94011d3 722 * adc_ref_src equals to ADC_REFER_VOL_IRVS
sahilmgandhi 18:6a4db94011d3 723 */
sahilmgandhi 18:6a4db94011d3 724 static inline void adc_ref_vol_sel(Adc *const adc,
sahilmgandhi 18:6a4db94011d3 725 enum adc_refer_voltage_source adc_ref_src,
sahilmgandhi 18:6a4db94011d3 726 uint8_t irvs)
sahilmgandhi 18:6a4db94011d3 727 {
sahilmgandhi 18:6a4db94011d3 728 if (ADC_REFER_VOL_EXTERNAL == adc_ref_src) {
sahilmgandhi 18:6a4db94011d3 729 adc->ADC_ACR &= ~ADC_ACR_ONREF_EN;
sahilmgandhi 18:6a4db94011d3 730 } else if (ADC_REFER_VOL_STUCK_AT_MIN == adc_ref_src) {
sahilmgandhi 18:6a4db94011d3 731 adc->ADC_ACR |= ADC_ACR_ONREF_EN;
sahilmgandhi 18:6a4db94011d3 732 adc->ADC_ACR &= ~(ADC_ACR_IRVCE_EN | ADC_ACR_FORCEREF_EN);
sahilmgandhi 18:6a4db94011d3 733 } else if (ADC_REFER_VOL_VDDANA == adc_ref_src) {
sahilmgandhi 18:6a4db94011d3 734 adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_FORCEREF_EN;
sahilmgandhi 18:6a4db94011d3 735 } else if (ADC_REFER_VOL_IRVS == adc_ref_src) {
sahilmgandhi 18:6a4db94011d3 736 adc->ADC_ACR &= ~ADC_ACR_FORCEREF_EN;
sahilmgandhi 18:6a4db94011d3 737 adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_IRVCE_EN |
sahilmgandhi 18:6a4db94011d3 738 (irvs << ADC_ACR_IRVS_Pos);
sahilmgandhi 18:6a4db94011d3 739 }
sahilmgandhi 18:6a4db94011d3 740 }
sahilmgandhi 18:6a4db94011d3 741 #endif
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 /**
sahilmgandhi 18:6a4db94011d3 744 * \page sam_adc2_quickstart Quickstart guide for ADC driver
sahilmgandhi 18:6a4db94011d3 745 *
sahilmgandhi 18:6a4db94011d3 746 * This is the quickstart guide for the \ref sam_drivers_adc2_group
sahilmgandhi 18:6a4db94011d3 747 * "ADC2 driver" with step-by-step instructions on how to configure and use
sahilmgandhi 18:6a4db94011d3 748 * the driver in a selection of use cases.
sahilmgandhi 18:6a4db94011d3 749 *
sahilmgandhi 18:6a4db94011d3 750 * The use cases contain several code fragments. The code fragments in the
sahilmgandhi 18:6a4db94011d3 751 * steps for setup can be copied into a custom initialization function, while
sahilmgandhi 18:6a4db94011d3 752 * the steps for usage can be copied into, e.g., the main application function.
sahilmgandhi 18:6a4db94011d3 753 *
sahilmgandhi 18:6a4db94011d3 754 * \section adc_basic_use_case Basic use case
sahilmgandhi 18:6a4db94011d3 755 * In this basic use case, the ADC module and single channel are configured for:
sahilmgandhi 18:6a4db94011d3 756 * - 10 -bit resolution
sahilmgandhi 18:6a4db94011d3 757 * - ADC clock frequency is 6MHz
sahilmgandhi 18:6a4db94011d3 758 * - Start Up Time is 64 periods ADC clock
sahilmgandhi 18:6a4db94011d3 759 * - Tracking Time is 3 periods of ADC clock
sahilmgandhi 18:6a4db94011d3 760 * - Transfer Period field shall be programmed with 2 as datasheet said
sahilmgandhi 18:6a4db94011d3 761 * - The controller converts channels in a simple numeric order
sahilmgandhi 18:6a4db94011d3 762 * - Appends the channel number to the conversion result in AFE_LDCR register
sahilmgandhi 18:6a4db94011d3 763 * - Single Trigger is optional to get an averaged value
sahilmgandhi 18:6a4db94011d3 764 * - Software triggering of conversions
sahilmgandhi 18:6a4db94011d3 765 * - Single channel measurement
sahilmgandhi 18:6a4db94011d3 766 * - ADC_CHANNEL_1 of ADC as input
sahilmgandhi 18:6a4db94011d3 767 *
sahilmgandhi 18:6a4db94011d3 768 * \subsection sam_adc2_quickstart_prereq Prerequisites
sahilmgandhi 18:6a4db94011d3 769 * -# \ref sysclk_group "System Clock Management (Sysclock)"
sahilmgandhi 18:6a4db94011d3 770 *
sahilmgandhi 18:6a4db94011d3 771 * \section adc_basic_use_case_setup Setup steps
sahilmgandhi 18:6a4db94011d3 772 * \subsection adc_basic_use_case_setup_code Example code
sahilmgandhi 18:6a4db94011d3 773 * Add to application C-file:
sahilmgandhi 18:6a4db94011d3 774 * \code
sahilmgandhi 18:6a4db94011d3 775 adc_enable();
sahilmgandhi 18:6a4db94011d3 776 adc_get_config_defaults(&adc_cfg);
sahilmgandhi 18:6a4db94011d3 777 adc_init(ADC, &adc_cfg);
sahilmgandhi 18:6a4db94011d3 778 adc_set_trigger(ADC, ADC_TRIG_SW);
sahilmgandhi 18:6a4db94011d3 779 adc_channel_enable(ADC, ADC_CHANNEL_1);
sahilmgandhi 18:6a4db94011d3 780 \endcode
sahilmgandhi 18:6a4db94011d3 781 *
sahilmgandhi 18:6a4db94011d3 782 * \subsection adc_basic_use_case_setup_flow Workflow
sahilmgandhi 18:6a4db94011d3 783 * -# Enable ADC Module:
sahilmgandhi 18:6a4db94011d3 784 * - \code adc_enable(); \endcode
sahilmgandhi 18:6a4db94011d3 785 * -# Get the ADC default configurations:
sahilmgandhi 18:6a4db94011d3 786 * - \code adc_get_config_defaults(&adc_cfg); \endcode
sahilmgandhi 18:6a4db94011d3 787 * -# Initialize the ADC Module:
sahilmgandhi 18:6a4db94011d3 788 * - \code adc_init(ADC, &adc_cfg); \endcode
sahilmgandhi 18:6a4db94011d3 789 * -# Configure conversion trigger and free run mode:
sahilmgandhi 18:6a4db94011d3 790 * - \code adc_set_trigger(ADC, ADC_TRIG_SW); \endcode
sahilmgandhi 18:6a4db94011d3 791 * -# Enable Channel:
sahilmgandhi 18:6a4db94011d3 792 * - \code adc_channel_enable(ADC, ADC_CHANNEL_1); \endcode
sahilmgandhi 18:6a4db94011d3 793 *
sahilmgandhi 18:6a4db94011d3 794 * \section adc_basic_use_case_usage Usage steps
sahilmgandhi 18:6a4db94011d3 795 * \subsection adc_basic_use_case_usage_code Example code
sahilmgandhi 18:6a4db94011d3 796 * Add to, e.g., main loop in application C-file:
sahilmgandhi 18:6a4db94011d3 797 * \code
sahilmgandhi 18:6a4db94011d3 798 adc_start_software_conversion(ADC);
sahilmgandhi 18:6a4db94011d3 799 while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1));
sahilmgandhi 18:6a4db94011d3 800 uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1);
sahilmgandhi 18:6a4db94011d3 801 \endcode
sahilmgandhi 18:6a4db94011d3 802 *
sahilmgandhi 18:6a4db94011d3 803 * \subsection adc_basic_use_case_usage_flow Workflow
sahilmgandhi 18:6a4db94011d3 804 * -# Start ADC conversion on channel:
sahilmgandhi 18:6a4db94011d3 805 * - \code adc_start_software_conversion(ADC); \endcode
sahilmgandhi 18:6a4db94011d3 806 * -# Wait for the conversion over:
sahilmgandhi 18:6a4db94011d3 807 * - \code while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1));
sahilmgandhi 18:6a4db94011d3 808 \endcode
sahilmgandhi 18:6a4db94011d3 809 * -# Get the conversion result:
sahilmgandhi 18:6a4db94011d3 810 * - \code uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1);
sahilmgandhi 18:6a4db94011d3 811 \endcode
sahilmgandhi 18:6a4db94011d3 812 */
sahilmgandhi 18:6a4db94011d3 813 #endif /* ADC2_H_INCLUDED */