MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief SAM TC - Timer Counter Driver
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #include "tc.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 #if TC_ASYNC == true
sahilmgandhi 18:6a4db94011d3 50 # include "tc_interrupt.h"
sahilmgandhi 18:6a4db94011d3 51 # include <system_interrupt.h>
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** \internal
sahilmgandhi 18:6a4db94011d3 54 * Converts a given TC index to its interrupt vector index.
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56 # define _TC_INTERRUPT_VECT_NUM(n, unused) \
sahilmgandhi 18:6a4db94011d3 57 SYSTEM_INTERRUPT_MODULE_TC##n,
sahilmgandhi 18:6a4db94011d3 58 #endif
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 #if !defined(__DOXYGEN__)
sahilmgandhi 18:6a4db94011d3 61 # define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) ,
sahilmgandhi 18:6a4db94011d3 62 # define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) ,
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 # define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) }
sahilmgandhi 18:6a4db94011d3 65 # define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) }
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 #endif
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /**
sahilmgandhi 18:6a4db94011d3 70 * \internal Find the index of given TC module instance.
sahilmgandhi 18:6a4db94011d3 71 *
sahilmgandhi 18:6a4db94011d3 72 * \param[in] TC module instance pointer.
sahilmgandhi 18:6a4db94011d3 73 *
sahilmgandhi 18:6a4db94011d3 74 * \return Index of the given TC module instance.
sahilmgandhi 18:6a4db94011d3 75 */
sahilmgandhi 18:6a4db94011d3 76 uint8_t _tc_get_inst_index(
sahilmgandhi 18:6a4db94011d3 77 Tc *const hw)
sahilmgandhi 18:6a4db94011d3 78 {
sahilmgandhi 18:6a4db94011d3 79 /* List of available TC modules. */
sahilmgandhi 18:6a4db94011d3 80 Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /* Find index for TC instance. */
sahilmgandhi 18:6a4db94011d3 83 for (uint32_t i = 0; i < TC_INST_NUM; i++) {
sahilmgandhi 18:6a4db94011d3 84 if (hw == tc_modules[i]) {
sahilmgandhi 18:6a4db94011d3 85 return i;
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /* Invalid data given. */
sahilmgandhi 18:6a4db94011d3 90 Assert(false);
sahilmgandhi 18:6a4db94011d3 91 return 0;
sahilmgandhi 18:6a4db94011d3 92 }
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /**
sahilmgandhi 18:6a4db94011d3 96 * \brief Initializes a hardware TC module instance.
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 * Enables the clock and initializes the TC module, based on the given
sahilmgandhi 18:6a4db94011d3 99 * configuration values.
sahilmgandhi 18:6a4db94011d3 100 *
sahilmgandhi 18:6a4db94011d3 101 * \param[in,out] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 102 * \param[in] hw Pointer to the TC hardware module
sahilmgandhi 18:6a4db94011d3 103 * \param[in] config Pointer to the TC configuration options struct
sahilmgandhi 18:6a4db94011d3 104 *
sahilmgandhi 18:6a4db94011d3 105 * \return Status of the initialization procedure.
sahilmgandhi 18:6a4db94011d3 106 *
sahilmgandhi 18:6a4db94011d3 107 * \retval STATUS_OK The module was initialized successfully
sahilmgandhi 18:6a4db94011d3 108 * \retval STATUS_BUSY Hardware module was busy when the
sahilmgandhi 18:6a4db94011d3 109 * initialization procedure was attempted
sahilmgandhi 18:6a4db94011d3 110 * \retval STATUS_INVALID_ARG An invalid configuration option or argument
sahilmgandhi 18:6a4db94011d3 111 * was supplied
sahilmgandhi 18:6a4db94011d3 112 * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the
sahilmgandhi 18:6a4db94011d3 113 * hardware module is configured in 32-bit
sahilmgandhi 18:6a4db94011d3 114 * slave mode
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116 enum status_code tc_init(
sahilmgandhi 18:6a4db94011d3 117 struct tc_module *const module_inst,
sahilmgandhi 18:6a4db94011d3 118 Tc *const hw,
sahilmgandhi 18:6a4db94011d3 119 const struct tc_config *const config)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 122 Assert(hw);
sahilmgandhi 18:6a4db94011d3 123 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 124 Assert(config);
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /* Temporary variable to hold all updates to the CTRLA
sahilmgandhi 18:6a4db94011d3 127 * register before they are written to it */
sahilmgandhi 18:6a4db94011d3 128 uint16_t ctrla_tmp = 0;
sahilmgandhi 18:6a4db94011d3 129 /* Temporary variable to hold all updates to the CTRLBSET
sahilmgandhi 18:6a4db94011d3 130 * register before they are written to it */
sahilmgandhi 18:6a4db94011d3 131 uint8_t ctrlbset_tmp = 0;
sahilmgandhi 18:6a4db94011d3 132 /* Temporary variable to hold all updates to the CTRLC
sahilmgandhi 18:6a4db94011d3 133 * register before they are written to it */
sahilmgandhi 18:6a4db94011d3 134 uint8_t ctrlc_tmp = 0;
sahilmgandhi 18:6a4db94011d3 135 /* Temporary variable to hold TC instance number */
sahilmgandhi 18:6a4db94011d3 136 uint8_t instance = _tc_get_inst_index(hw);
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /* Array of GLCK ID for different TC instances */
sahilmgandhi 18:6a4db94011d3 139 uint8_t inst_gclk_id[] = TC_INST_GCLK_ID;
sahilmgandhi 18:6a4db94011d3 140 /* Array of PM APBC mask bit position for different TC instances */
sahilmgandhi 18:6a4db94011d3 141 uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK;
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 struct system_pinmux_config pin_config;
sahilmgandhi 18:6a4db94011d3 144 struct system_gclk_chan_config gclk_chan_config;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 #if TC_ASYNC == true
sahilmgandhi 18:6a4db94011d3 147 /* Initialize parameters */
sahilmgandhi 18:6a4db94011d3 148 for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
sahilmgandhi 18:6a4db94011d3 149 module_inst->callback[i] = NULL;
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151 module_inst->register_callback_mask = 0x00;
sahilmgandhi 18:6a4db94011d3 152 module_inst->enable_callback_mask = 0x00;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /* Register this instance for callbacks*/
sahilmgandhi 18:6a4db94011d3 155 _tc_instances[instance] = module_inst;
sahilmgandhi 18:6a4db94011d3 156 #endif
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /* Associate the given device instance with the hardware module */
sahilmgandhi 18:6a4db94011d3 159 module_inst->hw = hw;
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 #if SAMD10 || SAMD11
sahilmgandhi 18:6a4db94011d3 162 /* Check if even numbered TC modules are being configured in 32-bit
sahilmgandhi 18:6a4db94011d3 163 * counter size. Only odd numbered counters are allowed to be
sahilmgandhi 18:6a4db94011d3 164 * configured in 32-bit counter size.
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166 if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
sahilmgandhi 18:6a4db94011d3 167 !((instance + TC_INSTANCE_OFFSET) & 0x01)) {
sahilmgandhi 18:6a4db94011d3 168 Assert(false);
sahilmgandhi 18:6a4db94011d3 169 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171 #else
sahilmgandhi 18:6a4db94011d3 172 /* Check if odd numbered TC modules are being configured in 32-bit
sahilmgandhi 18:6a4db94011d3 173 * counter size. Only even numbered counters are allowed to be
sahilmgandhi 18:6a4db94011d3 174 * configured in 32-bit counter size.
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
sahilmgandhi 18:6a4db94011d3 177 ((instance + TC_INSTANCE_OFFSET) & 0x01)) {
sahilmgandhi 18:6a4db94011d3 178 Assert(false);
sahilmgandhi 18:6a4db94011d3 179 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181 #endif
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /* Make the counter size variable in the module_inst struct reflect
sahilmgandhi 18:6a4db94011d3 184 * the counter size in the module
sahilmgandhi 18:6a4db94011d3 185 */
sahilmgandhi 18:6a4db94011d3 186 module_inst->counter_size = config->counter_size;
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
sahilmgandhi 18:6a4db94011d3 189 /* We are in the middle of a reset. Abort. */
sahilmgandhi 18:6a4db94011d3 190 return STATUS_BUSY;
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
sahilmgandhi 18:6a4db94011d3 194 /* Module is used as a slave */
sahilmgandhi 18:6a4db94011d3 195 return STATUS_ERR_DENIED;
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
sahilmgandhi 18:6a4db94011d3 199 /* Module must be disabled before initialization. Abort. */
sahilmgandhi 18:6a4db94011d3 200 return STATUS_ERR_DENIED;
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /* Set up the TC PWM out pin for channel 0 */
sahilmgandhi 18:6a4db94011d3 204 if (config->pwm_channel[0].enabled) {
sahilmgandhi 18:6a4db94011d3 205 system_pinmux_get_config_defaults(&pin_config);
sahilmgandhi 18:6a4db94011d3 206 pin_config.mux_position = config->pwm_channel[0].pin_mux;
sahilmgandhi 18:6a4db94011d3 207 pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
sahilmgandhi 18:6a4db94011d3 208 system_pinmux_pin_set_config(
sahilmgandhi 18:6a4db94011d3 209 config->pwm_channel[0].pin_out, &pin_config);
sahilmgandhi 18:6a4db94011d3 210 }
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /* Set up the TC PWM out pin for channel 1 */
sahilmgandhi 18:6a4db94011d3 213 if (config->pwm_channel[1].enabled) {
sahilmgandhi 18:6a4db94011d3 214 system_pinmux_get_config_defaults(&pin_config);
sahilmgandhi 18:6a4db94011d3 215 pin_config.mux_position = config->pwm_channel[1].pin_mux;
sahilmgandhi 18:6a4db94011d3 216 pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
sahilmgandhi 18:6a4db94011d3 217 system_pinmux_pin_set_config(
sahilmgandhi 18:6a4db94011d3 218 config->pwm_channel[1].pin_out, &pin_config);
sahilmgandhi 18:6a4db94011d3 219 }
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /* Enable the user interface clock in the PM */
sahilmgandhi 18:6a4db94011d3 222 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
sahilmgandhi 18:6a4db94011d3 223 inst_pm_apbmask[instance]);
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 /* Enable the slave counter if counter_size is 32-bit */
sahilmgandhi 18:6a4db94011d3 226 if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) {
sahilmgandhi 18:6a4db94011d3 227 /* Enable the user interface clock in the PM */
sahilmgandhi 18:6a4db94011d3 228 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
sahilmgandhi 18:6a4db94011d3 229 inst_pm_apbmask[instance + 1]);
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /* Setup clock for module */
sahilmgandhi 18:6a4db94011d3 233 system_gclk_chan_get_config_defaults(&gclk_chan_config);
sahilmgandhi 18:6a4db94011d3 234 gclk_chan_config.source_generator = config->clock_source;
sahilmgandhi 18:6a4db94011d3 235 system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
sahilmgandhi 18:6a4db94011d3 236 system_gclk_chan_enable(inst_gclk_id[instance]);
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Set ctrla register */
sahilmgandhi 18:6a4db94011d3 239 ctrla_tmp =
sahilmgandhi 18:6a4db94011d3 240 (uint32_t)config->counter_size |
sahilmgandhi 18:6a4db94011d3 241 (uint32_t)config->wave_generation |
sahilmgandhi 18:6a4db94011d3 242 (uint32_t)config->reload_action |
sahilmgandhi 18:6a4db94011d3 243 (uint32_t)config->clock_prescaler;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 if (config->run_in_standby) {
sahilmgandhi 18:6a4db94011d3 246 ctrla_tmp |= TC_CTRLA_RUNSTDBY;
sahilmgandhi 18:6a4db94011d3 247 }
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /* Write configuration to register */
sahilmgandhi 18:6a4db94011d3 250 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 251 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 252 }
sahilmgandhi 18:6a4db94011d3 253 hw->COUNT8.CTRLA.reg = ctrla_tmp;
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /* Set ctrlb register */
sahilmgandhi 18:6a4db94011d3 256 if (config->oneshot) {
sahilmgandhi 18:6a4db94011d3 257 ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 if (config->count_direction) {
sahilmgandhi 18:6a4db94011d3 261 ctrlbset_tmp |= TC_CTRLBSET_DIR;
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /* Clear old ctrlb configuration */
sahilmgandhi 18:6a4db94011d3 265 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 266 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 267 }
sahilmgandhi 18:6a4db94011d3 268 hw->COUNT8.CTRLBCLR.reg = 0xFF;
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /* Check if we actually need to go into a wait state. */
sahilmgandhi 18:6a4db94011d3 271 if (ctrlbset_tmp) {
sahilmgandhi 18:6a4db94011d3 272 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 273 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 274 }
sahilmgandhi 18:6a4db94011d3 275 /* Write configuration to register */
sahilmgandhi 18:6a4db94011d3 276 hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /* Set ctrlc register*/
sahilmgandhi 18:6a4db94011d3 280 ctrlc_tmp = config->waveform_invert_output;
sahilmgandhi 18:6a4db94011d3 281 for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
sahilmgandhi 18:6a4db94011d3 282 if (config->enable_capture_on_channel[i] == true) {
sahilmgandhi 18:6a4db94011d3 283 ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i);
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285 }
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /* Write configuration to register */
sahilmgandhi 18:6a4db94011d3 288 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 289 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 290 }
sahilmgandhi 18:6a4db94011d3 291 hw->COUNT8.CTRLC.reg = ctrlc_tmp;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /* Write configuration to register */
sahilmgandhi 18:6a4db94011d3 294 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 295 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 296 }
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* Switch for TC counter size */
sahilmgandhi 18:6a4db94011d3 299 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 300 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 301 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 302 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 hw->COUNT8.COUNT.reg =
sahilmgandhi 18:6a4db94011d3 306 config->counter_8_bit.value;
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 310 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 hw->COUNT8.PER.reg =
sahilmgandhi 18:6a4db94011d3 314 config->counter_8_bit.period;
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 317 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 hw->COUNT8.CC[0].reg =
sahilmgandhi 18:6a4db94011d3 321 config->counter_8_bit.compare_capture_channel[0];
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 324 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 hw->COUNT8.CC[1].reg =
sahilmgandhi 18:6a4db94011d3 328 config->counter_8_bit.compare_capture_channel[1];
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 333 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 334 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 335 }
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 hw->COUNT16.COUNT.reg
sahilmgandhi 18:6a4db94011d3 338 = config->counter_16_bit.value;
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 341 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 342 }
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 hw->COUNT16.CC[0].reg =
sahilmgandhi 18:6a4db94011d3 345 config->counter_16_bit.compare_capture_channel[0];
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 348 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 349 }
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 hw->COUNT16.CC[1].reg =
sahilmgandhi 18:6a4db94011d3 352 config->counter_16_bit.compare_capture_channel[1];
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 357 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 358 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 359 }
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 hw->COUNT32.COUNT.reg
sahilmgandhi 18:6a4db94011d3 362 = config->counter_32_bit.value;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 365 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 366 }
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 hw->COUNT32.CC[0].reg =
sahilmgandhi 18:6a4db94011d3 369 config->counter_32_bit.compare_capture_channel[0];
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 372 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 hw->COUNT32.CC[1].reg =
sahilmgandhi 18:6a4db94011d3 376 config->counter_32_bit.compare_capture_channel[1];
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 379 }
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 Assert(false);
sahilmgandhi 18:6a4db94011d3 382 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * \brief Sets TC module count value.
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 * Sets the current timer count value of a initialized TC module. The
sahilmgandhi 18:6a4db94011d3 389 * specified TC module may be started or stopped.
sahilmgandhi 18:6a4db94011d3 390 *
sahilmgandhi 18:6a4db94011d3 391 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 392 * \param[in] count New timer count value to set
sahilmgandhi 18:6a4db94011d3 393 *
sahilmgandhi 18:6a4db94011d3 394 * \return Status of the count update procedure.
sahilmgandhi 18:6a4db94011d3 395 *
sahilmgandhi 18:6a4db94011d3 396 * \retval STATUS_OK The timer count was updated successfully
sahilmgandhi 18:6a4db94011d3 397 * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified
sahilmgandhi 18:6a4db94011d3 398 */
sahilmgandhi 18:6a4db94011d3 399 enum status_code tc_set_count_value(
sahilmgandhi 18:6a4db94011d3 400 const struct tc_module *const module_inst,
sahilmgandhi 18:6a4db94011d3 401 const uint32_t count)
sahilmgandhi 18:6a4db94011d3 402 {
sahilmgandhi 18:6a4db94011d3 403 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 404 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 405 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /* Get a pointer to the module's hardware instance*/
sahilmgandhi 18:6a4db94011d3 408 Tc *const tc_module = module_inst->hw;
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 411 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 412 }
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 /* Write to based on the TC counter_size */
sahilmgandhi 18:6a4db94011d3 415 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 416 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 417 tc_module->COUNT8.COUNT.reg = (uint8_t)count;
sahilmgandhi 18:6a4db94011d3 418 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 421 tc_module->COUNT16.COUNT.reg = (uint16_t)count;
sahilmgandhi 18:6a4db94011d3 422 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 425 tc_module->COUNT32.COUNT.reg = (uint32_t)count;
sahilmgandhi 18:6a4db94011d3 426 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 default:
sahilmgandhi 18:6a4db94011d3 429 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431 }
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 /**
sahilmgandhi 18:6a4db94011d3 434 * \brief Get TC module count value.
sahilmgandhi 18:6a4db94011d3 435 *
sahilmgandhi 18:6a4db94011d3 436 * Retrieves the current count value of a TC module. The specified TC module
sahilmgandhi 18:6a4db94011d3 437 * may be started or stopped.
sahilmgandhi 18:6a4db94011d3 438 *
sahilmgandhi 18:6a4db94011d3 439 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 440 *
sahilmgandhi 18:6a4db94011d3 441 * \return Count value of the specified TC module.
sahilmgandhi 18:6a4db94011d3 442 */
sahilmgandhi 18:6a4db94011d3 443 uint32_t tc_get_count_value(
sahilmgandhi 18:6a4db94011d3 444 const struct tc_module *const module_inst)
sahilmgandhi 18:6a4db94011d3 445 {
sahilmgandhi 18:6a4db94011d3 446 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 447 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 448 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 /* Get a pointer to the module's hardware instance */
sahilmgandhi 18:6a4db94011d3 451 Tc *const tc_module = module_inst->hw;
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 454 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 /* Read from based on the TC counter size */
sahilmgandhi 18:6a4db94011d3 458 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 459 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 460 return (uint32_t)tc_module->COUNT8.COUNT.reg;
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 463 return (uint32_t)tc_module->COUNT16.COUNT.reg;
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 466 return tc_module->COUNT32.COUNT.reg;
sahilmgandhi 18:6a4db94011d3 467 }
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 Assert(false);
sahilmgandhi 18:6a4db94011d3 470 return 0;
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 /**
sahilmgandhi 18:6a4db94011d3 474 * \brief Gets the TC module capture value.
sahilmgandhi 18:6a4db94011d3 475 *
sahilmgandhi 18:6a4db94011d3 476 * Retrieves the capture value in the indicated TC module capture channel.
sahilmgandhi 18:6a4db94011d3 477 *
sahilmgandhi 18:6a4db94011d3 478 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 479 * \param[in] channel_index Index of the Compare Capture channel to read
sahilmgandhi 18:6a4db94011d3 480 *
sahilmgandhi 18:6a4db94011d3 481 * \return Capture value stored in the specified timer channel.
sahilmgandhi 18:6a4db94011d3 482 */
sahilmgandhi 18:6a4db94011d3 483 uint32_t tc_get_capture_value(
sahilmgandhi 18:6a4db94011d3 484 const struct tc_module *const module_inst,
sahilmgandhi 18:6a4db94011d3 485 const enum tc_compare_capture_channel channel_index)
sahilmgandhi 18:6a4db94011d3 486 {
sahilmgandhi 18:6a4db94011d3 487 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 488 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 489 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /* Get a pointer to the module's hardware instance */
sahilmgandhi 18:6a4db94011d3 492 Tc *const tc_module = module_inst->hw;
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 495 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 496 }
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 /* Read out based on the TC counter size */
sahilmgandhi 18:6a4db94011d3 499 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 500 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 501 if (channel_index <
sahilmgandhi 18:6a4db94011d3 502 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 503 return tc_module->COUNT8.CC[channel_index].reg;
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 507 if (channel_index <
sahilmgandhi 18:6a4db94011d3 508 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 509 return tc_module->COUNT16.CC[channel_index].reg;
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 513 if (channel_index <
sahilmgandhi 18:6a4db94011d3 514 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 515 return tc_module->COUNT32.CC[channel_index].reg;
sahilmgandhi 18:6a4db94011d3 516 }
sahilmgandhi 18:6a4db94011d3 517 }
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 Assert(false);
sahilmgandhi 18:6a4db94011d3 520 return 0;
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 /**
sahilmgandhi 18:6a4db94011d3 524 * \brief Sets a TC module compare value.
sahilmgandhi 18:6a4db94011d3 525 *
sahilmgandhi 18:6a4db94011d3 526 * Writes a compare value to the given TC module compare/capture channel.
sahilmgandhi 18:6a4db94011d3 527 *
sahilmgandhi 18:6a4db94011d3 528 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 529 * \param[in] channel_index Index of the compare channel to write to
sahilmgandhi 18:6a4db94011d3 530 * \param[in] compare New compare value to set
sahilmgandhi 18:6a4db94011d3 531 *
sahilmgandhi 18:6a4db94011d3 532 * \return Status of the compare update procedure.
sahilmgandhi 18:6a4db94011d3 533 *
sahilmgandhi 18:6a4db94011d3 534 * \retval STATUS_OK The compare value was updated successfully
sahilmgandhi 18:6a4db94011d3 535 * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied
sahilmgandhi 18:6a4db94011d3 536 */
sahilmgandhi 18:6a4db94011d3 537 enum status_code tc_set_compare_value(
sahilmgandhi 18:6a4db94011d3 538 const struct tc_module *const module_inst,
sahilmgandhi 18:6a4db94011d3 539 const enum tc_compare_capture_channel channel_index,
sahilmgandhi 18:6a4db94011d3 540 const uint32_t compare)
sahilmgandhi 18:6a4db94011d3 541 {
sahilmgandhi 18:6a4db94011d3 542 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 543 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 544 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /* Get a pointer to the module's hardware instance */
sahilmgandhi 18:6a4db94011d3 547 Tc *const tc_module = module_inst->hw;
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 550 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /* Read out based on the TC counter size */
sahilmgandhi 18:6a4db94011d3 554 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 555 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 556 if (channel_index <
sahilmgandhi 18:6a4db94011d3 557 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 558 tc_module->COUNT8.CC[channel_index].reg =
sahilmgandhi 18:6a4db94011d3 559 (uint8_t)compare;
sahilmgandhi 18:6a4db94011d3 560 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 561 }
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 564 if (channel_index <
sahilmgandhi 18:6a4db94011d3 565 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 566 tc_module->COUNT16.CC[channel_index].reg =
sahilmgandhi 18:6a4db94011d3 567 (uint16_t)compare;
sahilmgandhi 18:6a4db94011d3 568 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 569 }
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 572 if (channel_index <
sahilmgandhi 18:6a4db94011d3 573 NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 574 tc_module->COUNT32.CC[channel_index].reg =
sahilmgandhi 18:6a4db94011d3 575 (uint32_t)compare;
sahilmgandhi 18:6a4db94011d3 576 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 581 }
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /**
sahilmgandhi 18:6a4db94011d3 584 * \brief Resets the TC module.
sahilmgandhi 18:6a4db94011d3 585 *
sahilmgandhi 18:6a4db94011d3 586 * Resets the TC module, restoring all hardware module registers to their
sahilmgandhi 18:6a4db94011d3 587 * default values and disabling the module. The TC module will not be
sahilmgandhi 18:6a4db94011d3 588 * accessible while the reset is being performed.
sahilmgandhi 18:6a4db94011d3 589 *
sahilmgandhi 18:6a4db94011d3 590 * \note When resetting a 32-bit counter only the master TC module's instance
sahilmgandhi 18:6a4db94011d3 591 * structure should be passed to the function.
sahilmgandhi 18:6a4db94011d3 592 *
sahilmgandhi 18:6a4db94011d3 593 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 594 *
sahilmgandhi 18:6a4db94011d3 595 * \return Status of the procedure.
sahilmgandhi 18:6a4db94011d3 596 * \retval STATUS_OK The module was reset successfully
sahilmgandhi 18:6a4db94011d3 597 * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to
sahilmgandhi 18:6a4db94011d3 598 * the function. Only use reset on master
sahilmgandhi 18:6a4db94011d3 599 * TC
sahilmgandhi 18:6a4db94011d3 600 */
sahilmgandhi 18:6a4db94011d3 601 enum status_code tc_reset(
sahilmgandhi 18:6a4db94011d3 602 const struct tc_module *const module_inst)
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 605 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 606 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Get a pointer to the module hardware instance */
sahilmgandhi 18:6a4db94011d3 609 TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
sahilmgandhi 18:6a4db94011d3 612 return STATUS_ERR_UNSUPPORTED_DEV;
sahilmgandhi 18:6a4db94011d3 613 }
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 /* Disable this module if it is running */
sahilmgandhi 18:6a4db94011d3 616 if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
sahilmgandhi 18:6a4db94011d3 617 tc_disable(module_inst);
sahilmgandhi 18:6a4db94011d3 618 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 619 /* wait while module is disabling */
sahilmgandhi 18:6a4db94011d3 620 }
sahilmgandhi 18:6a4db94011d3 621 }
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 /* Reset this TC module */
sahilmgandhi 18:6a4db94011d3 624 tc_module->CTRLA.reg |= TC_CTRLA_SWRST;
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /**
sahilmgandhi 18:6a4db94011d3 630 * \brief Set the timer TOP/period value.
sahilmgandhi 18:6a4db94011d3 631 *
sahilmgandhi 18:6a4db94011d3 632 * For 8-bit counter size this function writes the top value to the period
sahilmgandhi 18:6a4db94011d3 633 * register.
sahilmgandhi 18:6a4db94011d3 634 *
sahilmgandhi 18:6a4db94011d3 635 * For 16- and 32-bit counter size this function writes the top value to
sahilmgandhi 18:6a4db94011d3 636 * Capture Compare register 0. The value in this register can not be used for
sahilmgandhi 18:6a4db94011d3 637 * any other purpose.
sahilmgandhi 18:6a4db94011d3 638 *
sahilmgandhi 18:6a4db94011d3 639 * \note This function is designed to be used in PWM or frequency
sahilmgandhi 18:6a4db94011d3 640 * match modes only. When the counter is set to 16- or 32-bit counter
sahilmgandhi 18:6a4db94011d3 641 * size. In 8-bit counter size it will always be possible to change the
sahilmgandhi 18:6a4db94011d3 642 * top value even in normal mode.
sahilmgandhi 18:6a4db94011d3 643 *
sahilmgandhi 18:6a4db94011d3 644 * \param[in] module_inst Pointer to the software module instance struct
sahilmgandhi 18:6a4db94011d3 645 * \param[in] top_value New timer TOP value to set
sahilmgandhi 18:6a4db94011d3 646 *
sahilmgandhi 18:6a4db94011d3 647 * \return Status of the TOP set procedure.
sahilmgandhi 18:6a4db94011d3 648 *
sahilmgandhi 18:6a4db94011d3 649 * \retval STATUS_OK The timer TOP value was updated successfully
sahilmgandhi 18:6a4db94011d3 650 * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the
sahilmgandhi 18:6a4db94011d3 651 * module instance is invalid
sahilmgandhi 18:6a4db94011d3 652 */
sahilmgandhi 18:6a4db94011d3 653 enum status_code tc_set_top_value (
sahilmgandhi 18:6a4db94011d3 654 const struct tc_module *const module_inst,
sahilmgandhi 18:6a4db94011d3 655 const uint32_t top_value)
sahilmgandhi 18:6a4db94011d3 656 {
sahilmgandhi 18:6a4db94011d3 657 Assert(module_inst);
sahilmgandhi 18:6a4db94011d3 658 Assert(module_inst->hw);
sahilmgandhi 18:6a4db94011d3 659 Assert(top_value);
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 Tc *const tc_module = module_inst->hw;
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 while (tc_is_syncing(module_inst)) {
sahilmgandhi 18:6a4db94011d3 664 /* Wait for sync */
sahilmgandhi 18:6a4db94011d3 665 }
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 switch (module_inst->counter_size) {
sahilmgandhi 18:6a4db94011d3 668 case TC_COUNTER_SIZE_8BIT:
sahilmgandhi 18:6a4db94011d3 669 tc_module->COUNT8.PER.reg = (uint8_t)top_value;
sahilmgandhi 18:6a4db94011d3 670 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 case TC_COUNTER_SIZE_16BIT:
sahilmgandhi 18:6a4db94011d3 673 tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
sahilmgandhi 18:6a4db94011d3 674 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 case TC_COUNTER_SIZE_32BIT:
sahilmgandhi 18:6a4db94011d3 677 tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
sahilmgandhi 18:6a4db94011d3 678 return STATUS_OK;
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 default:
sahilmgandhi 18:6a4db94011d3 681 Assert(false);
sahilmgandhi 18:6a4db94011d3 682 return STATUS_ERR_INVALID_ARG;
sahilmgandhi 18:6a4db94011d3 683 }
sahilmgandhi 18:6a4db94011d3 684 }