MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief SAM Generic Clock Driver
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46 #ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 47 #define SYSTEM_CLOCK_GCLK_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /**
sahilmgandhi 18:6a4db94011d3 50 * \addtogroup asfdoc_sam0_system_clock_group
sahilmgandhi 18:6a4db94011d3 51 *
sahilmgandhi 18:6a4db94011d3 52 * @{
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #include <compiler.h>
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 58 extern "C" {
sahilmgandhi 18:6a4db94011d3 59 #endif
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /**
sahilmgandhi 18:6a4db94011d3 62 * \brief List of available GCLK generators.
sahilmgandhi 18:6a4db94011d3 63 *
sahilmgandhi 18:6a4db94011d3 64 * List of Available GCLK generators. This enum is used in the peripheral
sahilmgandhi 18:6a4db94011d3 65 * device drivers to select the GCLK generator to be used for its operation.
sahilmgandhi 18:6a4db94011d3 66 *
sahilmgandhi 18:6a4db94011d3 67 * The number of GCLK generators available is device dependent.
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 enum gclk_generator {
sahilmgandhi 18:6a4db94011d3 70 /** GCLK generator channel 0 */
sahilmgandhi 18:6a4db94011d3 71 GCLK_GENERATOR_0,
sahilmgandhi 18:6a4db94011d3 72 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
sahilmgandhi 18:6a4db94011d3 73 /** GCLK generator channel 1 */
sahilmgandhi 18:6a4db94011d3 74 GCLK_GENERATOR_1,
sahilmgandhi 18:6a4db94011d3 75 #endif
sahilmgandhi 18:6a4db94011d3 76 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
sahilmgandhi 18:6a4db94011d3 77 /** GCLK generator channel 2 */
sahilmgandhi 18:6a4db94011d3 78 GCLK_GENERATOR_2,
sahilmgandhi 18:6a4db94011d3 79 #endif
sahilmgandhi 18:6a4db94011d3 80 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
sahilmgandhi 18:6a4db94011d3 81 /** GCLK generator channel 3 */
sahilmgandhi 18:6a4db94011d3 82 GCLK_GENERATOR_3,
sahilmgandhi 18:6a4db94011d3 83 #endif
sahilmgandhi 18:6a4db94011d3 84 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
sahilmgandhi 18:6a4db94011d3 85 /** GCLK generator channel 4 */
sahilmgandhi 18:6a4db94011d3 86 GCLK_GENERATOR_4,
sahilmgandhi 18:6a4db94011d3 87 #endif
sahilmgandhi 18:6a4db94011d3 88 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
sahilmgandhi 18:6a4db94011d3 89 /** GCLK generator channel 5 */
sahilmgandhi 18:6a4db94011d3 90 GCLK_GENERATOR_5,
sahilmgandhi 18:6a4db94011d3 91 #endif
sahilmgandhi 18:6a4db94011d3 92 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
sahilmgandhi 18:6a4db94011d3 93 /** GCLK generator channel 6 */
sahilmgandhi 18:6a4db94011d3 94 GCLK_GENERATOR_6,
sahilmgandhi 18:6a4db94011d3 95 #endif
sahilmgandhi 18:6a4db94011d3 96 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
sahilmgandhi 18:6a4db94011d3 97 /** GCLK generator channel 7 */
sahilmgandhi 18:6a4db94011d3 98 GCLK_GENERATOR_7,
sahilmgandhi 18:6a4db94011d3 99 #endif
sahilmgandhi 18:6a4db94011d3 100 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
sahilmgandhi 18:6a4db94011d3 101 /** GCLK generator channel 8 */
sahilmgandhi 18:6a4db94011d3 102 GCLK_GENERATOR_8,
sahilmgandhi 18:6a4db94011d3 103 #endif
sahilmgandhi 18:6a4db94011d3 104 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
sahilmgandhi 18:6a4db94011d3 105 /** GCLK generator channel 9 */
sahilmgandhi 18:6a4db94011d3 106 GCLK_GENERATOR_9,
sahilmgandhi 18:6a4db94011d3 107 #endif
sahilmgandhi 18:6a4db94011d3 108 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
sahilmgandhi 18:6a4db94011d3 109 /** GCLK generator channel 10 */
sahilmgandhi 18:6a4db94011d3 110 GCLK_GENERATOR_10,
sahilmgandhi 18:6a4db94011d3 111 #endif
sahilmgandhi 18:6a4db94011d3 112 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
sahilmgandhi 18:6a4db94011d3 113 /** GCLK generator channel 11 */
sahilmgandhi 18:6a4db94011d3 114 GCLK_GENERATOR_11,
sahilmgandhi 18:6a4db94011d3 115 #endif
sahilmgandhi 18:6a4db94011d3 116 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
sahilmgandhi 18:6a4db94011d3 117 /** GCLK generator channel 12 */
sahilmgandhi 18:6a4db94011d3 118 GCLK_GENERATOR_12,
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
sahilmgandhi 18:6a4db94011d3 121 /** GCLK generator channel 13 */
sahilmgandhi 18:6a4db94011d3 122 GCLK_GENERATOR_13,
sahilmgandhi 18:6a4db94011d3 123 #endif
sahilmgandhi 18:6a4db94011d3 124 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
sahilmgandhi 18:6a4db94011d3 125 /** GCLK generator channel 14 */
sahilmgandhi 18:6a4db94011d3 126 GCLK_GENERATOR_14,
sahilmgandhi 18:6a4db94011d3 127 #endif
sahilmgandhi 18:6a4db94011d3 128 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
sahilmgandhi 18:6a4db94011d3 129 /** GCLK generator channel 15 */
sahilmgandhi 18:6a4db94011d3 130 GCLK_GENERATOR_15,
sahilmgandhi 18:6a4db94011d3 131 #endif
sahilmgandhi 18:6a4db94011d3 132 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
sahilmgandhi 18:6a4db94011d3 133 /** GCLK generator channel 16 */
sahilmgandhi 18:6a4db94011d3 134 GCLK_GENERATOR_16,
sahilmgandhi 18:6a4db94011d3 135 #endif
sahilmgandhi 18:6a4db94011d3 136 };
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /**
sahilmgandhi 18:6a4db94011d3 139 * \brief Generic Clock Generator configuration structure.
sahilmgandhi 18:6a4db94011d3 140 *
sahilmgandhi 18:6a4db94011d3 141 * Configuration structure for a Generic Clock Generator channel. This
sahilmgandhi 18:6a4db94011d3 142 * structure should be initialized by the
sahilmgandhi 18:6a4db94011d3 143 * \ref system_gclk_gen_get_config_defaults() function before being modified by
sahilmgandhi 18:6a4db94011d3 144 * the user application.
sahilmgandhi 18:6a4db94011d3 145 */
sahilmgandhi 18:6a4db94011d3 146 struct system_gclk_gen_config {
sahilmgandhi 18:6a4db94011d3 147 /** Source clock input channel index, see the \ref system_clock_source */
sahilmgandhi 18:6a4db94011d3 148 uint8_t source_clock;
sahilmgandhi 18:6a4db94011d3 149 /** If \c true, the generator output level is high when disabled */
sahilmgandhi 18:6a4db94011d3 150 bool high_when_disabled;
sahilmgandhi 18:6a4db94011d3 151 /** Integer division factor of the clock output compared to the input */
sahilmgandhi 18:6a4db94011d3 152 uint32_t division_factor;
sahilmgandhi 18:6a4db94011d3 153 /** If \c true, the clock is kept enabled during device standby mode */
sahilmgandhi 18:6a4db94011d3 154 bool run_in_standby;
sahilmgandhi 18:6a4db94011d3 155 /** If \c true, enables GCLK generator clock output to a GPIO pin */
sahilmgandhi 18:6a4db94011d3 156 bool output_enable;
sahilmgandhi 18:6a4db94011d3 157 };
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /**
sahilmgandhi 18:6a4db94011d3 160 * \brief Generic Clock configuration structure.
sahilmgandhi 18:6a4db94011d3 161 *
sahilmgandhi 18:6a4db94011d3 162 * Configuration structure for a Generic Clock channel. This structure
sahilmgandhi 18:6a4db94011d3 163 * should be initialized by the \ref system_gclk_chan_get_config_defaults()
sahilmgandhi 18:6a4db94011d3 164 * function before being modified by the user application.
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166 struct system_gclk_chan_config {
sahilmgandhi 18:6a4db94011d3 167 /** Generic Clock Generator source channel */
sahilmgandhi 18:6a4db94011d3 168 enum gclk_generator source_generator;
sahilmgandhi 18:6a4db94011d3 169 };
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** \name Generic Clock Management
sahilmgandhi 18:6a4db94011d3 172 * @{
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174 void system_gclk_init(void);
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /** @} */
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /**
sahilmgandhi 18:6a4db94011d3 180 * \name Generic Clock Management (Generators)
sahilmgandhi 18:6a4db94011d3 181 * @{
sahilmgandhi 18:6a4db94011d3 182 */
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 /**
sahilmgandhi 18:6a4db94011d3 185 * \brief Initializes a Generic Clock Generator configuration structure to defaults.
sahilmgandhi 18:6a4db94011d3 186 *
sahilmgandhi 18:6a4db94011d3 187 * Initializes a given Generic Clock Generator configuration structure to
sahilmgandhi 18:6a4db94011d3 188 * a set of known default values. This function should be called on all
sahilmgandhi 18:6a4db94011d3 189 * new instances of these configuration structures before being modified
sahilmgandhi 18:6a4db94011d3 190 * by the user application.
sahilmgandhi 18:6a4db94011d3 191 *
sahilmgandhi 18:6a4db94011d3 192 * The default configuration is:
sahilmgandhi 18:6a4db94011d3 193 * \li Clock is generated undivided from the source frequency
sahilmgandhi 18:6a4db94011d3 194 * \li Clock generator output is low when the generator is disabled
sahilmgandhi 18:6a4db94011d3 195 * \li The input clock is sourced from input clock channel 0
sahilmgandhi 18:6a4db94011d3 196 * \li Clock will be disabled during sleep
sahilmgandhi 18:6a4db94011d3 197 * \li The clock output will not be routed to a physical GPIO pin
sahilmgandhi 18:6a4db94011d3 198 *
sahilmgandhi 18:6a4db94011d3 199 * \param[out] config Configuration structure to initialize to default values
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201 static inline void system_gclk_gen_get_config_defaults(
sahilmgandhi 18:6a4db94011d3 202 struct system_gclk_gen_config *const config)
sahilmgandhi 18:6a4db94011d3 203 {
sahilmgandhi 18:6a4db94011d3 204 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 205 Assert(config);
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /* Default configuration values */
sahilmgandhi 18:6a4db94011d3 208 config->division_factor = 1;
sahilmgandhi 18:6a4db94011d3 209 config->high_when_disabled = false;
sahilmgandhi 18:6a4db94011d3 210 #if SAML21
sahilmgandhi 18:6a4db94011d3 211 config->source_clock = GCLK_SOURCE_OSC16M;
sahilmgandhi 18:6a4db94011d3 212 #elif (SAMC20) || (SAMC21)
sahilmgandhi 18:6a4db94011d3 213 config->source_clock = GCLK_SOURCE_OSC48M;
sahilmgandhi 18:6a4db94011d3 214 #else
sahilmgandhi 18:6a4db94011d3 215 config->source_clock = GCLK_SOURCE_OSC8M;
sahilmgandhi 18:6a4db94011d3 216 #endif
sahilmgandhi 18:6a4db94011d3 217 config->run_in_standby = false;
sahilmgandhi 18:6a4db94011d3 218 config->output_enable = false;
sahilmgandhi 18:6a4db94011d3 219 }
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 void system_gclk_gen_set_config(
sahilmgandhi 18:6a4db94011d3 222 const uint8_t generator,
sahilmgandhi 18:6a4db94011d3 223 struct system_gclk_gen_config *const config);
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 void system_gclk_gen_enable(
sahilmgandhi 18:6a4db94011d3 226 const uint8_t generator);
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 void system_gclk_gen_disable(
sahilmgandhi 18:6a4db94011d3 229 const uint8_t generator);
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 bool system_gclk_gen_is_enabled(
sahilmgandhi 18:6a4db94011d3 232 const uint8_t generator);
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /** @} */
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /**
sahilmgandhi 18:6a4db94011d3 238 * \name Generic Clock Management (Channels)
sahilmgandhi 18:6a4db94011d3 239 * @{
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /**
sahilmgandhi 18:6a4db94011d3 243 * \brief Initializes a Generic Clock configuration structure to defaults.
sahilmgandhi 18:6a4db94011d3 244 *
sahilmgandhi 18:6a4db94011d3 245 * Initializes a given Generic Clock configuration structure to a set of
sahilmgandhi 18:6a4db94011d3 246 * known default values. This function should be called on all new
sahilmgandhi 18:6a4db94011d3 247 * instances of these configuration structures before being modified by the
sahilmgandhi 18:6a4db94011d3 248 * user application.
sahilmgandhi 18:6a4db94011d3 249 *
sahilmgandhi 18:6a4db94011d3 250 * The default configuration is as follows:
sahilmgandhi 18:6a4db94011d3 251 * \li Clock is sourced from the Generic Clock Generator channel 0
sahilmgandhi 18:6a4db94011d3 252 * \li Clock configuration will not be write-locked when set
sahilmgandhi 18:6a4db94011d3 253 *
sahilmgandhi 18:6a4db94011d3 254 * \param[out] config Configuration structure to initialize to default values
sahilmgandhi 18:6a4db94011d3 255 */
sahilmgandhi 18:6a4db94011d3 256 static inline void system_gclk_chan_get_config_defaults(
sahilmgandhi 18:6a4db94011d3 257 struct system_gclk_chan_config *const config)
sahilmgandhi 18:6a4db94011d3 258 {
sahilmgandhi 18:6a4db94011d3 259 /* Sanity check arguments */
sahilmgandhi 18:6a4db94011d3 260 Assert(config);
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Default configuration values */
sahilmgandhi 18:6a4db94011d3 263 config->source_generator = GCLK_GENERATOR_0;
sahilmgandhi 18:6a4db94011d3 264 }
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 void system_gclk_chan_set_config(
sahilmgandhi 18:6a4db94011d3 267 const uint8_t channel,
sahilmgandhi 18:6a4db94011d3 268 struct system_gclk_chan_config *const config);
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 void system_gclk_chan_enable(
sahilmgandhi 18:6a4db94011d3 271 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 void system_gclk_chan_disable(
sahilmgandhi 18:6a4db94011d3 274 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 bool system_gclk_chan_is_enabled(
sahilmgandhi 18:6a4db94011d3 277 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 void system_gclk_chan_lock(
sahilmgandhi 18:6a4db94011d3 280 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 bool system_gclk_chan_is_locked(
sahilmgandhi 18:6a4db94011d3 283 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /** @} */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 /**
sahilmgandhi 18:6a4db94011d3 289 * \name Generic Clock Frequency Retrieval
sahilmgandhi 18:6a4db94011d3 290 * @{
sahilmgandhi 18:6a4db94011d3 291 */
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 uint32_t system_gclk_gen_get_hz(
sahilmgandhi 18:6a4db94011d3 294 const uint8_t generator);
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 uint32_t system_gclk_chan_get_hz(
sahilmgandhi 18:6a4db94011d3 297 const uint8_t channel);
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /** @} */
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 302 }
sahilmgandhi 18:6a4db94011d3 303 #endif
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /** @} */
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 #endif