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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:: sahilmgandhi
Date:: Sun May 14 23:18:57 2017 +0000
Revision:: 18:6a4db94011d3

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sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	* \file
sahilmgandhi	18:6a4db94011d3	3	*
sahilmgandhi	18:6a4db94011d3	4	* \brief SAM Clock Driver
sahilmgandhi	18:6a4db94011d3	5	*
sahilmgandhi	18:6a4db94011d3	6	* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
sahilmgandhi	18:6a4db94011d3	7	*
sahilmgandhi	18:6a4db94011d3	8	* \asf_license_start
sahilmgandhi	18:6a4db94011d3	9	*
sahilmgandhi	18:6a4db94011d3	10	* \page License
sahilmgandhi	18:6a4db94011d3	11	*
sahilmgandhi	18:6a4db94011d3	12	* Redistribution and use in source and binary forms, with or without
sahilmgandhi	18:6a4db94011d3	13	* modification, are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	16	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	17	*
sahilmgandhi	18:6a4db94011d3	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	19	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	20	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	21	*
sahilmgandhi	18:6a4db94011d3	22	* 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi	18:6a4db94011d3	23	* from this software without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	24	*
sahilmgandhi	18:6a4db94011d3	25	* 4. This software may only be redistributed and used in connection with an
sahilmgandhi	18:6a4db94011d3	26	* Atmel microcontroller product.
sahilmgandhi	18:6a4db94011d3	27	*
sahilmgandhi	18:6a4db94011d3	28	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi	18:6a4db94011d3	29	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi	18:6a4db94011d3	30	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi	18:6a4db94011d3	31	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi	18:6a4db94011d3	32	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi	18:6a4db94011d3	34	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi	18:6a4db94011d3	35	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi	18:6a4db94011d3	36	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi	18:6a4db94011d3	37	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi	18:6a4db94011d3	38	* POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	39	*
sahilmgandhi	18:6a4db94011d3	40	* \asf_license_stop
sahilmgandhi	18:6a4db94011d3	41	*
sahilmgandhi	18:6a4db94011d3	42	*/
sahilmgandhi	18:6a4db94011d3	43	/*
sahilmgandhi	18:6a4db94011d3	44	* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi	18:6a4db94011d3	45	*/
sahilmgandhi	18:6a4db94011d3	46	#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
sahilmgandhi	18:6a4db94011d3	47	#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	50	extern "C" {
sahilmgandhi	18:6a4db94011d3	51	#endif
sahilmgandhi	18:6a4db94011d3	52
sahilmgandhi	18:6a4db94011d3	53	/**
sahilmgandhi	18:6a4db94011d3	54	* \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
sahilmgandhi	18:6a4db94011d3	55	*
sahilmgandhi	18:6a4db94011d3	56	* This driver for Atmel® \| SMART ARM®-based microcontrollers provides an interface for the configuration
sahilmgandhi	18:6a4db94011d3	57	* and management of the device's clocking related functions. This includes
sahilmgandhi	18:6a4db94011d3	58	* the various clock sources, bus clocks, and generic clocks within the device,
sahilmgandhi	18:6a4db94011d3	59	* with functions to manage the enabling, disabling, source selection, and
sahilmgandhi	18:6a4db94011d3	60	* prescaling of clocks to various internal peripherals.
sahilmgandhi	18:6a4db94011d3	61	*
sahilmgandhi	18:6a4db94011d3	62	* The following peripherals are used by this module:
sahilmgandhi	18:6a4db94011d3	63	*
sahilmgandhi	18:6a4db94011d3	64	* - GCLK (Generic Clock Management)
sahilmgandhi	18:6a4db94011d3	65	* - PM (Power Management)
sahilmgandhi	18:6a4db94011d3	66	* - SYSCTRL (Clock Source Control)
sahilmgandhi	18:6a4db94011d3	67	*
sahilmgandhi	18:6a4db94011d3	68	* The following devices can use this module:
sahilmgandhi	18:6a4db94011d3	69	* - Atmel \| SMART SAM D20/D21
sahilmgandhi	18:6a4db94011d3	70	* - Atmel \| SMART SAM R21
sahilmgandhi	18:6a4db94011d3	71	* - Atmel \| SMART SAM D10/D11
sahilmgandhi	18:6a4db94011d3	72	* - Atmel \| SMART SAM DA0/DA1
sahilmgandhi	18:6a4db94011d3	73	*
sahilmgandhi	18:6a4db94011d3	74	* The outline of this documentation is as follows:
sahilmgandhi	18:6a4db94011d3	75	* - \ref asfdoc_sam0_system_clock_prerequisites
sahilmgandhi	18:6a4db94011d3	76	* - \ref asfdoc_sam0_system_clock_module_overview
sahilmgandhi	18:6a4db94011d3	77	* - \ref asfdoc_sam0_system_clock_special_considerations
sahilmgandhi	18:6a4db94011d3	78	* - \ref asfdoc_sam0_system_clock_extra_info
sahilmgandhi	18:6a4db94011d3	79	* - \ref asfdoc_sam0_system_clock_examples
sahilmgandhi	18:6a4db94011d3	80	* - \ref asfdoc_sam0_system_clock_api_overview
sahilmgandhi	18:6a4db94011d3	81	*
sahilmgandhi	18:6a4db94011d3	82	*
sahilmgandhi	18:6a4db94011d3	83	* \section asfdoc_sam0_system_clock_prerequisites Prerequisites
sahilmgandhi	18:6a4db94011d3	84	*
sahilmgandhi	18:6a4db94011d3	85	* There are no prerequisites for this module.
sahilmgandhi	18:6a4db94011d3	86	*
sahilmgandhi	18:6a4db94011d3	87	*
sahilmgandhi	18:6a4db94011d3	88	* \section asfdoc_sam0_system_clock_module_overview Module Overview
sahilmgandhi	18:6a4db94011d3	89	* The SAM devices contain a sophisticated clocking system, which is designed
sahilmgandhi	18:6a4db94011d3	90	* to give the maximum flexibility to the user application. This system allows
sahilmgandhi	18:6a4db94011d3	91	* a system designer to tune the performance and power consumption of the device
sahilmgandhi	18:6a4db94011d3	92	* in a dynamic manner, to achieve the best trade-off between the two for a
sahilmgandhi	18:6a4db94011d3	93	* particular application.
sahilmgandhi	18:6a4db94011d3	94	*
sahilmgandhi	18:6a4db94011d3	95	* This driver provides a set of functions for the configuration and management
sahilmgandhi	18:6a4db94011d3	96	* of the various clock related functionality within the device.
sahilmgandhi	18:6a4db94011d3	97	*
sahilmgandhi	18:6a4db94011d3	98	* \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
sahilmgandhi	18:6a4db94011d3	99	* <table>
sahilmgandhi	18:6a4db94011d3	100	* <tr>
sahilmgandhi	18:6a4db94011d3	101	* <th>Driver Feature Macro</th>
sahilmgandhi	18:6a4db94011d3	102	* <th>Supported devices</th>
sahilmgandhi	18:6a4db94011d3	103	* </tr>
sahilmgandhi	18:6a4db94011d3	104	* <tr>
sahilmgandhi	18:6a4db94011d3	105	* <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
sahilmgandhi	18:6a4db94011d3	106	* <td>SAMD21, SAMR21, SAMD10, SAMD11, SAMDAx</td>
sahilmgandhi	18:6a4db94011d3	107	* </tr>
sahilmgandhi	18:6a4db94011d3	108	* </table>
sahilmgandhi	18:6a4db94011d3	109	* \note The specific features are only available in the driver when the
sahilmgandhi	18:6a4db94011d3	110	* selected device supports those features.
sahilmgandhi	18:6a4db94011d3	111	*
sahilmgandhi	18:6a4db94011d3	112	* \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
sahilmgandhi	18:6a4db94011d3	113	* The SAM devices have a number of master clock source modules, each of
sahilmgandhi	18:6a4db94011d3	114	* which being capable of producing a stabilized output frequency, which can then
sahilmgandhi	18:6a4db94011d3	115	* be fed into the various peripherals and modules within the device.
sahilmgandhi	18:6a4db94011d3	116	*
sahilmgandhi	18:6a4db94011d3	117	* Possible clock source modules include internal R/C oscillators, internal
sahilmgandhi	18:6a4db94011d3	118	* DFLL modules, as well as external crystal oscillators and/or clock inputs.
sahilmgandhi	18:6a4db94011d3	119	*
sahilmgandhi	18:6a4db94011d3	120	* \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
sahilmgandhi	18:6a4db94011d3	121	* The CPU and AHB/APBx buses are clocked by the same physical clock source
sahilmgandhi	18:6a4db94011d3	122	* (referred in this module as the Main Clock), however the APBx buses may
sahilmgandhi	18:6a4db94011d3	123	* have additional prescaler division ratios set to give each peripheral bus a
sahilmgandhi	18:6a4db94011d3	124	* different clock speed.
sahilmgandhi	18:6a4db94011d3	125	*
sahilmgandhi	18:6a4db94011d3	126	* The general main clock tree for the CPU and associated buses is shown in
sahilmgandhi	18:6a4db94011d3	127	* \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
sahilmgandhi	18:6a4db94011d3	128	*
sahilmgandhi	18:6a4db94011d3	129	* \anchor asfdoc_sam0_system_clock_module_clock_tree
sahilmgandhi	18:6a4db94011d3	130	* \dot
sahilmgandhi	18:6a4db94011d3	131	* digraph overview {
sahilmgandhi	18:6a4db94011d3	132	* rankdir=LR;
sahilmgandhi	18:6a4db94011d3	133	* clk_src [label="Clock Sources", shape=none, height=0];
sahilmgandhi	18:6a4db94011d3	134	* node [label="CPU Bus" shape=ellipse] cpu_bus;
sahilmgandhi	18:6a4db94011d3	135	* node [label="AHB Bus" shape=ellipse] ahb_bus;
sahilmgandhi	18:6a4db94011d3	136	* node [label="APBA Bus" shape=ellipse] apb_a_bus;
sahilmgandhi	18:6a4db94011d3	137	* node [label="APBB Bus" shape=ellipse] apb_b_bus;
sahilmgandhi	18:6a4db94011d3	138	* node [label="APBC Bus" shape=ellipse] apb_c_bus;
sahilmgandhi	18:6a4db94011d3	139	* node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
sahilmgandhi	18:6a4db94011d3	140	* node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
sahilmgandhi	18:6a4db94011d3	141	* node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
sahilmgandhi	18:6a4db94011d3	142	* node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
sahilmgandhi	18:6a4db94011d3	143	* node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
sahilmgandhi	18:6a4db94011d3	144	*
sahilmgandhi	18:6a4db94011d3	145	* clk_src -> main_clock_mux;
sahilmgandhi	18:6a4db94011d3	146	* main_clock_mux -> main_prescaler;
sahilmgandhi	18:6a4db94011d3	147	* main_prescaler -> cpu_bus;
sahilmgandhi	18:6a4db94011d3	148	* main_prescaler -> ahb_bus;
sahilmgandhi	18:6a4db94011d3	149	* main_prescaler -> apb_a_prescaler;
sahilmgandhi	18:6a4db94011d3	150	* main_prescaler -> apb_b_prescaler;
sahilmgandhi	18:6a4db94011d3	151	* main_prescaler -> apb_c_prescaler;
sahilmgandhi	18:6a4db94011d3	152	* apb_a_prescaler -> apb_a_bus;
sahilmgandhi	18:6a4db94011d3	153	* apb_b_prescaler -> apb_b_bus;
sahilmgandhi	18:6a4db94011d3	154	* apb_c_prescaler -> apb_c_bus;
sahilmgandhi	18:6a4db94011d3	155	* }
sahilmgandhi	18:6a4db94011d3	156	* \enddot
sahilmgandhi	18:6a4db94011d3	157	*
sahilmgandhi	18:6a4db94011d3	158	* \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
sahilmgandhi	18:6a4db94011d3	159	* To save power, the input clock to one or more peripherals on the AHB and APBx
sahilmgandhi	18:6a4db94011d3	160	* buses can be masked away - when masked, no clock is passed into the module.
sahilmgandhi	18:6a4db94011d3	161	* Disabling of clocks of unused modules will prevent all access to the masked
sahilmgandhi	18:6a4db94011d3	162	* module, but will reduce the overall device power consumption.
sahilmgandhi	18:6a4db94011d3	163	*
sahilmgandhi	18:6a4db94011d3	164	* \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
sahilmgandhi	18:6a4db94011d3	165	* Within the SAM devices there are a number of Generic Clocks; these are used to
sahilmgandhi	18:6a4db94011d3	166	* provide clocks to the various peripheral clock domains in the device in a
sahilmgandhi	18:6a4db94011d3	167	* standardized manner. One or more master source clocks can be selected as the
sahilmgandhi	18:6a4db94011d3	168	* input clock to a Generic Clock Generator, which can prescale down the input
sahilmgandhi	18:6a4db94011d3	169	* frequency to a slower rate for use in a peripheral.
sahilmgandhi	18:6a4db94011d3	170	*
sahilmgandhi	18:6a4db94011d3	171	* Additionally, a number of individually selectable Generic Clock Channels are
sahilmgandhi	18:6a4db94011d3	172	* provided, which multiplex and gate the various generator outputs for one or
sahilmgandhi	18:6a4db94011d3	173	* more peripherals within the device. This setup allows for a single common
sahilmgandhi	18:6a4db94011d3	174	* generator to feed one or more channels, which can then be enabled or disabled
sahilmgandhi	18:6a4db94011d3	175	* individually as required.
sahilmgandhi	18:6a4db94011d3	176	*
sahilmgandhi	18:6a4db94011d3	177	* \anchor asfdoc_sam0_system_clock_module_chain_overview
sahilmgandhi	18:6a4db94011d3	178	* \dot
sahilmgandhi	18:6a4db94011d3	179	* digraph overview {
sahilmgandhi	18:6a4db94011d3	180	* rankdir=LR;
sahilmgandhi	18:6a4db94011d3	181	* node [label="Clock\nSource a" shape=square] system_clock_source;
sahilmgandhi	18:6a4db94011d3	182	* node [label="Generator 1" shape=square] clock_gen;
sahilmgandhi	18:6a4db94011d3	183	* node [label="Channel x" shape=square] clock_chan0;
sahilmgandhi	18:6a4db94011d3	184	* node [label="Channel y" shape=square] clock_chan1;
sahilmgandhi	18:6a4db94011d3	185	* node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
sahilmgandhi	18:6a4db94011d3	186	* node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
sahilmgandhi	18:6a4db94011d3	187	*
sahilmgandhi	18:6a4db94011d3	188	* system_clock_source -> clock_gen;
sahilmgandhi	18:6a4db94011d3	189	* clock_gen -> clock_chan0;
sahilmgandhi	18:6a4db94011d3	190	* clock_chan0 -> peripheral0;
sahilmgandhi	18:6a4db94011d3	191	* clock_gen -> clock_chan1;
sahilmgandhi	18:6a4db94011d3	192	* clock_chan1 -> peripheral1;
sahilmgandhi	18:6a4db94011d3	193	* }
sahilmgandhi	18:6a4db94011d3	194	* \enddot
sahilmgandhi	18:6a4db94011d3	195	*
sahilmgandhi	18:6a4db94011d3	196	* \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
sahilmgandhi	18:6a4db94011d3	197	* An example setup of a complete clock chain within the device is shown in
sahilmgandhi	18:6a4db94011d3	198	* \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
sahilmgandhi	18:6a4db94011d3	199	*
sahilmgandhi	18:6a4db94011d3	200	* \anchor asfdoc_sam0_system_clock_module_chain_example_fig
sahilmgandhi	18:6a4db94011d3	201	* \dot
sahilmgandhi	18:6a4db94011d3	202	* digraph overview {
sahilmgandhi	18:6a4db94011d3	203	* rankdir=LR;
sahilmgandhi	18:6a4db94011d3	204	* node [label="External\nOscillator" shape=square] system_clock_source0;
sahilmgandhi	18:6a4db94011d3	205	* node [label="Generator 0" shape=square] clock_gen0;
sahilmgandhi	18:6a4db94011d3	206	* node [label="Channel x" shape=square] clock_chan0;
sahilmgandhi	18:6a4db94011d3	207	* node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
sahilmgandhi	18:6a4db94011d3	208	*
sahilmgandhi	18:6a4db94011d3	209	* system_clock_source0 -> clock_gen0;
sahilmgandhi	18:6a4db94011d3	210	* clock_gen0 -> clock_chan0;
sahilmgandhi	18:6a4db94011d3	211	* clock_chan0 -> peripheral0;
sahilmgandhi	18:6a4db94011d3	212	* node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
sahilmgandhi	18:6a4db94011d3	213	* node [label="Generator 1" shape=square] clock_gen1;
sahilmgandhi	18:6a4db94011d3	214	* node [label="Channel y" shape=square] clock_chan1;
sahilmgandhi	18:6a4db94011d3	215	* node [label="Channel z" shape=square] clock_chan2;
sahilmgandhi	18:6a4db94011d3	216	* node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
sahilmgandhi	18:6a4db94011d3	217	* node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
sahilmgandhi	18:6a4db94011d3	218	*
sahilmgandhi	18:6a4db94011d3	219	* system_clock_source1 -> clock_gen1;
sahilmgandhi	18:6a4db94011d3	220	* clock_gen1 -> clock_chan1;
sahilmgandhi	18:6a4db94011d3	221	* clock_gen1 -> clock_chan2;
sahilmgandhi	18:6a4db94011d3	222	* clock_chan1 -> peripheral1;
sahilmgandhi	18:6a4db94011d3	223	* clock_chan2 -> peripheral2;
sahilmgandhi	18:6a4db94011d3	224	* }
sahilmgandhi	18:6a4db94011d3	225	* \enddot
sahilmgandhi	18:6a4db94011d3	226	*
sahilmgandhi	18:6a4db94011d3	227	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
sahilmgandhi	18:6a4db94011d3	228	* Each Generic Clock generator within the device can source its input clock
sahilmgandhi	18:6a4db94011d3	229	* from one of the provided Source Clocks, and prescale the output for one or
sahilmgandhi	18:6a4db94011d3	230	* more Generic Clock Channels in a one-to-many relationship. The generators
sahilmgandhi	18:6a4db94011d3	231	* thus allow for several clocks to be generated of different frequencies,
sahilmgandhi	18:6a4db94011d3	232	* power usages, and accuracies, which can be turned on and off individually to
sahilmgandhi	18:6a4db94011d3	233	* disable the clocks to multiple peripherals as a group.
sahilmgandhi	18:6a4db94011d3	234	*
sahilmgandhi	18:6a4db94011d3	235	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
sahilmgandhi	18:6a4db94011d3	236	* To connect a Generic Clock Generator to a peripheral within the
sahilmgandhi	18:6a4db94011d3	237	* device, a Generic Clock Channel is used. Each peripheral or
sahilmgandhi	18:6a4db94011d3	238	* peripheral group has an associated Generic Clock Channel, which serves as the
sahilmgandhi	18:6a4db94011d3	239	* clock input for the peripheral(s). To supply a clock to the peripheral
sahilmgandhi	18:6a4db94011d3	240	* module(s), the associated channel must be connected to a running Generic
sahilmgandhi	18:6a4db94011d3	241	* Clock Generator and the channel enabled.
sahilmgandhi	18:6a4db94011d3	242	*
sahilmgandhi	18:6a4db94011d3	243	* \section asfdoc_sam0_system_clock_special_considerations Special Considerations
sahilmgandhi	18:6a4db94011d3	244	*
sahilmgandhi	18:6a4db94011d3	245	* There are no special considerations for this module.
sahilmgandhi	18:6a4db94011d3	246	*
sahilmgandhi	18:6a4db94011d3	247	*
sahilmgandhi	18:6a4db94011d3	248	* \section asfdoc_sam0_system_clock_extra_info Extra Information
sahilmgandhi	18:6a4db94011d3	249	*
sahilmgandhi	18:6a4db94011d3	250	* For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
sahilmgandhi	18:6a4db94011d3	251	* - \ref asfdoc_sam0_system_clock_extra_acronyms
sahilmgandhi	18:6a4db94011d3	252	* - \ref asfdoc_sam0_system_clock_extra_dependencies
sahilmgandhi	18:6a4db94011d3	253	* - \ref asfdoc_sam0_system_clock_extra_errata
sahilmgandhi	18:6a4db94011d3	254	* - \ref asfdoc_sam0_system_clock_extra_history
sahilmgandhi	18:6a4db94011d3	255	*
sahilmgandhi	18:6a4db94011d3	256	*
sahilmgandhi	18:6a4db94011d3	257	* \section asfdoc_sam0_system_clock_examples Examples
sahilmgandhi	18:6a4db94011d3	258	*
sahilmgandhi	18:6a4db94011d3	259	* For a list of examples related to this driver, see
sahilmgandhi	18:6a4db94011d3	260	* \ref asfdoc_sam0_system_clock_exqsg.
sahilmgandhi	18:6a4db94011d3	261	*
sahilmgandhi	18:6a4db94011d3	262	*
sahilmgandhi	18:6a4db94011d3	263	* \section asfdoc_sam0_system_clock_api_overview API Overview
sahilmgandhi	18:6a4db94011d3	264	* @{
sahilmgandhi	18:6a4db94011d3	265	*/
sahilmgandhi	18:6a4db94011d3	266
sahilmgandhi	18:6a4db94011d3	267	#include <compiler.h>
sahilmgandhi	18:6a4db94011d3	268	#include <gclk.h>
sahilmgandhi	18:6a4db94011d3	269
sahilmgandhi	18:6a4db94011d3	270	/**
sahilmgandhi	18:6a4db94011d3	271	* \name Driver Feature Definition
sahilmgandhi	18:6a4db94011d3	272	* Define system clock features set according to different device family.
sahilmgandhi	18:6a4db94011d3	273	* @{
sahilmgandhi	18:6a4db94011d3	274	*/
sahilmgandhi	18:6a4db94011d3	275	#if (SAMD21) \|\| (SAMR21) \|\| (SAMD11) \|\| (SAMD10) \|\| (SAMDA1) \|\| defined(__DOXYGEN__)
sahilmgandhi	18:6a4db94011d3	276	/** Digital Phase Locked Loop (DPLL) feature support. */
sahilmgandhi	18:6a4db94011d3	277	# define FEATURE_SYSTEM_CLOCK_DPLL
sahilmgandhi	18:6a4db94011d3	278	#endif
sahilmgandhi	18:6a4db94011d3	279	/@}/
sahilmgandhi	18:6a4db94011d3	280
sahilmgandhi	18:6a4db94011d3	281	/**
sahilmgandhi	18:6a4db94011d3	282	* \brief Available start-up times for the XOSC32K.
sahilmgandhi	18:6a4db94011d3	283	*
sahilmgandhi	18:6a4db94011d3	284	* Available external 32KHz oscillator start-up times, as a number of external
sahilmgandhi	18:6a4db94011d3	285	* clock cycles.
sahilmgandhi	18:6a4db94011d3	286	*/
sahilmgandhi	18:6a4db94011d3	287	enum system_xosc32k_startup {
sahilmgandhi	18:6a4db94011d3	288	/** Wait zero clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	289	SYSTEM_XOSC32K_STARTUP_0,
sahilmgandhi	18:6a4db94011d3	290	/** Wait 32 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	291	SYSTEM_XOSC32K_STARTUP_32,
sahilmgandhi	18:6a4db94011d3	292	/** Wait 2048 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	293	SYSTEM_XOSC32K_STARTUP_2048,
sahilmgandhi	18:6a4db94011d3	294	/** Wait 4096 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	295	SYSTEM_XOSC32K_STARTUP_4096,
sahilmgandhi	18:6a4db94011d3	296	/** Wait 16384 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	297	SYSTEM_XOSC32K_STARTUP_16384,
sahilmgandhi	18:6a4db94011d3	298	/** Wait 32768 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	299	SYSTEM_XOSC32K_STARTUP_32768,
sahilmgandhi	18:6a4db94011d3	300	/** Wait 65536 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	301	SYSTEM_XOSC32K_STARTUP_65536,
sahilmgandhi	18:6a4db94011d3	302	/** Wait 131072 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	303	SYSTEM_XOSC32K_STARTUP_131072,
sahilmgandhi	18:6a4db94011d3	304	};
sahilmgandhi	18:6a4db94011d3	305
sahilmgandhi	18:6a4db94011d3	306	/**
sahilmgandhi	18:6a4db94011d3	307	* \brief Available start-up times for the XOSC.
sahilmgandhi	18:6a4db94011d3	308	*
sahilmgandhi	18:6a4db94011d3	309	* Available external oscillator start-up times, as a number of external clock
sahilmgandhi	18:6a4db94011d3	310	* cycles.
sahilmgandhi	18:6a4db94011d3	311	*/
sahilmgandhi	18:6a4db94011d3	312	enum system_xosc_startup {
sahilmgandhi	18:6a4db94011d3	313	/** Wait one clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	314	SYSTEM_XOSC_STARTUP_1,
sahilmgandhi	18:6a4db94011d3	315	/** Wait two clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	316	SYSTEM_XOSC_STARTUP_2,
sahilmgandhi	18:6a4db94011d3	317	/** Wait four clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	318	SYSTEM_XOSC_STARTUP_4,
sahilmgandhi	18:6a4db94011d3	319	/** Wait eight clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	320	SYSTEM_XOSC_STARTUP_8,
sahilmgandhi	18:6a4db94011d3	321	/** Wait 16 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	322	SYSTEM_XOSC_STARTUP_16,
sahilmgandhi	18:6a4db94011d3	323	/** Wait 32 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	324	SYSTEM_XOSC_STARTUP_32,
sahilmgandhi	18:6a4db94011d3	325	/** Wait 64 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	326	SYSTEM_XOSC_STARTUP_64,
sahilmgandhi	18:6a4db94011d3	327	/** Wait 128 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	328	SYSTEM_XOSC_STARTUP_128,
sahilmgandhi	18:6a4db94011d3	329	/** Wait 256 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	330	SYSTEM_XOSC_STARTUP_256,
sahilmgandhi	18:6a4db94011d3	331	/** Wait 512 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	332	SYSTEM_XOSC_STARTUP_512,
sahilmgandhi	18:6a4db94011d3	333	/** Wait 1024 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	334	SYSTEM_XOSC_STARTUP_1024,
sahilmgandhi	18:6a4db94011d3	335	/** Wait 2048 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	336	SYSTEM_XOSC_STARTUP_2048,
sahilmgandhi	18:6a4db94011d3	337	/** Wait 4096 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	338	SYSTEM_XOSC_STARTUP_4096,
sahilmgandhi	18:6a4db94011d3	339	/** Wait 8192 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	340	SYSTEM_XOSC_STARTUP_8192,
sahilmgandhi	18:6a4db94011d3	341	/** Wait 16384 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	342	SYSTEM_XOSC_STARTUP_16384,
sahilmgandhi	18:6a4db94011d3	343	/** Wait 32768 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	344	SYSTEM_XOSC_STARTUP_32768,
sahilmgandhi	18:6a4db94011d3	345	};
sahilmgandhi	18:6a4db94011d3	346
sahilmgandhi	18:6a4db94011d3	347	/**
sahilmgandhi	18:6a4db94011d3	348	* \brief Available start-up times for the OSC32K.
sahilmgandhi	18:6a4db94011d3	349	*
sahilmgandhi	18:6a4db94011d3	350	* Available internal 32KHz oscillator start-up times, as a number of internal
sahilmgandhi	18:6a4db94011d3	351	* OSC32K clock cycles.
sahilmgandhi	18:6a4db94011d3	352	*/
sahilmgandhi	18:6a4db94011d3	353	enum system_osc32k_startup {
sahilmgandhi	18:6a4db94011d3	354	/** Wait three clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	355	SYSTEM_OSC32K_STARTUP_3,
sahilmgandhi	18:6a4db94011d3	356	/** Wait four clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	357	SYSTEM_OSC32K_STARTUP_4,
sahilmgandhi	18:6a4db94011d3	358	/** Wait six clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	359	SYSTEM_OSC32K_STARTUP_6,
sahilmgandhi	18:6a4db94011d3	360	/** Wait ten clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	361	SYSTEM_OSC32K_STARTUP_10,
sahilmgandhi	18:6a4db94011d3	362	/** Wait 18 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	363	SYSTEM_OSC32K_STARTUP_18,
sahilmgandhi	18:6a4db94011d3	364	/** Wait 34 clock cycles until the clock source is considered stable */
sahilmgandhi	18:6a4db94011d3	365	SYSTEM_OSC32K_STARTUP_34,
sahilmgandhi	18:6a4db94011d3	366	/** Wait 66 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	367	SYSTEM_OSC32K_STARTUP_66,
sahilmgandhi	18:6a4db94011d3	368	/** Wait 130 clock cycles until the clock source is considered stable. */
sahilmgandhi	18:6a4db94011d3	369	SYSTEM_OSC32K_STARTUP_130,
sahilmgandhi	18:6a4db94011d3	370	};
sahilmgandhi	18:6a4db94011d3	371
sahilmgandhi	18:6a4db94011d3	372	/**
sahilmgandhi	18:6a4db94011d3	373	* \brief Division prescalers for the internal 8MHz system clock.
sahilmgandhi	18:6a4db94011d3	374	*
sahilmgandhi	18:6a4db94011d3	375	* Available prescalers for the internal 8MHz (nominal) system clock.
sahilmgandhi	18:6a4db94011d3	376	*/
sahilmgandhi	18:6a4db94011d3	377	enum system_osc8m_div {
sahilmgandhi	18:6a4db94011d3	378	/** Do not divide the 8MHz RC oscillator output. */
sahilmgandhi	18:6a4db94011d3	379	SYSTEM_OSC8M_DIV_1,
sahilmgandhi	18:6a4db94011d3	380	/** Divide the 8MHz RC oscillator output by two. */
sahilmgandhi	18:6a4db94011d3	381	SYSTEM_OSC8M_DIV_2,
sahilmgandhi	18:6a4db94011d3	382	/** Divide the 8MHz RC oscillator output by four. */
sahilmgandhi	18:6a4db94011d3	383	SYSTEM_OSC8M_DIV_4,
sahilmgandhi	18:6a4db94011d3	384	/** Divide the 8MHz RC oscillator output by eight. */
sahilmgandhi	18:6a4db94011d3	385	SYSTEM_OSC8M_DIV_8,
sahilmgandhi	18:6a4db94011d3	386	};
sahilmgandhi	18:6a4db94011d3	387
sahilmgandhi	18:6a4db94011d3	388	/**
sahilmgandhi	18:6a4db94011d3	389	* \brief Frequency range for the internal 8MHz RC oscillator.
sahilmgandhi	18:6a4db94011d3	390	*
sahilmgandhi	18:6a4db94011d3	391	* Internal 8MHz RC oscillator frequency range setting
sahilmgandhi	18:6a4db94011d3	392	*/
sahilmgandhi	18:6a4db94011d3	393	enum system_osc8m_frequency_range {
sahilmgandhi	18:6a4db94011d3	394	/** Frequency range 4MHz to 6MHz. */
sahilmgandhi	18:6a4db94011d3	395	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
sahilmgandhi	18:6a4db94011d3	396	/** Frequency range 6MHz to 8MHz. */
sahilmgandhi	18:6a4db94011d3	397	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
sahilmgandhi	18:6a4db94011d3	398	/** Frequency range 8MHz to 11MHz. */
sahilmgandhi	18:6a4db94011d3	399	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
sahilmgandhi	18:6a4db94011d3	400	/** Frequency range 11MHz to 15MHz. */
sahilmgandhi	18:6a4db94011d3	401	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
sahilmgandhi	18:6a4db94011d3	402	};
sahilmgandhi	18:6a4db94011d3	403
sahilmgandhi	18:6a4db94011d3	404	/**
sahilmgandhi	18:6a4db94011d3	405	* \brief Main CPU and APB/AHB bus clock source prescaler values.
sahilmgandhi	18:6a4db94011d3	406	*
sahilmgandhi	18:6a4db94011d3	407	* Available division ratios for the CPU and APB/AHB bus clocks.
sahilmgandhi	18:6a4db94011d3	408	*/
sahilmgandhi	18:6a4db94011d3	409	enum system_main_clock_div {
sahilmgandhi	18:6a4db94011d3	410	/** Divide Main clock by one. */
sahilmgandhi	18:6a4db94011d3	411	SYSTEM_MAIN_CLOCK_DIV_1,
sahilmgandhi	18:6a4db94011d3	412	/** Divide Main clock by two. */
sahilmgandhi	18:6a4db94011d3	413	SYSTEM_MAIN_CLOCK_DIV_2,
sahilmgandhi	18:6a4db94011d3	414	/** Divide Main clock by four. */
sahilmgandhi	18:6a4db94011d3	415	SYSTEM_MAIN_CLOCK_DIV_4,
sahilmgandhi	18:6a4db94011d3	416	/** Divide Main clock by eight. */
sahilmgandhi	18:6a4db94011d3	417	SYSTEM_MAIN_CLOCK_DIV_8,
sahilmgandhi	18:6a4db94011d3	418	/** Divide Main clock by 16. */
sahilmgandhi	18:6a4db94011d3	419	SYSTEM_MAIN_CLOCK_DIV_16,
sahilmgandhi	18:6a4db94011d3	420	/** Divide Main clock by 32. */
sahilmgandhi	18:6a4db94011d3	421	SYSTEM_MAIN_CLOCK_DIV_32,
sahilmgandhi	18:6a4db94011d3	422	/** Divide Main clock by 64. */
sahilmgandhi	18:6a4db94011d3	423	SYSTEM_MAIN_CLOCK_DIV_64,
sahilmgandhi	18:6a4db94011d3	424	/** Divide Main clock by 128. */
sahilmgandhi	18:6a4db94011d3	425	SYSTEM_MAIN_CLOCK_DIV_128,
sahilmgandhi	18:6a4db94011d3	426	};
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/**
sahilmgandhi	18:6a4db94011d3	429	* \brief External clock source types.
sahilmgandhi	18:6a4db94011d3	430	*
sahilmgandhi	18:6a4db94011d3	431	* Available external clock source types.
sahilmgandhi	18:6a4db94011d3	432	*/
sahilmgandhi	18:6a4db94011d3	433	enum system_clock_external {
sahilmgandhi	18:6a4db94011d3	434	/** The external clock source is a crystal oscillator. */
sahilmgandhi	18:6a4db94011d3	435	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
sahilmgandhi	18:6a4db94011d3	436	/** The connected clock source is an external logic level clock signal. */
sahilmgandhi	18:6a4db94011d3	437	SYSTEM_CLOCK_EXTERNAL_CLOCK,
sahilmgandhi	18:6a4db94011d3	438	};
sahilmgandhi	18:6a4db94011d3	439
sahilmgandhi	18:6a4db94011d3	440	/**
sahilmgandhi	18:6a4db94011d3	441	* \brief Operating modes of the DFLL clock source.
sahilmgandhi	18:6a4db94011d3	442	*
sahilmgandhi	18:6a4db94011d3	443	* Available operating modes of the DFLL clock source module.
sahilmgandhi	18:6a4db94011d3	444	*/
sahilmgandhi	18:6a4db94011d3	445	enum system_clock_dfll_loop_mode {
sahilmgandhi	18:6a4db94011d3	446	/** The DFLL is operating in open loop mode with no feedback. */
sahilmgandhi	18:6a4db94011d3	447	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
sahilmgandhi	18:6a4db94011d3	448	/** The DFLL is operating in closed loop mode with frequency feedback from
sahilmgandhi	18:6a4db94011d3	449	* a low frequency reference clock.
sahilmgandhi	18:6a4db94011d3	450	*/
sahilmgandhi	18:6a4db94011d3	451	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
sahilmgandhi	18:6a4db94011d3	452
sahilmgandhi	18:6a4db94011d3	453	#ifdef SYSCTRL_DFLLCTRL_USBCRM
sahilmgandhi	18:6a4db94011d3	454	/** The DFLL is operating in USB recovery mode with frequency feedback
sahilmgandhi	18:6a4db94011d3	455	* from USB SOF.
sahilmgandhi	18:6a4db94011d3	456	*/
sahilmgandhi	18:6a4db94011d3	457	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
sahilmgandhi	18:6a4db94011d3	458	#endif
sahilmgandhi	18:6a4db94011d3	459	};
sahilmgandhi	18:6a4db94011d3	460
sahilmgandhi	18:6a4db94011d3	461	/**
sahilmgandhi	18:6a4db94011d3	462	* \brief Locking behavior for the DFLL during device wake-up.
sahilmgandhi	18:6a4db94011d3	463	*
sahilmgandhi	18:6a4db94011d3	464	* DFLL lock behavior modes on device wake-up from sleep.
sahilmgandhi	18:6a4db94011d3	465	*/
sahilmgandhi	18:6a4db94011d3	466	enum system_clock_dfll_wakeup_lock {
sahilmgandhi	18:6a4db94011d3	467	/** Keep DFLL lock when the device wakes from sleep. */
sahilmgandhi	18:6a4db94011d3	468	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
sahilmgandhi	18:6a4db94011d3	469	/** Lose DFLL lock when the devices wakes from sleep. */
sahilmgandhi	18:6a4db94011d3	470	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
sahilmgandhi	18:6a4db94011d3	471	};
sahilmgandhi	18:6a4db94011d3	472
sahilmgandhi	18:6a4db94011d3	473	/**
sahilmgandhi	18:6a4db94011d3	474	* \brief Fine tracking behavior for the DFLL once a lock has been acquired.
sahilmgandhi	18:6a4db94011d3	475	*
sahilmgandhi	18:6a4db94011d3	476	* DFLL fine tracking behavior modes after a lock has been acquired.
sahilmgandhi	18:6a4db94011d3	477	*/
sahilmgandhi	18:6a4db94011d3	478	enum system_clock_dfll_stable_tracking {
sahilmgandhi	18:6a4db94011d3	479	/** Keep tracking after the DFLL has gotten a fine lock. */
sahilmgandhi	18:6a4db94011d3	480	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
sahilmgandhi	18:6a4db94011d3	481	/** Stop tracking after the DFLL has gotten a fine lock. */
sahilmgandhi	18:6a4db94011d3	482	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
sahilmgandhi	18:6a4db94011d3	483	};
sahilmgandhi	18:6a4db94011d3	484
sahilmgandhi	18:6a4db94011d3	485	/**
sahilmgandhi	18:6a4db94011d3	486	* \brief Chill-cycle behavior of the DFLL module.
sahilmgandhi	18:6a4db94011d3	487	*
sahilmgandhi	18:6a4db94011d3	488	* DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
sahilmgandhi	18:6a4db94011d3	489	* of time when the DFLL output frequency is not measured by the unit, to allow
sahilmgandhi	18:6a4db94011d3	490	* the output to stabilize after a change in the input clock source.
sahilmgandhi	18:6a4db94011d3	491	*/
sahilmgandhi	18:6a4db94011d3	492	enum system_clock_dfll_chill_cycle {
sahilmgandhi	18:6a4db94011d3	493	/** Enable a chill cycle, where the DFLL output frequency is not measured. */
sahilmgandhi	18:6a4db94011d3	494	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
sahilmgandhi	18:6a4db94011d3	495	/** Disable a chill cycle, where the DFLL output frequency is not measured. */
sahilmgandhi	18:6a4db94011d3	496	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
sahilmgandhi	18:6a4db94011d3	497	};
sahilmgandhi	18:6a4db94011d3	498
sahilmgandhi	18:6a4db94011d3	499	/**
sahilmgandhi	18:6a4db94011d3	500	* \brief QuickLock settings for the DFLL module.
sahilmgandhi	18:6a4db94011d3	501	*
sahilmgandhi	18:6a4db94011d3	502	* DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
sahilmgandhi	18:6a4db94011d3	503	* the DFLL output frequency at the expense of accuracy.
sahilmgandhi	18:6a4db94011d3	504	*/
sahilmgandhi	18:6a4db94011d3	505	enum system_clock_dfll_quick_lock {
sahilmgandhi	18:6a4db94011d3	506	/** Enable the QuickLock feature for looser lock requirements on the DFLL. */
sahilmgandhi	18:6a4db94011d3	507	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
sahilmgandhi	18:6a4db94011d3	508	/** Disable the QuickLock feature for strict lock requirements on the DFLL. */
sahilmgandhi	18:6a4db94011d3	509	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
sahilmgandhi	18:6a4db94011d3	510	};
sahilmgandhi	18:6a4db94011d3	511
sahilmgandhi	18:6a4db94011d3	512	/**
sahilmgandhi	18:6a4db94011d3	513	* \brief Available clock sources in the system.
sahilmgandhi	18:6a4db94011d3	514	*
sahilmgandhi	18:6a4db94011d3	515	* Clock sources available to the GCLK generators.
sahilmgandhi	18:6a4db94011d3	516	*/
sahilmgandhi	18:6a4db94011d3	517	enum system_clock_source {
sahilmgandhi	18:6a4db94011d3	518	/** Internal 8MHz RC oscillator. */
sahilmgandhi	18:6a4db94011d3	519	SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
sahilmgandhi	18:6a4db94011d3	520	/** Internal 32KHz RC oscillator. */
sahilmgandhi	18:6a4db94011d3	521	SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
sahilmgandhi	18:6a4db94011d3	522	/** External oscillator. */
sahilmgandhi	18:6a4db94011d3	523	SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
sahilmgandhi	18:6a4db94011d3	524	/** External 32KHz oscillator. */
sahilmgandhi	18:6a4db94011d3	525	SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
sahilmgandhi	18:6a4db94011d3	526	/** Digital Frequency Locked Loop (DFLL). */
sahilmgandhi	18:6a4db94011d3	527	SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
sahilmgandhi	18:6a4db94011d3	528	/** Internal Ultra Low Power 32KHz oscillator. */
sahilmgandhi	18:6a4db94011d3	529	SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
sahilmgandhi	18:6a4db94011d3	530	/** Generator input pad. */
sahilmgandhi	18:6a4db94011d3	531	SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
sahilmgandhi	18:6a4db94011d3	532	/** Generic clock generator one output. */
sahilmgandhi	18:6a4db94011d3	533	SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
sahilmgandhi	18:6a4db94011d3	534	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
sahilmgandhi	18:6a4db94011d3	535	/** Digital Phase Locked Loop (DPLL).
sahilmgandhi	18:6a4db94011d3	536	* Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
sahilmgandhi	18:6a4db94011d3	537	*/
sahilmgandhi	18:6a4db94011d3	538	SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
sahilmgandhi	18:6a4db94011d3	539	#endif
sahilmgandhi	18:6a4db94011d3	540	};
sahilmgandhi	18:6a4db94011d3	541
sahilmgandhi	18:6a4db94011d3	542	/**
sahilmgandhi	18:6a4db94011d3	543	* \brief List of APB peripheral buses.
sahilmgandhi	18:6a4db94011d3	544	*
sahilmgandhi	18:6a4db94011d3	545	* Available bus clock domains on the APB bus.
sahilmgandhi	18:6a4db94011d3	546	*/
sahilmgandhi	18:6a4db94011d3	547	enum system_clock_apb_bus {
sahilmgandhi	18:6a4db94011d3	548	/** Peripheral bus A on the APB bus. */
sahilmgandhi	18:6a4db94011d3	549	SYSTEM_CLOCK_APB_APBA,
sahilmgandhi	18:6a4db94011d3	550	/** Peripheral bus B on the APB bus. */
sahilmgandhi	18:6a4db94011d3	551	SYSTEM_CLOCK_APB_APBB,
sahilmgandhi	18:6a4db94011d3	552	/** Peripheral bus C on the APB bus. */
sahilmgandhi	18:6a4db94011d3	553	SYSTEM_CLOCK_APB_APBC,
sahilmgandhi	18:6a4db94011d3	554	};
sahilmgandhi	18:6a4db94011d3	555
sahilmgandhi	18:6a4db94011d3	556	/**
sahilmgandhi	18:6a4db94011d3	557	* \brief Configuration structure for XOSC.
sahilmgandhi	18:6a4db94011d3	558	*
sahilmgandhi	18:6a4db94011d3	559	* External oscillator clock configuration structure.
sahilmgandhi	18:6a4db94011d3	560	*/
sahilmgandhi	18:6a4db94011d3	561	struct system_clock_source_xosc_config {
sahilmgandhi	18:6a4db94011d3	562	/** External clock type. */
sahilmgandhi	18:6a4db94011d3	563	enum system_clock_external external_clock;
sahilmgandhi	18:6a4db94011d3	564	/** Crystal oscillator start-up time. */
sahilmgandhi	18:6a4db94011d3	565	enum system_xosc_startup startup_time;
sahilmgandhi	18:6a4db94011d3	566	/** Enable automatic amplitude gain control. */
sahilmgandhi	18:6a4db94011d3	567	bool auto_gain_control;
sahilmgandhi	18:6a4db94011d3	568	/** External clock/crystal frequency. */
sahilmgandhi	18:6a4db94011d3	569	uint32_t frequency;
sahilmgandhi	18:6a4db94011d3	570	/** Keep the XOSC enabled in standby sleep mode. */
sahilmgandhi	18:6a4db94011d3	571	bool run_in_standby;
sahilmgandhi	18:6a4db94011d3	572	/** Run On Demand. If this is set the XOSC won't run
sahilmgandhi	18:6a4db94011d3	573	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	574	bool on_demand;
sahilmgandhi	18:6a4db94011d3	575	};
sahilmgandhi	18:6a4db94011d3	576
sahilmgandhi	18:6a4db94011d3	577	/**
sahilmgandhi	18:6a4db94011d3	578	* \brief Configuration structure for XOSC32K.
sahilmgandhi	18:6a4db94011d3	579	*
sahilmgandhi	18:6a4db94011d3	580	* External 32KHz oscillator clock configuration structure.
sahilmgandhi	18:6a4db94011d3	581	*/
sahilmgandhi	18:6a4db94011d3	582	struct system_clock_source_xosc32k_config {
sahilmgandhi	18:6a4db94011d3	583	/** External clock type. */
sahilmgandhi	18:6a4db94011d3	584	enum system_clock_external external_clock;
sahilmgandhi	18:6a4db94011d3	585	/** Crystal oscillator start-up time. */
sahilmgandhi	18:6a4db94011d3	586	enum system_xosc32k_startup startup_time;
sahilmgandhi	18:6a4db94011d3	587	/** Enable automatic amplitude control. */
sahilmgandhi	18:6a4db94011d3	588	bool auto_gain_control;
sahilmgandhi	18:6a4db94011d3	589	/** Enable 1KHz output. */
sahilmgandhi	18:6a4db94011d3	590	bool enable_1khz_output;
sahilmgandhi	18:6a4db94011d3	591	/** Enable 32KHz output. */
sahilmgandhi	18:6a4db94011d3	592	bool enable_32khz_output;
sahilmgandhi	18:6a4db94011d3	593	/** External clock/crystal frequency. */
sahilmgandhi	18:6a4db94011d3	594	uint32_t frequency;
sahilmgandhi	18:6a4db94011d3	595	/** Keep the XOSC32K enabled in standby sleep mode. */
sahilmgandhi	18:6a4db94011d3	596	bool run_in_standby;
sahilmgandhi	18:6a4db94011d3	597	/** Run On Demand. If this is set the XOSC32K won't run
sahilmgandhi	18:6a4db94011d3	598	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	599	bool on_demand;
sahilmgandhi	18:6a4db94011d3	600	/** Lock configuration after it has been written,
sahilmgandhi	18:6a4db94011d3	601	* a device reset will release the lock. */
sahilmgandhi	18:6a4db94011d3	602	bool write_once;
sahilmgandhi	18:6a4db94011d3	603	};
sahilmgandhi	18:6a4db94011d3	604
sahilmgandhi	18:6a4db94011d3	605	/**
sahilmgandhi	18:6a4db94011d3	606	* \brief Configuration structure for OSC8M.
sahilmgandhi	18:6a4db94011d3	607	*
sahilmgandhi	18:6a4db94011d3	608	* Internal 8MHz (nominal) oscillator configuration structure.
sahilmgandhi	18:6a4db94011d3	609	*/
sahilmgandhi	18:6a4db94011d3	610	struct system_clock_source_osc8m_config {
sahilmgandhi	18:6a4db94011d3	611	/** Internal 8MHz RC oscillator prescaler. */
sahilmgandhi	18:6a4db94011d3	612	enum system_osc8m_div prescaler;
sahilmgandhi	18:6a4db94011d3	613	/** Keep the OSC8M enabled in standby sleep mode. */
sahilmgandhi	18:6a4db94011d3	614	bool run_in_standby;
sahilmgandhi	18:6a4db94011d3	615	/** Run On Demand. If this is set the OSC8M won't run
sahilmgandhi	18:6a4db94011d3	616	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	617	bool on_demand;
sahilmgandhi	18:6a4db94011d3	618	};
sahilmgandhi	18:6a4db94011d3	619
sahilmgandhi	18:6a4db94011d3	620	/**
sahilmgandhi	18:6a4db94011d3	621	* \brief Configuration structure for OSC32K.
sahilmgandhi	18:6a4db94011d3	622	*
sahilmgandhi	18:6a4db94011d3	623	* Internal 32KHz (nominal) oscillator configuration structure.
sahilmgandhi	18:6a4db94011d3	624	*/
sahilmgandhi	18:6a4db94011d3	625	struct system_clock_source_osc32k_config {
sahilmgandhi	18:6a4db94011d3	626	/** Startup time. */
sahilmgandhi	18:6a4db94011d3	627	enum system_osc32k_startup startup_time;
sahilmgandhi	18:6a4db94011d3	628	/** Enable 1KHz output. */
sahilmgandhi	18:6a4db94011d3	629	bool enable_1khz_output;
sahilmgandhi	18:6a4db94011d3	630	/** Enable 32KHz output. */
sahilmgandhi	18:6a4db94011d3	631	bool enable_32khz_output;
sahilmgandhi	18:6a4db94011d3	632	/** Keep the OSC32K enabled in standby sleep mode. */
sahilmgandhi	18:6a4db94011d3	633	bool run_in_standby;
sahilmgandhi	18:6a4db94011d3	634	/** Run On Demand. If this is set the OSC32K won't run
sahilmgandhi	18:6a4db94011d3	635	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	636	bool on_demand;
sahilmgandhi	18:6a4db94011d3	637	/** Lock configuration after it has been written,
sahilmgandhi	18:6a4db94011d3	638	* a device reset will release the lock. */
sahilmgandhi	18:6a4db94011d3	639	bool write_once;
sahilmgandhi	18:6a4db94011d3	640	};
sahilmgandhi	18:6a4db94011d3	641
sahilmgandhi	18:6a4db94011d3	642	/**
sahilmgandhi	18:6a4db94011d3	643	* \brief Configuration structure for DFLL.
sahilmgandhi	18:6a4db94011d3	644	*
sahilmgandhi	18:6a4db94011d3	645	* DFLL oscillator configuration structure.
sahilmgandhi	18:6a4db94011d3	646	*/
sahilmgandhi	18:6a4db94011d3	647	struct system_clock_source_dfll_config {
sahilmgandhi	18:6a4db94011d3	648	/** Loop mode. */
sahilmgandhi	18:6a4db94011d3	649	enum system_clock_dfll_loop_mode loop_mode;
sahilmgandhi	18:6a4db94011d3	650	/** Run On Demand. If this is set the DFLL won't run
sahilmgandhi	18:6a4db94011d3	651	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	652	bool on_demand;
sahilmgandhi	18:6a4db94011d3	653	/** Enable Quick Lock. */
sahilmgandhi	18:6a4db94011d3	654	enum system_clock_dfll_quick_lock quick_lock;
sahilmgandhi	18:6a4db94011d3	655	/** Enable Chill Cycle. */
sahilmgandhi	18:6a4db94011d3	656	enum system_clock_dfll_chill_cycle chill_cycle;
sahilmgandhi	18:6a4db94011d3	657	/** DFLL lock state on wakeup. */
sahilmgandhi	18:6a4db94011d3	658	enum system_clock_dfll_wakeup_lock wakeup_lock;
sahilmgandhi	18:6a4db94011d3	659	/** DFLL tracking after fine lock. */
sahilmgandhi	18:6a4db94011d3	660	enum system_clock_dfll_stable_tracking stable_tracking;
sahilmgandhi	18:6a4db94011d3	661	/** Coarse calibration value (Open loop mode). */
sahilmgandhi	18:6a4db94011d3	662	uint8_t coarse_value;
sahilmgandhi	18:6a4db94011d3	663	/** Fine calibration value (Open loop mode). */
sahilmgandhi	18:6a4db94011d3	664	uint16_t fine_value;
sahilmgandhi	18:6a4db94011d3	665	/** Coarse adjustment maximum step size (Closed loop mode). */
sahilmgandhi	18:6a4db94011d3	666	uint8_t coarse_max_step;
sahilmgandhi	18:6a4db94011d3	667	/** Fine adjustment maximum step size (Closed loop mode). */
sahilmgandhi	18:6a4db94011d3	668	uint16_t fine_max_step;
sahilmgandhi	18:6a4db94011d3	669	/** DFLL multiply factor (Closed loop mode. */
sahilmgandhi	18:6a4db94011d3	670	uint16_t multiply_factor;
sahilmgandhi	18:6a4db94011d3	671	};
sahilmgandhi	18:6a4db94011d3	672
sahilmgandhi	18:6a4db94011d3	673	/**
sahilmgandhi	18:6a4db94011d3	674	* \name External Oscillator Management
sahilmgandhi	18:6a4db94011d3	675	* @{
sahilmgandhi	18:6a4db94011d3	676	*/
sahilmgandhi	18:6a4db94011d3	677
sahilmgandhi	18:6a4db94011d3	678	/**
sahilmgandhi	18:6a4db94011d3	679	* \brief Retrieve the default configuration for XOSC.
sahilmgandhi	18:6a4db94011d3	680	*
sahilmgandhi	18:6a4db94011d3	681	* Fills a configuration structure with the default configuration for an
sahilmgandhi	18:6a4db94011d3	682	* external oscillator module:
sahilmgandhi	18:6a4db94011d3	683	* - External Crystal
sahilmgandhi	18:6a4db94011d3	684	* - Start-up time of 16384 external clock cycles
sahilmgandhi	18:6a4db94011d3	685	* - Automatic crystal gain control mode enabled
sahilmgandhi	18:6a4db94011d3	686	* - Frequency of 12MHz
sahilmgandhi	18:6a4db94011d3	687	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	688	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	689	*
sahilmgandhi	18:6a4db94011d3	690	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	691	*/
sahilmgandhi	18:6a4db94011d3	692	static inline void system_clock_source_xosc_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	693	struct system_clock_source_xosc_config *const config)
sahilmgandhi	18:6a4db94011d3	694	{
sahilmgandhi	18:6a4db94011d3	695	Assert(config);
sahilmgandhi	18:6a4db94011d3	696
sahilmgandhi	18:6a4db94011d3	697	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
sahilmgandhi	18:6a4db94011d3	698	config->startup_time = SYSTEM_XOSC_STARTUP_16384;
sahilmgandhi	18:6a4db94011d3	699	config->auto_gain_control = true;
sahilmgandhi	18:6a4db94011d3	700	config->frequency = 12000000UL;
sahilmgandhi	18:6a4db94011d3	701	config->run_in_standby = false;
sahilmgandhi	18:6a4db94011d3	702	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	703	}
sahilmgandhi	18:6a4db94011d3	704
sahilmgandhi	18:6a4db94011d3	705	void system_clock_source_xosc_set_config(
sahilmgandhi	18:6a4db94011d3	706	struct system_clock_source_xosc_config *const config);
sahilmgandhi	18:6a4db94011d3	707
sahilmgandhi	18:6a4db94011d3	708	/**
sahilmgandhi	18:6a4db94011d3	709	* @}
sahilmgandhi	18:6a4db94011d3	710	*/
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712
sahilmgandhi	18:6a4db94011d3	713	/**
sahilmgandhi	18:6a4db94011d3	714	* \name External 32KHz Oscillator Management
sahilmgandhi	18:6a4db94011d3	715	* @{
sahilmgandhi	18:6a4db94011d3	716	*/
sahilmgandhi	18:6a4db94011d3	717
sahilmgandhi	18:6a4db94011d3	718	/**
sahilmgandhi	18:6a4db94011d3	719	* \brief Retrieve the default configuration for XOSC32K.
sahilmgandhi	18:6a4db94011d3	720	*
sahilmgandhi	18:6a4db94011d3	721	* Fills a configuration structure with the default configuration for an
sahilmgandhi	18:6a4db94011d3	722	* external 32KHz oscillator module:
sahilmgandhi	18:6a4db94011d3	723	* - External Crystal
sahilmgandhi	18:6a4db94011d3	724	* - Start-up time of 16384 external clock cycles
sahilmgandhi	18:6a4db94011d3	725	* - Automatic crystal gain control mode disabled
sahilmgandhi	18:6a4db94011d3	726	* - Frequency of 32.768KHz
sahilmgandhi	18:6a4db94011d3	727	* - 1KHz clock output disabled
sahilmgandhi	18:6a4db94011d3	728	* - 32KHz clock output enabled
sahilmgandhi	18:6a4db94011d3	729	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	730	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	731	* - Don't lock registers after configuration has been written
sahilmgandhi	18:6a4db94011d3	732	*
sahilmgandhi	18:6a4db94011d3	733	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	734	*/
sahilmgandhi	18:6a4db94011d3	735	static inline void system_clock_source_xosc32k_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	736	struct system_clock_source_xosc32k_config *const config)
sahilmgandhi	18:6a4db94011d3	737	{
sahilmgandhi	18:6a4db94011d3	738	Assert(config);
sahilmgandhi	18:6a4db94011d3	739
sahilmgandhi	18:6a4db94011d3	740	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
sahilmgandhi	18:6a4db94011d3	741	config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
sahilmgandhi	18:6a4db94011d3	742	config->auto_gain_control = false;
sahilmgandhi	18:6a4db94011d3	743	config->frequency = 32768UL;
sahilmgandhi	18:6a4db94011d3	744	config->enable_1khz_output = false;
sahilmgandhi	18:6a4db94011d3	745	config->enable_32khz_output = true;
sahilmgandhi	18:6a4db94011d3	746	config->run_in_standby = false;
sahilmgandhi	18:6a4db94011d3	747	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	748	config->write_once = false;
sahilmgandhi	18:6a4db94011d3	749	}
sahilmgandhi	18:6a4db94011d3	750
sahilmgandhi	18:6a4db94011d3	751	void system_clock_source_xosc32k_set_config(
sahilmgandhi	18:6a4db94011d3	752	struct system_clock_source_xosc32k_config *const config);
sahilmgandhi	18:6a4db94011d3	753	/**
sahilmgandhi	18:6a4db94011d3	754	* @}
sahilmgandhi	18:6a4db94011d3	755	*/
sahilmgandhi	18:6a4db94011d3	756
sahilmgandhi	18:6a4db94011d3	757
sahilmgandhi	18:6a4db94011d3	758	/**
sahilmgandhi	18:6a4db94011d3	759	* \name Internal 32KHz Oscillator Management
sahilmgandhi	18:6a4db94011d3	760	* @{
sahilmgandhi	18:6a4db94011d3	761	*/
sahilmgandhi	18:6a4db94011d3	762
sahilmgandhi	18:6a4db94011d3	763	/**
sahilmgandhi	18:6a4db94011d3	764	* \brief Retrieve the default configuration for OSC32K.
sahilmgandhi	18:6a4db94011d3	765	*
sahilmgandhi	18:6a4db94011d3	766	* Fills a configuration structure with the default configuration for an
sahilmgandhi	18:6a4db94011d3	767	* internal 32KHz oscillator module:
sahilmgandhi	18:6a4db94011d3	768	* - 1KHz clock output enabled
sahilmgandhi	18:6a4db94011d3	769	* - 32KHz clock output enabled
sahilmgandhi	18:6a4db94011d3	770	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	771	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	772	* - Set startup time to 130 cycles
sahilmgandhi	18:6a4db94011d3	773	* - Don't lock registers after configuration has been written
sahilmgandhi	18:6a4db94011d3	774	*
sahilmgandhi	18:6a4db94011d3	775	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	776	*/
sahilmgandhi	18:6a4db94011d3	777	static inline void system_clock_source_osc32k_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	778	struct system_clock_source_osc32k_config *const config)
sahilmgandhi	18:6a4db94011d3	779	{
sahilmgandhi	18:6a4db94011d3	780	Assert(config);
sahilmgandhi	18:6a4db94011d3	781
sahilmgandhi	18:6a4db94011d3	782	config->enable_1khz_output = true;
sahilmgandhi	18:6a4db94011d3	783	config->enable_32khz_output = true;
sahilmgandhi	18:6a4db94011d3	784	config->run_in_standby = false;
sahilmgandhi	18:6a4db94011d3	785	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	786	config->startup_time = SYSTEM_OSC32K_STARTUP_130;
sahilmgandhi	18:6a4db94011d3	787	config->write_once = false;
sahilmgandhi	18:6a4db94011d3	788	}
sahilmgandhi	18:6a4db94011d3	789
sahilmgandhi	18:6a4db94011d3	790	void system_clock_source_osc32k_set_config(
sahilmgandhi	18:6a4db94011d3	791	struct system_clock_source_osc32k_config *const config);
sahilmgandhi	18:6a4db94011d3	792
sahilmgandhi	18:6a4db94011d3	793	/**
sahilmgandhi	18:6a4db94011d3	794	* @}
sahilmgandhi	18:6a4db94011d3	795	*/
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797
sahilmgandhi	18:6a4db94011d3	798	/**
sahilmgandhi	18:6a4db94011d3	799	* \name Internal 8MHz Oscillator Management
sahilmgandhi	18:6a4db94011d3	800	* @{
sahilmgandhi	18:6a4db94011d3	801	*/
sahilmgandhi	18:6a4db94011d3	802
sahilmgandhi	18:6a4db94011d3	803	/**
sahilmgandhi	18:6a4db94011d3	804	* \brief Retrieve the default configuration for OSC8M.
sahilmgandhi	18:6a4db94011d3	805	*
sahilmgandhi	18:6a4db94011d3	806	* Fills a configuration structure with the default configuration for an
sahilmgandhi	18:6a4db94011d3	807	* internal 8MHz (nominal) oscillator module:
sahilmgandhi	18:6a4db94011d3	808	* - Clock output frequency divided by a factor of eight
sahilmgandhi	18:6a4db94011d3	809	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	810	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	811	*
sahilmgandhi	18:6a4db94011d3	812	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	813	*/
sahilmgandhi	18:6a4db94011d3	814	static inline void system_clock_source_osc8m_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	815	struct system_clock_source_osc8m_config *const config)
sahilmgandhi	18:6a4db94011d3	816	{
sahilmgandhi	18:6a4db94011d3	817	Assert(config);
sahilmgandhi	18:6a4db94011d3	818
sahilmgandhi	18:6a4db94011d3	819	config->prescaler = SYSTEM_OSC8M_DIV_8;
sahilmgandhi	18:6a4db94011d3	820	config->run_in_standby = false;
sahilmgandhi	18:6a4db94011d3	821	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	822	}
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824	void system_clock_source_osc8m_set_config(
sahilmgandhi	18:6a4db94011d3	825	struct system_clock_source_osc8m_config *const config);
sahilmgandhi	18:6a4db94011d3	826
sahilmgandhi	18:6a4db94011d3	827	/**
sahilmgandhi	18:6a4db94011d3	828	* @}
sahilmgandhi	18:6a4db94011d3	829	*/
sahilmgandhi	18:6a4db94011d3	830
sahilmgandhi	18:6a4db94011d3	831
sahilmgandhi	18:6a4db94011d3	832	/**
sahilmgandhi	18:6a4db94011d3	833	* \name Internal DFLL Management
sahilmgandhi	18:6a4db94011d3	834	* @{
sahilmgandhi	18:6a4db94011d3	835	*/
sahilmgandhi	18:6a4db94011d3	836
sahilmgandhi	18:6a4db94011d3	837	/**
sahilmgandhi	18:6a4db94011d3	838	* \brief Retrieve the default configuration for DFLL.
sahilmgandhi	18:6a4db94011d3	839	*
sahilmgandhi	18:6a4db94011d3	840	* Fills a configuration structure with the default configuration for a
sahilmgandhi	18:6a4db94011d3	841	* DFLL oscillator module:
sahilmgandhi	18:6a4db94011d3	842	* - Open loop mode
sahilmgandhi	18:6a4db94011d3	843	* - QuickLock mode enabled
sahilmgandhi	18:6a4db94011d3	844	* - Chill cycle enabled
sahilmgandhi	18:6a4db94011d3	845	* - Output frequency lock maintained during device wake-up
sahilmgandhi	18:6a4db94011d3	846	* - Continuous tracking of the output frequency
sahilmgandhi	18:6a4db94011d3	847	* - Default tracking values at the mid-points for both coarse and fine
sahilmgandhi	18:6a4db94011d3	848	* tracking parameters
sahilmgandhi	18:6a4db94011d3	849	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	850	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	851	*
sahilmgandhi	18:6a4db94011d3	852	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	853	*/
sahilmgandhi	18:6a4db94011d3	854	static inline void system_clock_source_dfll_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	855	struct system_clock_source_dfll_config *const config)
sahilmgandhi	18:6a4db94011d3	856	{
sahilmgandhi	18:6a4db94011d3	857	Assert(config);
sahilmgandhi	18:6a4db94011d3	858
sahilmgandhi	18:6a4db94011d3	859	config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
sahilmgandhi	18:6a4db94011d3	860	config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
sahilmgandhi	18:6a4db94011d3	861	config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
sahilmgandhi	18:6a4db94011d3	862	config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
sahilmgandhi	18:6a4db94011d3	863	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
sahilmgandhi	18:6a4db94011d3	864	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	865
sahilmgandhi	18:6a4db94011d3	866	/* Open loop mode calibration value */
sahilmgandhi	18:6a4db94011d3	867	config->coarse_value = 0x1f / 4; /* Midpoint */
sahilmgandhi	18:6a4db94011d3	868	config->fine_value = 0xff / 4; /* Midpoint */
sahilmgandhi	18:6a4db94011d3	869
sahilmgandhi	18:6a4db94011d3	870	/* Closed loop mode */
sahilmgandhi	18:6a4db94011d3	871	config->coarse_max_step = 1;
sahilmgandhi	18:6a4db94011d3	872	config->fine_max_step = 1;
sahilmgandhi	18:6a4db94011d3	873	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
sahilmgandhi	18:6a4db94011d3	874	}
sahilmgandhi	18:6a4db94011d3	875
sahilmgandhi	18:6a4db94011d3	876	void system_clock_source_dfll_set_config(
sahilmgandhi	18:6a4db94011d3	877	struct system_clock_source_dfll_config *const config);
sahilmgandhi	18:6a4db94011d3	878
sahilmgandhi	18:6a4db94011d3	879	/**
sahilmgandhi	18:6a4db94011d3	880	* @}
sahilmgandhi	18:6a4db94011d3	881	*/
sahilmgandhi	18:6a4db94011d3	882
sahilmgandhi	18:6a4db94011d3	883	/**
sahilmgandhi	18:6a4db94011d3	884	* \name Clock Source Management
sahilmgandhi	18:6a4db94011d3	885	* @{
sahilmgandhi	18:6a4db94011d3	886	*/
sahilmgandhi	18:6a4db94011d3	887	enum status_code system_clock_source_write_calibration(
sahilmgandhi	18:6a4db94011d3	888	const enum system_clock_source system_clock_source,
sahilmgandhi	18:6a4db94011d3	889	const uint16_t calibration_value,
sahilmgandhi	18:6a4db94011d3	890	const uint8_t freq_range);
sahilmgandhi	18:6a4db94011d3	891
sahilmgandhi	18:6a4db94011d3	892	enum status_code system_clock_source_enable(
sahilmgandhi	18:6a4db94011d3	893	const enum system_clock_source system_clock_source);
sahilmgandhi	18:6a4db94011d3	894
sahilmgandhi	18:6a4db94011d3	895	enum status_code system_clock_source_disable(
sahilmgandhi	18:6a4db94011d3	896	const enum system_clock_source clk_source);
sahilmgandhi	18:6a4db94011d3	897
sahilmgandhi	18:6a4db94011d3	898	bool system_clock_source_is_ready(
sahilmgandhi	18:6a4db94011d3	899	const enum system_clock_source clk_source);
sahilmgandhi	18:6a4db94011d3	900
sahilmgandhi	18:6a4db94011d3	901	uint32_t system_clock_source_get_hz(
sahilmgandhi	18:6a4db94011d3	902	const enum system_clock_source clk_source);
sahilmgandhi	18:6a4db94011d3	903
sahilmgandhi	18:6a4db94011d3	904	/**
sahilmgandhi	18:6a4db94011d3	905	* @}
sahilmgandhi	18:6a4db94011d3	906	*/
sahilmgandhi	18:6a4db94011d3	907
sahilmgandhi	18:6a4db94011d3	908	/**
sahilmgandhi	18:6a4db94011d3	909	* \name Main Clock Management
sahilmgandhi	18:6a4db94011d3	910	* @{
sahilmgandhi	18:6a4db94011d3	911	*/
sahilmgandhi	18:6a4db94011d3	912
sahilmgandhi	18:6a4db94011d3	913	/**
sahilmgandhi	18:6a4db94011d3	914	* \brief Set main CPU clock divider.
sahilmgandhi	18:6a4db94011d3	915	*
sahilmgandhi	18:6a4db94011d3	916	* Sets the clock divider used on the main clock to provide the CPU clock.
sahilmgandhi	18:6a4db94011d3	917	*
sahilmgandhi	18:6a4db94011d3	918	* \param[in] divider CPU clock divider to set
sahilmgandhi	18:6a4db94011d3	919	*/
sahilmgandhi	18:6a4db94011d3	920	static inline void system_cpu_clock_set_divider(
sahilmgandhi	18:6a4db94011d3	921	const enum system_main_clock_div divider)
sahilmgandhi	18:6a4db94011d3	922	{
sahilmgandhi	18:6a4db94011d3	923	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
sahilmgandhi	18:6a4db94011d3	924	PM->CPUSEL.reg = (uint32_t)divider;
sahilmgandhi	18:6a4db94011d3	925	}
sahilmgandhi	18:6a4db94011d3	926
sahilmgandhi	18:6a4db94011d3	927	/**
sahilmgandhi	18:6a4db94011d3	928	* \brief Retrieves the current frequency of the CPU core.
sahilmgandhi	18:6a4db94011d3	929	*
sahilmgandhi	18:6a4db94011d3	930	* Retrieves the operating frequency of the CPU core, obtained from the main
sahilmgandhi	18:6a4db94011d3	931	* generic clock and the set CPU bus divider.
sahilmgandhi	18:6a4db94011d3	932	*
sahilmgandhi	18:6a4db94011d3	933	* \return Current CPU frequency in Hz.
sahilmgandhi	18:6a4db94011d3	934	*/
sahilmgandhi	18:6a4db94011d3	935	static inline uint32_t system_cpu_clock_get_hz(void)
sahilmgandhi	18:6a4db94011d3	936	{
sahilmgandhi	18:6a4db94011d3	937	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
sahilmgandhi	18:6a4db94011d3	938	}
sahilmgandhi	18:6a4db94011d3	939
sahilmgandhi	18:6a4db94011d3	940	/**
sahilmgandhi	18:6a4db94011d3	941	* \brief Set APBx clock divider.
sahilmgandhi	18:6a4db94011d3	942	*
sahilmgandhi	18:6a4db94011d3	943	* Set the clock divider used on the main clock to provide the clock for the
sahilmgandhi	18:6a4db94011d3	944	* given APBx bus.
sahilmgandhi	18:6a4db94011d3	945	*
sahilmgandhi	18:6a4db94011d3	946	* \param[in] divider APBx bus divider to set
sahilmgandhi	18:6a4db94011d3	947	* \param[in] bus APBx bus to set divider
sahilmgandhi	18:6a4db94011d3	948	*
sahilmgandhi	18:6a4db94011d3	949	* \returns Status of the clock division change operation.
sahilmgandhi	18:6a4db94011d3	950	*
sahilmgandhi	18:6a4db94011d3	951	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
sahilmgandhi	18:6a4db94011d3	952	* \retval STATUS_OK The APBx clock was set successfully
sahilmgandhi	18:6a4db94011d3	953	*/
sahilmgandhi	18:6a4db94011d3	954	static inline enum status_code system_apb_clock_set_divider(
sahilmgandhi	18:6a4db94011d3	955	const enum system_clock_apb_bus bus,
sahilmgandhi	18:6a4db94011d3	956	const enum system_main_clock_div divider)
sahilmgandhi	18:6a4db94011d3	957	{
sahilmgandhi	18:6a4db94011d3	958	switch (bus) {
sahilmgandhi	18:6a4db94011d3	959	case SYSTEM_CLOCK_APB_APBA:
sahilmgandhi	18:6a4db94011d3	960	PM->APBASEL.reg = (uint32_t)divider;
sahilmgandhi	18:6a4db94011d3	961	break;
sahilmgandhi	18:6a4db94011d3	962	case SYSTEM_CLOCK_APB_APBB:
sahilmgandhi	18:6a4db94011d3	963	PM->APBBSEL.reg = (uint32_t)divider;
sahilmgandhi	18:6a4db94011d3	964	break;
sahilmgandhi	18:6a4db94011d3	965	case SYSTEM_CLOCK_APB_APBC:
sahilmgandhi	18:6a4db94011d3	966	PM->APBCSEL.reg = (uint32_t)divider;
sahilmgandhi	18:6a4db94011d3	967	break;
sahilmgandhi	18:6a4db94011d3	968	default:
sahilmgandhi	18:6a4db94011d3	969	Assert(false);
sahilmgandhi	18:6a4db94011d3	970	return STATUS_ERR_INVALID_ARG;
sahilmgandhi	18:6a4db94011d3	971	}
sahilmgandhi	18:6a4db94011d3	972
sahilmgandhi	18:6a4db94011d3	973	return STATUS_OK;
sahilmgandhi	18:6a4db94011d3	974	}
sahilmgandhi	18:6a4db94011d3	975
sahilmgandhi	18:6a4db94011d3	976	/**
sahilmgandhi	18:6a4db94011d3	977	* \brief Retrieves the current frequency of a ABPx.
sahilmgandhi	18:6a4db94011d3	978	*
sahilmgandhi	18:6a4db94011d3	979	* Retrieves the operating frequency of an APBx bus, obtained from the main
sahilmgandhi	18:6a4db94011d3	980	* generic clock and the set APBx bus divider.
sahilmgandhi	18:6a4db94011d3	981	*
sahilmgandhi	18:6a4db94011d3	982	* \return Current APBx bus frequency in Hz.
sahilmgandhi	18:6a4db94011d3	983	*/
sahilmgandhi	18:6a4db94011d3	984	static inline uint32_t system_apb_clock_get_hz(
sahilmgandhi	18:6a4db94011d3	985	const enum system_clock_apb_bus bus)
sahilmgandhi	18:6a4db94011d3	986	{
sahilmgandhi	18:6a4db94011d3	987	uint16_t bus_divider = 0;
sahilmgandhi	18:6a4db94011d3	988
sahilmgandhi	18:6a4db94011d3	989	switch (bus) {
sahilmgandhi	18:6a4db94011d3	990	case SYSTEM_CLOCK_APB_APBA:
sahilmgandhi	18:6a4db94011d3	991	bus_divider = PM->APBASEL.reg;
sahilmgandhi	18:6a4db94011d3	992	break;
sahilmgandhi	18:6a4db94011d3	993	case SYSTEM_CLOCK_APB_APBB:
sahilmgandhi	18:6a4db94011d3	994	bus_divider = PM->APBBSEL.reg;
sahilmgandhi	18:6a4db94011d3	995	break;
sahilmgandhi	18:6a4db94011d3	996	case SYSTEM_CLOCK_APB_APBC:
sahilmgandhi	18:6a4db94011d3	997	bus_divider = PM->APBCSEL.reg;
sahilmgandhi	18:6a4db94011d3	998	break;
sahilmgandhi	18:6a4db94011d3	999	default:
sahilmgandhi	18:6a4db94011d3	1000	Assert(false);
sahilmgandhi	18:6a4db94011d3	1001	return 0;
sahilmgandhi	18:6a4db94011d3	1002	}
sahilmgandhi	18:6a4db94011d3	1003
sahilmgandhi	18:6a4db94011d3	1004	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
sahilmgandhi	18:6a4db94011d3	1005	}
sahilmgandhi	18:6a4db94011d3	1006
sahilmgandhi	18:6a4db94011d3	1007
sahilmgandhi	18:6a4db94011d3	1008	/**
sahilmgandhi	18:6a4db94011d3	1009	* @}
sahilmgandhi	18:6a4db94011d3	1010	*/
sahilmgandhi	18:6a4db94011d3	1011
sahilmgandhi	18:6a4db94011d3	1012	/**
sahilmgandhi	18:6a4db94011d3	1013	* \name Bus Clock Masking
sahilmgandhi	18:6a4db94011d3	1014	* @{
sahilmgandhi	18:6a4db94011d3	1015	*/
sahilmgandhi	18:6a4db94011d3	1016
sahilmgandhi	18:6a4db94011d3	1017	/**
sahilmgandhi	18:6a4db94011d3	1018	* \brief Set bits in the clock mask for the AHB bus.
sahilmgandhi	18:6a4db94011d3	1019	*
sahilmgandhi	18:6a4db94011d3	1020	* This function will set bits in the clock mask for the AHB bus.
sahilmgandhi	18:6a4db94011d3	1021	* Any bits set to 1 will enable that clock, 0 bits in the mask
sahilmgandhi	18:6a4db94011d3	1022	* will be ignored.
sahilmgandhi	18:6a4db94011d3	1023	*
sahilmgandhi	18:6a4db94011d3	1024	* \param[in] ahb_mask AHB clock mask to enable
sahilmgandhi	18:6a4db94011d3	1025	*/
sahilmgandhi	18:6a4db94011d3	1026	static inline void system_ahb_clock_set_mask(
sahilmgandhi	18:6a4db94011d3	1027	const uint32_t ahb_mask)
sahilmgandhi	18:6a4db94011d3	1028	{
sahilmgandhi	18:6a4db94011d3	1029	PM->AHBMASK.reg \|= ahb_mask;
sahilmgandhi	18:6a4db94011d3	1030	}
sahilmgandhi	18:6a4db94011d3	1031
sahilmgandhi	18:6a4db94011d3	1032	/**
sahilmgandhi	18:6a4db94011d3	1033	* \brief Clear bits in the clock mask for the AHB bus.
sahilmgandhi	18:6a4db94011d3	1034	*
sahilmgandhi	18:6a4db94011d3	1035	* This function will clear bits in the clock mask for the AHB bus.
sahilmgandhi	18:6a4db94011d3	1036	* Any bits set to 1 will disable that clock, 0 bits in the mask
sahilmgandhi	18:6a4db94011d3	1037	* will be ignored.
sahilmgandhi	18:6a4db94011d3	1038	*
sahilmgandhi	18:6a4db94011d3	1039	* \param[in] ahb_mask AHB clock mask to disable
sahilmgandhi	18:6a4db94011d3	1040	*/
sahilmgandhi	18:6a4db94011d3	1041	static inline void system_ahb_clock_clear_mask(
sahilmgandhi	18:6a4db94011d3	1042	const uint32_t ahb_mask)
sahilmgandhi	18:6a4db94011d3	1043	{
sahilmgandhi	18:6a4db94011d3	1044	PM->AHBMASK.reg &= ~ahb_mask;
sahilmgandhi	18:6a4db94011d3	1045	}
sahilmgandhi	18:6a4db94011d3	1046
sahilmgandhi	18:6a4db94011d3	1047	/**
sahilmgandhi	18:6a4db94011d3	1048	* \brief Set bits in the clock mask for an APBx bus.
sahilmgandhi	18:6a4db94011d3	1049	*
sahilmgandhi	18:6a4db94011d3	1050	* This function will set bits in the clock mask for an APBx bus.
sahilmgandhi	18:6a4db94011d3	1051	* Any bits set to 1 will enable the corresponding module clock, zero bits in
sahilmgandhi	18:6a4db94011d3	1052	* the mask will be ignored.
sahilmgandhi	18:6a4db94011d3	1053	*
sahilmgandhi	18:6a4db94011d3	1054	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
sahilmgandhi	18:6a4db94011d3	1055	* the device header files
sahilmgandhi	18:6a4db94011d3	1056	* \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
sahilmgandhi	18:6a4db94011d3	1057	* constants from the device header files
sahilmgandhi	18:6a4db94011d3	1058	*
sahilmgandhi	18:6a4db94011d3	1059	* \returns Status indicating the result of the clock mask change operation.
sahilmgandhi	18:6a4db94011d3	1060	*
sahilmgandhi	18:6a4db94011d3	1061	* \retval STATUS_ERR_INVALID_ARG Invalid bus given
sahilmgandhi	18:6a4db94011d3	1062	* \retval STATUS_OK The clock mask was set successfully
sahilmgandhi	18:6a4db94011d3	1063	*/
sahilmgandhi	18:6a4db94011d3	1064	static inline enum status_code system_apb_clock_set_mask(
sahilmgandhi	18:6a4db94011d3	1065	const enum system_clock_apb_bus bus,
sahilmgandhi	18:6a4db94011d3	1066	const uint32_t mask)
sahilmgandhi	18:6a4db94011d3	1067	{
sahilmgandhi	18:6a4db94011d3	1068	switch (bus) {
sahilmgandhi	18:6a4db94011d3	1069	case SYSTEM_CLOCK_APB_APBA:
sahilmgandhi	18:6a4db94011d3	1070	PM->APBAMASK.reg \|= mask;
sahilmgandhi	18:6a4db94011d3	1071	break;
sahilmgandhi	18:6a4db94011d3	1072
sahilmgandhi	18:6a4db94011d3	1073	case SYSTEM_CLOCK_APB_APBB:
sahilmgandhi	18:6a4db94011d3	1074	PM->APBBMASK.reg \|= mask;
sahilmgandhi	18:6a4db94011d3	1075	break;
sahilmgandhi	18:6a4db94011d3	1076
sahilmgandhi	18:6a4db94011d3	1077	case SYSTEM_CLOCK_APB_APBC:
sahilmgandhi	18:6a4db94011d3	1078	PM->APBCMASK.reg \|= mask;
sahilmgandhi	18:6a4db94011d3	1079	break;
sahilmgandhi	18:6a4db94011d3	1080
sahilmgandhi	18:6a4db94011d3	1081	default:
sahilmgandhi	18:6a4db94011d3	1082	Assert(false);
sahilmgandhi	18:6a4db94011d3	1083	return STATUS_ERR_INVALID_ARG;
sahilmgandhi	18:6a4db94011d3	1084
sahilmgandhi	18:6a4db94011d3	1085	}
sahilmgandhi	18:6a4db94011d3	1086
sahilmgandhi	18:6a4db94011d3	1087	return STATUS_OK;
sahilmgandhi	18:6a4db94011d3	1088	}
sahilmgandhi	18:6a4db94011d3	1089
sahilmgandhi	18:6a4db94011d3	1090	/**
sahilmgandhi	18:6a4db94011d3	1091	* \brief Clear bits in the clock mask for an APBx bus.
sahilmgandhi	18:6a4db94011d3	1092	*
sahilmgandhi	18:6a4db94011d3	1093	* This function will clear bits in the clock mask for an APBx bus.
sahilmgandhi	18:6a4db94011d3	1094	* Any bits set to 1 will disable the corresponding module clock, zero bits in
sahilmgandhi	18:6a4db94011d3	1095	* the mask will be ignored.
sahilmgandhi	18:6a4db94011d3	1096	*
sahilmgandhi	18:6a4db94011d3	1097	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
sahilmgandhi	18:6a4db94011d3	1098	* the device header files
sahilmgandhi	18:6a4db94011d3	1099	* \param[in] bus Bus to clear clock mask bits
sahilmgandhi	18:6a4db94011d3	1100	*
sahilmgandhi	18:6a4db94011d3	1101	* \returns Status indicating the result of the clock mask change operation.
sahilmgandhi	18:6a4db94011d3	1102	*
sahilmgandhi	18:6a4db94011d3	1103	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
sahilmgandhi	18:6a4db94011d3	1104	* \retval STATUS_OK The clock mask was changed successfully
sahilmgandhi	18:6a4db94011d3	1105	*/
sahilmgandhi	18:6a4db94011d3	1106	static inline enum status_code system_apb_clock_clear_mask(
sahilmgandhi	18:6a4db94011d3	1107	const enum system_clock_apb_bus bus,
sahilmgandhi	18:6a4db94011d3	1108	const uint32_t mask)
sahilmgandhi	18:6a4db94011d3	1109	{
sahilmgandhi	18:6a4db94011d3	1110	switch (bus) {
sahilmgandhi	18:6a4db94011d3	1111	case SYSTEM_CLOCK_APB_APBA:
sahilmgandhi	18:6a4db94011d3	1112	PM->APBAMASK.reg &= ~mask;
sahilmgandhi	18:6a4db94011d3	1113	break;
sahilmgandhi	18:6a4db94011d3	1114
sahilmgandhi	18:6a4db94011d3	1115	case SYSTEM_CLOCK_APB_APBB:
sahilmgandhi	18:6a4db94011d3	1116	PM->APBBMASK.reg &= ~mask;
sahilmgandhi	18:6a4db94011d3	1117	break;
sahilmgandhi	18:6a4db94011d3	1118
sahilmgandhi	18:6a4db94011d3	1119	case SYSTEM_CLOCK_APB_APBC:
sahilmgandhi	18:6a4db94011d3	1120	PM->APBCMASK.reg &= ~mask;
sahilmgandhi	18:6a4db94011d3	1121	break;
sahilmgandhi	18:6a4db94011d3	1122
sahilmgandhi	18:6a4db94011d3	1123	default:
sahilmgandhi	18:6a4db94011d3	1124	Assert(false);
sahilmgandhi	18:6a4db94011d3	1125	return STATUS_ERR_INVALID_ARG;
sahilmgandhi	18:6a4db94011d3	1126	}
sahilmgandhi	18:6a4db94011d3	1127
sahilmgandhi	18:6a4db94011d3	1128	return STATUS_OK;
sahilmgandhi	18:6a4db94011d3	1129	}
sahilmgandhi	18:6a4db94011d3	1130
sahilmgandhi	18:6a4db94011d3	1131	/**
sahilmgandhi	18:6a4db94011d3	1132	* @}
sahilmgandhi	18:6a4db94011d3	1133	*/
sahilmgandhi	18:6a4db94011d3	1134
sahilmgandhi	18:6a4db94011d3	1135	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
sahilmgandhi	18:6a4db94011d3	1136	/**
sahilmgandhi	18:6a4db94011d3	1137	* \brief Reference clock source of the DPLL module.
sahilmgandhi	18:6a4db94011d3	1138	*/
sahilmgandhi	18:6a4db94011d3	1139	enum system_clock_source_dpll_reference_clock {
sahilmgandhi	18:6a4db94011d3	1140	/** Select XOSC32K as clock reference. */
sahilmgandhi	18:6a4db94011d3	1141	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
sahilmgandhi	18:6a4db94011d3	1142	/** Select XOSC as clock reference. */
sahilmgandhi	18:6a4db94011d3	1143	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
sahilmgandhi	18:6a4db94011d3	1144	/** Select GCLK as clock reference. */
sahilmgandhi	18:6a4db94011d3	1145	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
sahilmgandhi	18:6a4db94011d3	1146	};
sahilmgandhi	18:6a4db94011d3	1147
sahilmgandhi	18:6a4db94011d3	1148	/**
sahilmgandhi	18:6a4db94011d3	1149	* \brief Lock time-out value of the DPLL module.
sahilmgandhi	18:6a4db94011d3	1150	*/
sahilmgandhi	18:6a4db94011d3	1151	enum system_clock_source_dpll_lock_time {
sahilmgandhi	18:6a4db94011d3	1152	/** Set no time-out as default. */
sahilmgandhi	18:6a4db94011d3	1153	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
sahilmgandhi	18:6a4db94011d3	1154	/** Set time-out if no lock within 8ms. */
sahilmgandhi	18:6a4db94011d3	1155	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
sahilmgandhi	18:6a4db94011d3	1156	/** Set time-out if no lock within 9ms. */
sahilmgandhi	18:6a4db94011d3	1157	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
sahilmgandhi	18:6a4db94011d3	1158	/** Set time-out if no lock within 10ms. */
sahilmgandhi	18:6a4db94011d3	1159	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
sahilmgandhi	18:6a4db94011d3	1160	/** Set time-out if no lock within 11ms. */
sahilmgandhi	18:6a4db94011d3	1161	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
sahilmgandhi	18:6a4db94011d3	1162	};
sahilmgandhi	18:6a4db94011d3	1163
sahilmgandhi	18:6a4db94011d3	1164	/**
sahilmgandhi	18:6a4db94011d3	1165	* \brief Filter type of the DPLL module.
sahilmgandhi	18:6a4db94011d3	1166	*/
sahilmgandhi	18:6a4db94011d3	1167	enum system_clock_source_dpll_filter {
sahilmgandhi	18:6a4db94011d3	1168	/** Default filter mode. */
sahilmgandhi	18:6a4db94011d3	1169	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
sahilmgandhi	18:6a4db94011d3	1170	/** Low bandwidth filter. */
sahilmgandhi	18:6a4db94011d3	1171	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
sahilmgandhi	18:6a4db94011d3	1172	/** High bandwidth filter. */
sahilmgandhi	18:6a4db94011d3	1173	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
sahilmgandhi	18:6a4db94011d3	1174	/** High damping filter. */
sahilmgandhi	18:6a4db94011d3	1175	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
sahilmgandhi	18:6a4db94011d3	1176	};
sahilmgandhi	18:6a4db94011d3	1177
sahilmgandhi	18:6a4db94011d3	1178	/**
sahilmgandhi	18:6a4db94011d3	1179	* \brief Configuration structure for DPLL.
sahilmgandhi	18:6a4db94011d3	1180	*
sahilmgandhi	18:6a4db94011d3	1181	* DPLL oscillator configuration structure.
sahilmgandhi	18:6a4db94011d3	1182	*/
sahilmgandhi	18:6a4db94011d3	1183	struct system_clock_source_dpll_config {
sahilmgandhi	18:6a4db94011d3	1184	/** Run On Demand. If this is set the DPLL won't run
sahilmgandhi	18:6a4db94011d3	1185	* until requested by a peripheral. */
sahilmgandhi	18:6a4db94011d3	1186	bool on_demand;
sahilmgandhi	18:6a4db94011d3	1187	/** Keep the DPLL enabled in standby sleep mode. */
sahilmgandhi	18:6a4db94011d3	1188	bool run_in_standby;
sahilmgandhi	18:6a4db94011d3	1189	/** Bypass lock signal. */
sahilmgandhi	18:6a4db94011d3	1190	bool lock_bypass;
sahilmgandhi	18:6a4db94011d3	1191	/** Wake up fast. If this is set DPLL output clock is enabled after
sahilmgandhi	18:6a4db94011d3	1192	* the startup time. */
sahilmgandhi	18:6a4db94011d3	1193	bool wake_up_fast;
sahilmgandhi	18:6a4db94011d3	1194	/** Enable low power mode. */
sahilmgandhi	18:6a4db94011d3	1195	bool low_power_enable;
sahilmgandhi	18:6a4db94011d3	1196
sahilmgandhi	18:6a4db94011d3	1197	/** Output frequency of the clock. */
sahilmgandhi	18:6a4db94011d3	1198	uint32_t output_frequency;
sahilmgandhi	18:6a4db94011d3	1199	/** Reference frequency of the clock. */
sahilmgandhi	18:6a4db94011d3	1200	uint32_t reference_frequency;
sahilmgandhi	18:6a4db94011d3	1201	/** Devider of reference clock. */
sahilmgandhi	18:6a4db94011d3	1202	uint16_t reference_divider;
sahilmgandhi	18:6a4db94011d3	1203
sahilmgandhi	18:6a4db94011d3	1204	/** Filter type of the DPLL module. */
sahilmgandhi	18:6a4db94011d3	1205	enum system_clock_source_dpll_filter filter;
sahilmgandhi	18:6a4db94011d3	1206	/** Lock time-out value of the DPLL module. */
sahilmgandhi	18:6a4db94011d3	1207	enum system_clock_source_dpll_lock_time lock_time;
sahilmgandhi	18:6a4db94011d3	1208	/** Reference clock source of the DPLL module. */
sahilmgandhi	18:6a4db94011d3	1209	enum system_clock_source_dpll_reference_clock reference_clock;
sahilmgandhi	18:6a4db94011d3	1210	};
sahilmgandhi	18:6a4db94011d3	1211
sahilmgandhi	18:6a4db94011d3	1212	/**
sahilmgandhi	18:6a4db94011d3	1213	* \name Internal DPLL Management
sahilmgandhi	18:6a4db94011d3	1214	* @{
sahilmgandhi	18:6a4db94011d3	1215	*/
sahilmgandhi	18:6a4db94011d3	1216
sahilmgandhi	18:6a4db94011d3	1217	/**
sahilmgandhi	18:6a4db94011d3	1218	* \brief Retrieve the default configuration for DPLL.
sahilmgandhi	18:6a4db94011d3	1219	*
sahilmgandhi	18:6a4db94011d3	1220	* Fills a configuration structure with the default configuration for a
sahilmgandhi	18:6a4db94011d3	1221	* DPLL oscillator module:
sahilmgandhi	18:6a4db94011d3	1222	* - Run only when requested by peripheral (on demand)
sahilmgandhi	18:6a4db94011d3	1223	* - Don't run in STANDBY sleep mode
sahilmgandhi	18:6a4db94011d3	1224	* - Lock bypass disabled
sahilmgandhi	18:6a4db94011d3	1225	* - Fast wake up disabled
sahilmgandhi	18:6a4db94011d3	1226	* - Low power mode disabled
sahilmgandhi	18:6a4db94011d3	1227	* - Output frequency is 48MHz
sahilmgandhi	18:6a4db94011d3	1228	* - Reference clock frequency is 32768Hz
sahilmgandhi	18:6a4db94011d3	1229	* - Not divide reference clock
sahilmgandhi	18:6a4db94011d3	1230	* - Select REF0 as reference clock
sahilmgandhi	18:6a4db94011d3	1231	* - Set lock time to default mode
sahilmgandhi	18:6a4db94011d3	1232	* - Use default filter
sahilmgandhi	18:6a4db94011d3	1233	*
sahilmgandhi	18:6a4db94011d3	1234	* \param[out] config Configuration structure to fill with default values
sahilmgandhi	18:6a4db94011d3	1235	*/
sahilmgandhi	18:6a4db94011d3	1236	static inline void system_clock_source_dpll_get_config_defaults(
sahilmgandhi	18:6a4db94011d3	1237	struct system_clock_source_dpll_config *const config)
sahilmgandhi	18:6a4db94011d3	1238	{
sahilmgandhi	18:6a4db94011d3	1239	config->on_demand = true;
sahilmgandhi	18:6a4db94011d3	1240	config->run_in_standby = false;
sahilmgandhi	18:6a4db94011d3	1241	config->lock_bypass = false;
sahilmgandhi	18:6a4db94011d3	1242	config->wake_up_fast = false;
sahilmgandhi	18:6a4db94011d3	1243	config->low_power_enable = false;
sahilmgandhi	18:6a4db94011d3	1244
sahilmgandhi	18:6a4db94011d3	1245	config->output_frequency = 48000000;
sahilmgandhi	18:6a4db94011d3	1246	config->reference_frequency = 32768;
sahilmgandhi	18:6a4db94011d3	1247	config->reference_divider = 1;
sahilmgandhi	18:6a4db94011d3	1248	config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
sahilmgandhi	18:6a4db94011d3	1249
sahilmgandhi	18:6a4db94011d3	1250	config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
sahilmgandhi	18:6a4db94011d3	1251	config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
sahilmgandhi	18:6a4db94011d3	1252	};
sahilmgandhi	18:6a4db94011d3	1253
sahilmgandhi	18:6a4db94011d3	1254	void system_clock_source_dpll_set_config(
sahilmgandhi	18:6a4db94011d3	1255	struct system_clock_source_dpll_config *const config);
sahilmgandhi	18:6a4db94011d3	1256
sahilmgandhi	18:6a4db94011d3	1257	/* @} */
sahilmgandhi	18:6a4db94011d3	1258	#endif
sahilmgandhi	18:6a4db94011d3	1259
sahilmgandhi	18:6a4db94011d3	1260	/**
sahilmgandhi	18:6a4db94011d3	1261	* \name System Clock Initialization
sahilmgandhi	18:6a4db94011d3	1262	* @{
sahilmgandhi	18:6a4db94011d3	1263	*/
sahilmgandhi	18:6a4db94011d3	1264
sahilmgandhi	18:6a4db94011d3	1265	void system_clock_init(void);
sahilmgandhi	18:6a4db94011d3	1266
sahilmgandhi	18:6a4db94011d3	1267	/**
sahilmgandhi	18:6a4db94011d3	1268	* @}
sahilmgandhi	18:6a4db94011d3	1269	*/
sahilmgandhi	18:6a4db94011d3	1270
sahilmgandhi	18:6a4db94011d3	1271	/**
sahilmgandhi	18:6a4db94011d3	1272	* \name System Flash Wait States
sahilmgandhi	18:6a4db94011d3	1273	* @{
sahilmgandhi	18:6a4db94011d3	1274	*/
sahilmgandhi	18:6a4db94011d3	1275
sahilmgandhi	18:6a4db94011d3	1276	/**
sahilmgandhi	18:6a4db94011d3	1277	* \brief Set flash controller wait states.
sahilmgandhi	18:6a4db94011d3	1278	*
sahilmgandhi	18:6a4db94011d3	1279	* Will set the number of wait states that are used by the onboard
sahilmgandhi	18:6a4db94011d3	1280	* flash memory. The number of wait states depend on both device
sahilmgandhi	18:6a4db94011d3	1281	* supply voltage and CPU speed. The required number of wait states
sahilmgandhi	18:6a4db94011d3	1282	* can be found in the electrical characteristics of the device.
sahilmgandhi	18:6a4db94011d3	1283	*
sahilmgandhi	18:6a4db94011d3	1284	* \param[in] wait_states Number of wait states to use for internal flash
sahilmgandhi	18:6a4db94011d3	1285	*/
sahilmgandhi	18:6a4db94011d3	1286	static inline void system_flash_set_waitstates(uint8_t wait_states)
sahilmgandhi	18:6a4db94011d3	1287	{
sahilmgandhi	18:6a4db94011d3	1288	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
sahilmgandhi	18:6a4db94011d3	1289	((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
sahilmgandhi	18:6a4db94011d3	1290
sahilmgandhi	18:6a4db94011d3	1291	NVMCTRL->CTRLB.bit.RWS = wait_states;
sahilmgandhi	18:6a4db94011d3	1292	}
sahilmgandhi	18:6a4db94011d3	1293	/**
sahilmgandhi	18:6a4db94011d3	1294	* @}
sahilmgandhi	18:6a4db94011d3	1295	*/
sahilmgandhi	18:6a4db94011d3	1296
sahilmgandhi	18:6a4db94011d3	1297	/**
sahilmgandhi	18:6a4db94011d3	1298	* @}
sahilmgandhi	18:6a4db94011d3	1299	*/
sahilmgandhi	18:6a4db94011d3	1300
sahilmgandhi	18:6a4db94011d3	1301	/**
sahilmgandhi	18:6a4db94011d3	1302	* \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
sahilmgandhi	18:6a4db94011d3	1303	*
sahilmgandhi	18:6a4db94011d3	1304	* \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
sahilmgandhi	18:6a4db94011d3	1305	* Below is a table listing the acronyms used in this module, along with their
sahilmgandhi	18:6a4db94011d3	1306	* intended meanings.
sahilmgandhi	18:6a4db94011d3	1307	*
sahilmgandhi	18:6a4db94011d3	1308	* <table>
sahilmgandhi	18:6a4db94011d3	1309	* <tr>
sahilmgandhi	18:6a4db94011d3	1310	* <th>Acronym</th>
sahilmgandhi	18:6a4db94011d3	1311	* <th>Description</th>
sahilmgandhi	18:6a4db94011d3	1312	* </tr>
sahilmgandhi	18:6a4db94011d3	1313	* <tr>
sahilmgandhi	18:6a4db94011d3	1314	* <td>DFLL</td>
sahilmgandhi	18:6a4db94011d3	1315	* <td>Digital Frequency Locked Loop</td>
sahilmgandhi	18:6a4db94011d3	1316	* </tr>
sahilmgandhi	18:6a4db94011d3	1317	* <tr>
sahilmgandhi	18:6a4db94011d3	1318	* <td>MUX</td>
sahilmgandhi	18:6a4db94011d3	1319	* <td>Multiplexer</td>
sahilmgandhi	18:6a4db94011d3	1320	* </tr>
sahilmgandhi	18:6a4db94011d3	1321	* <tr>
sahilmgandhi	18:6a4db94011d3	1322	* <td>OSC32K</td>
sahilmgandhi	18:6a4db94011d3	1323	* <td>Internal 32KHz Oscillator</td>
sahilmgandhi	18:6a4db94011d3	1324	* </tr>
sahilmgandhi	18:6a4db94011d3	1325	* <tr>
sahilmgandhi	18:6a4db94011d3	1326	* <td>OSC8M</td>
sahilmgandhi	18:6a4db94011d3	1327	* <td>Internal 8MHz Oscillator</td>
sahilmgandhi	18:6a4db94011d3	1328	* </tr>
sahilmgandhi	18:6a4db94011d3	1329	* <tr>
sahilmgandhi	18:6a4db94011d3	1330	* <td>PLL</td>
sahilmgandhi	18:6a4db94011d3	1331	* <td>Phase Locked Loop</td>
sahilmgandhi	18:6a4db94011d3	1332	* </tr>
sahilmgandhi	18:6a4db94011d3	1333	* <tr>
sahilmgandhi	18:6a4db94011d3	1334	* <td>OSC</td>
sahilmgandhi	18:6a4db94011d3	1335	* <td>Oscillator</td>
sahilmgandhi	18:6a4db94011d3	1336	* </tr>
sahilmgandhi	18:6a4db94011d3	1337	* <tr>
sahilmgandhi	18:6a4db94011d3	1338	* <td>XOSC</td>
sahilmgandhi	18:6a4db94011d3	1339	* <td>External Oscillator</td>
sahilmgandhi	18:6a4db94011d3	1340	* </tr>
sahilmgandhi	18:6a4db94011d3	1341	* <tr>
sahilmgandhi	18:6a4db94011d3	1342	* <td>XOSC32K</td>
sahilmgandhi	18:6a4db94011d3	1343	* <td>External 32KHz Oscillator</td>
sahilmgandhi	18:6a4db94011d3	1344	* </tr>
sahilmgandhi	18:6a4db94011d3	1345	* <tr>
sahilmgandhi	18:6a4db94011d3	1346	* <td>AHB</td>
sahilmgandhi	18:6a4db94011d3	1347	* <td>Advanced High-performance Bus</td>
sahilmgandhi	18:6a4db94011d3	1348	* </tr>
sahilmgandhi	18:6a4db94011d3	1349	* <tr>
sahilmgandhi	18:6a4db94011d3	1350	* <td>APB</td>
sahilmgandhi	18:6a4db94011d3	1351	* <td>Advanced Peripheral Bus</td>
sahilmgandhi	18:6a4db94011d3	1352	* </tr>
sahilmgandhi	18:6a4db94011d3	1353	* <tr>
sahilmgandhi	18:6a4db94011d3	1354	* <td>DPLL</td>
sahilmgandhi	18:6a4db94011d3	1355	* <td>Digital Phase Locked Loop</td>
sahilmgandhi	18:6a4db94011d3	1356	* </tr>
sahilmgandhi	18:6a4db94011d3	1357	* </table>
sahilmgandhi	18:6a4db94011d3	1358	*
sahilmgandhi	18:6a4db94011d3	1359	*
sahilmgandhi	18:6a4db94011d3	1360	* \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
sahilmgandhi	18:6a4db94011d3	1361	* This driver has the following dependencies:
sahilmgandhi	18:6a4db94011d3	1362	*
sahilmgandhi	18:6a4db94011d3	1363	* - None
sahilmgandhi	18:6a4db94011d3	1364	*
sahilmgandhi	18:6a4db94011d3	1365	*
sahilmgandhi	18:6a4db94011d3	1366	* \section asfdoc_sam0_system_clock_extra_errata Errata
sahilmgandhi	18:6a4db94011d3	1367	*
sahilmgandhi	18:6a4db94011d3	1368	* - This driver implements experimental workaround for errata 9905
sahilmgandhi	18:6a4db94011d3	1369	*
sahilmgandhi	18:6a4db94011d3	1370	* "The DFLL clock must be requested before being configured otherwise a
sahilmgandhi	18:6a4db94011d3	1371	* write access to a DFLL register can freeze the device."
sahilmgandhi	18:6a4db94011d3	1372	* This driver will enable and configure the DFLL before the ONDEMAND bit is set.
sahilmgandhi	18:6a4db94011d3	1373	*
sahilmgandhi	18:6a4db94011d3	1374	*
sahilmgandhi	18:6a4db94011d3	1375	* \section asfdoc_sam0_system_clock_extra_history Module History
sahilmgandhi	18:6a4db94011d3	1376	* An overview of the module history is presented in the table below, with
sahilmgandhi	18:6a4db94011d3	1377	* details on the enhancements and fixes made to the module since its first
sahilmgandhi	18:6a4db94011d3	1378	* release. The current version of this corresponds to the newest version in
sahilmgandhi	18:6a4db94011d3	1379	* the table.
sahilmgandhi	18:6a4db94011d3	1380	*
sahilmgandhi	18:6a4db94011d3	1381	* <table>
sahilmgandhi	18:6a4db94011d3	1382	* <tr>
sahilmgandhi	18:6a4db94011d3	1383	* <th>Changelog</th>
sahilmgandhi	18:6a4db94011d3	1384	* </tr>
sahilmgandhi	18:6a4db94011d3	1385	* <tr>
sahilmgandhi	18:6a4db94011d3	1386	* <td>
sahilmgandhi	18:6a4db94011d3	1387	* \li Corrected OSC32K startup time definitions
sahilmgandhi	18:6a4db94011d3	1388	* \li Support locking of OSC32K and XOSC32K config register (default: false)
sahilmgandhi	18:6a4db94011d3	1389	* \li Added DPLL support, functions added:
sahilmgandhi	18:6a4db94011d3	1390	* \c system_clock_source_dpll_get_config_defaults() and
sahilmgandhi	18:6a4db94011d3	1391	* \c system_clock_source_dpll_set_config()
sahilmgandhi	18:6a4db94011d3	1392	* \li Moved gclk channel locking feature out of the config struct
sahilmgandhi	18:6a4db94011d3	1393	* functions added:
sahilmgandhi	18:6a4db94011d3	1394	* \c system_gclk_chan_lock(),
sahilmgandhi	18:6a4db94011d3	1395	* \c system_gclk_chan_is_locked()
sahilmgandhi	18:6a4db94011d3	1396	* \c system_gclk_chan_is_enabled() and
sahilmgandhi	18:6a4db94011d3	1397	* \c system_gclk_gen_is_enabled()
sahilmgandhi	18:6a4db94011d3	1398	* </td>
sahilmgandhi	18:6a4db94011d3	1399	* </tr>
sahilmgandhi	18:6a4db94011d3	1400	* <tr>
sahilmgandhi	18:6a4db94011d3	1401	* <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
sahilmgandhi	18:6a4db94011d3	1402	* and configured to a failed/not running clock generator</td>
sahilmgandhi	18:6a4db94011d3	1403	* </tr>
sahilmgandhi	18:6a4db94011d3	1404	* <tr>
sahilmgandhi	18:6a4db94011d3	1405	* <td>
sahilmgandhi	18:6a4db94011d3	1406	* \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
sahilmgandhi	18:6a4db94011d3	1407	* \li Fixed system_flash_set_waitstates() failing with an assertion
sahilmgandhi	18:6a4db94011d3	1408	* if an odd number of wait states provided
sahilmgandhi	18:6a4db94011d3	1409	* </td>
sahilmgandhi	18:6a4db94011d3	1410	* </tr>
sahilmgandhi	18:6a4db94011d3	1411	* <tr>
sahilmgandhi	18:6a4db94011d3	1412	* <td>
sahilmgandhi	18:6a4db94011d3	1413	* \li Updated dfll configuration function to implement workaround for
sahilmgandhi	18:6a4db94011d3	1414	* errata 9905 in the DFLL module
sahilmgandhi	18:6a4db94011d3	1415	* \li Updated \c system_clock_init() to reset interrupt flags before
sahilmgandhi	18:6a4db94011d3	1416	* they are used
sahilmgandhi	18:6a4db94011d3	1417	* \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
sahilmgandhi	18:6a4db94011d3	1418	* frequency number
sahilmgandhi	18:6a4db94011d3	1419	* </td>
sahilmgandhi	18:6a4db94011d3	1420	* </tr>
sahilmgandhi	18:6a4db94011d3	1421	* <tr>
sahilmgandhi	18:6a4db94011d3	1422	* <td>\li Fixed \c system_clock_source_is_ready not returning the correct
sahilmgandhi	18:6a4db94011d3	1423	* state for \c SYSTEM_CLOCK_SOURCE_OSC8M
sahilmgandhi	18:6a4db94011d3	1424	* \li Renamed the various \c system_clock_source_*_get_default_config()
sahilmgandhi	18:6a4db94011d3	1425	* functions to \c system_clock_source_*_get_config_defaults() to
sahilmgandhi	18:6a4db94011d3	1426	* match the remainder of ASF
sahilmgandhi	18:6a4db94011d3	1427	* \li Added OSC8M calibration constant loading from the device signature
sahilmgandhi	18:6a4db94011d3	1428	* row when the oscillator is initialized
sahilmgandhi	18:6a4db94011d3	1429	* \li Updated default configuration of the XOSC32 to disable Automatic
sahilmgandhi	18:6a4db94011d3	1430	* Gain Control due to silicon errata
sahilmgandhi	18:6a4db94011d3	1431	* </td>
sahilmgandhi	18:6a4db94011d3	1432	* </tr>
sahilmgandhi	18:6a4db94011d3	1433	* <tr>
sahilmgandhi	18:6a4db94011d3	1434	* <td>Initial Release</td>
sahilmgandhi	18:6a4db94011d3	1435	* </tr>
sahilmgandhi	18:6a4db94011d3	1436	* </table>
sahilmgandhi	18:6a4db94011d3	1437	*/
sahilmgandhi	18:6a4db94011d3	1438
sahilmgandhi	18:6a4db94011d3	1439	/**
sahilmgandhi	18:6a4db94011d3	1440	* \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
sahilmgandhi	18:6a4db94011d3	1441	*
sahilmgandhi	18:6a4db94011d3	1442	* This is a list of the available Quick Start guides (QSGs) and example
sahilmgandhi	18:6a4db94011d3	1443	* applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
sahilmgandhi	18:6a4db94011d3	1444	* examples with step-by-step instructions to configure and use this driver in
sahilmgandhi	18:6a4db94011d3	1445	* a selection of use cases. Note that QSGs can be compiled as a standalone
sahilmgandhi	18:6a4db94011d3	1446	* application or be added to the user application.
sahilmgandhi	18:6a4db94011d3	1447	*
sahilmgandhi	18:6a4db94011d3	1448	* - \subpage asfdoc_sam0_system_clock_basic_use_case
sahilmgandhi	18:6a4db94011d3	1449	* - \subpage asfdoc_sam0_system_gclk_basic_use_case
sahilmgandhi	18:6a4db94011d3	1450	*
sahilmgandhi	18:6a4db94011d3	1451	* \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
sahilmgandhi	18:6a4db94011d3	1452	*
sahilmgandhi	18:6a4db94011d3	1453	* <table>
sahilmgandhi	18:6a4db94011d3	1454	* <tr>
sahilmgandhi	18:6a4db94011d3	1455	* <th>Doc. Rev.</td>
sahilmgandhi	18:6a4db94011d3	1456	* <th>Date</td>
sahilmgandhi	18:6a4db94011d3	1457	* <th>Comments</td>
sahilmgandhi	18:6a4db94011d3	1458	* </tr>
sahilmgandhi	18:6a4db94011d3	1459	* <tr>
sahilmgandhi	18:6a4db94011d3	1460	* <td>E</td>
sahilmgandhi	18:6a4db94011d3	1461	* <td>04/2015</td>
sahilmgandhi	18:6a4db94011d3	1462	* <td>Added support for SAMDAx.</td>
sahilmgandhi	18:6a4db94011d3	1463	* </tr>
sahilmgandhi	18:6a4db94011d3	1464	* <tr>
sahilmgandhi	18:6a4db94011d3	1465	* <td>D</td>
sahilmgandhi	18:6a4db94011d3	1466	* <td>12/2014</td>
sahilmgandhi	18:6a4db94011d3	1467	* <td>Added support for SAMR21 and SAMD10/D11.</td>
sahilmgandhi	18:6a4db94011d3	1468	* </tr>
sahilmgandhi	18:6a4db94011d3	1469	* <tr>
sahilmgandhi	18:6a4db94011d3	1470	* <td>C</td>
sahilmgandhi	18:6a4db94011d3	1471	* <td>01/2014</td>
sahilmgandhi	18:6a4db94011d3	1472	* <td>Added support for SAMD21.</td>
sahilmgandhi	18:6a4db94011d3	1473	* </tr>
sahilmgandhi	18:6a4db94011d3	1474	* <tr>
sahilmgandhi	18:6a4db94011d3	1475	* <td>B</td>
sahilmgandhi	18:6a4db94011d3	1476	* <td>06/2013</td>
sahilmgandhi	18:6a4db94011d3	1477	* <td>Corrected documentation typos. Fixed missing steps in the Basic
sahilmgandhi	18:6a4db94011d3	1478	* Use Case Quick Start Guide.</td>
sahilmgandhi	18:6a4db94011d3	1479	* </tr>
sahilmgandhi	18:6a4db94011d3	1480	* <tr>
sahilmgandhi	18:6a4db94011d3	1481	* <td>A</td>
sahilmgandhi	18:6a4db94011d3	1482	* <td>06/2013</td>
sahilmgandhi	18:6a4db94011d3	1483	* <td>Initial release</td>
sahilmgandhi	18:6a4db94011d3	1484	* </tr>
sahilmgandhi	18:6a4db94011d3	1485	* </table>
sahilmgandhi	18:6a4db94011d3	1486	*/
sahilmgandhi	18:6a4db94011d3	1487
sahilmgandhi	18:6a4db94011d3	1488	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	1489	}
sahilmgandhi	18:6a4db94011d3	1490	#endif
sahilmgandhi	18:6a4db94011d3	1491
sahilmgandhi	18:6a4db94011d3	1492	#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h@18:6a4db94011d3, 2017-05-14 (annotated)

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