MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <math.h>
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "spi_def.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23 #include "mbed_wait_api.h"
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 static const PinMap PinMap_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 26 {SCLK_SPI , SPI_0, 0},
sahilmgandhi 18:6a4db94011d3 27 {CLCD_SCLK , SPI_1, 0},
sahilmgandhi 18:6a4db94011d3 28 {ADC_SCLK , SPI_2, 0},
sahilmgandhi 18:6a4db94011d3 29 {SHIELD_0_SPI_SCK , SPI_3, 0},
sahilmgandhi 18:6a4db94011d3 30 {SHIELD_1_SPI_SCK , SPI_4, 0},
sahilmgandhi 18:6a4db94011d3 31 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 32 };
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 static const PinMap PinMap_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 35 {MOSI_SPI, SPI_0, 0},
sahilmgandhi 18:6a4db94011d3 36 {CLCD_MOSI, SPI_1, 0},
sahilmgandhi 18:6a4db94011d3 37 {ADC_MOSI, SPI_2, 0},
sahilmgandhi 18:6a4db94011d3 38 {SHIELD_0_SPI_MOSI, SPI_3, 0},
sahilmgandhi 18:6a4db94011d3 39 {SHIELD_1_SPI_MOSI, SPI_4, 0},
sahilmgandhi 18:6a4db94011d3 40 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 41 };
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 static const PinMap PinMap_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 44 {MISO_SPI, SPI_0, 0},
sahilmgandhi 18:6a4db94011d3 45 {CLCD_MISO, SPI_1, 0},
sahilmgandhi 18:6a4db94011d3 46 {ADC_MISO, SPI_2, 0},
sahilmgandhi 18:6a4db94011d3 47 {SHIELD_0_SPI_MISO, SPI_3, 0},
sahilmgandhi 18:6a4db94011d3 48 {SHIELD_1_SPI_MISO, SPI_4, 0},
sahilmgandhi 18:6a4db94011d3 49 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 50 };
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 static const PinMap PinMap_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 53 {SSEL_SPI, SPI_0, 0},
sahilmgandhi 18:6a4db94011d3 54 {CLCD_SSEL, SPI_1, 0},
sahilmgandhi 18:6a4db94011d3 55 {ADC_SSEL, SPI_2, 0},
sahilmgandhi 18:6a4db94011d3 56 {SHIELD_0_SPI_nCS, SPI_3, 0},
sahilmgandhi 18:6a4db94011d3 57 {SHIELD_1_SPI_nCS, SPI_4, 0},
sahilmgandhi 18:6a4db94011d3 58 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 59 };
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 static inline int ssp_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 62 static inline int ssp_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 int altfunction[4];
sahilmgandhi 18:6a4db94011d3 67 // determine the SPI to use
sahilmgandhi 18:6a4db94011d3 68 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 69 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 70 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 71 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 72 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 73 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 74 obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 75 if ((int)obj->spi == NC) {
sahilmgandhi 18:6a4db94011d3 76 error("SPI pinout mapping failed");
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 // enable power and clocking
sahilmgandhi 18:6a4db94011d3 80 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 81 case (int)SPI_0:
sahilmgandhi 18:6a4db94011d3 82 obj->spi->CR1 = 0;
sahilmgandhi 18:6a4db94011d3 83 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
sahilmgandhi 18:6a4db94011d3 84 obj->spi->CPSR = SSP_CPSR_DFLT;
sahilmgandhi 18:6a4db94011d3 85 obj->spi->IMSC = 0x8;
sahilmgandhi 18:6a4db94011d3 86 obj->spi->DMACR = 0;
sahilmgandhi 18:6a4db94011d3 87 obj->spi->CR1 = SSP_CR1_SSE_Msk;
sahilmgandhi 18:6a4db94011d3 88 obj->spi->ICR = 0x3;
sahilmgandhi 18:6a4db94011d3 89 break;
sahilmgandhi 18:6a4db94011d3 90 case (int)SPI_1:
sahilmgandhi 18:6a4db94011d3 91 /* Configure SSP used for LCD */
sahilmgandhi 18:6a4db94011d3 92 obj->spi->CR1 = 0; /* Synchronous serial port disable */
sahilmgandhi 18:6a4db94011d3 93 obj->spi->DMACR = 0; /* Disable FIFO DMA */
sahilmgandhi 18:6a4db94011d3 94 obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
sahilmgandhi 18:6a4db94011d3 95 obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
sahilmgandhi 18:6a4db94011d3 96 (1ul << 1) ); /* Clear SSPRTINTR interrupt */
sahilmgandhi 18:6a4db94011d3 97 obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
sahilmgandhi 18:6a4db94011d3 98 (0ul << 4) | /* Motorola frame format */
sahilmgandhi 18:6a4db94011d3 99 (0ul << 6) | /* CPOL = 0 */
sahilmgandhi 18:6a4db94011d3 100 (0ul << 7) | /* CPHA = 0 */
sahilmgandhi 18:6a4db94011d3 101 (1ul << 8) ); /* Set serial clock rate */
sahilmgandhi 18:6a4db94011d3 102 obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
sahilmgandhi 18:6a4db94011d3 103 obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
sahilmgandhi 18:6a4db94011d3 104 (0ul << 2) ); /* Device configured as master */
sahilmgandhi 18:6a4db94011d3 105 break;
sahilmgandhi 18:6a4db94011d3 106 case (int)SPI_2:
sahilmgandhi 18:6a4db94011d3 107 obj->spi->CR1 = 0;
sahilmgandhi 18:6a4db94011d3 108 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
sahilmgandhi 18:6a4db94011d3 109 obj->spi->CPSR = SSP_CPSR_DFLT;
sahilmgandhi 18:6a4db94011d3 110 obj->spi->IMSC = 0x8;
sahilmgandhi 18:6a4db94011d3 111 obj->spi->DMACR = 0;
sahilmgandhi 18:6a4db94011d3 112 obj->spi->CR1 = SSP_CR1_SSE_Msk;
sahilmgandhi 18:6a4db94011d3 113 obj->spi->ICR = 0x3;
sahilmgandhi 18:6a4db94011d3 114 break;
sahilmgandhi 18:6a4db94011d3 115 case (int)SPI_3:
sahilmgandhi 18:6a4db94011d3 116 obj->spi->CR1 = 0;
sahilmgandhi 18:6a4db94011d3 117 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
sahilmgandhi 18:6a4db94011d3 118 obj->spi->CPSR = SSP_CPSR_DFLT;
sahilmgandhi 18:6a4db94011d3 119 obj->spi->IMSC = 0x8;
sahilmgandhi 18:6a4db94011d3 120 obj->spi->DMACR = 0;
sahilmgandhi 18:6a4db94011d3 121 obj->spi->CR1 = SSP_CR1_SSE_Msk;
sahilmgandhi 18:6a4db94011d3 122 obj->spi->ICR = 0x3;
sahilmgandhi 18:6a4db94011d3 123 break;
sahilmgandhi 18:6a4db94011d3 124 case (int)SPI_4:
sahilmgandhi 18:6a4db94011d3 125 obj->spi->CR1 = 0;
sahilmgandhi 18:6a4db94011d3 126 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
sahilmgandhi 18:6a4db94011d3 127 obj->spi->CPSR = SSP_CPSR_DFLT;
sahilmgandhi 18:6a4db94011d3 128 obj->spi->IMSC = 0x8;
sahilmgandhi 18:6a4db94011d3 129 obj->spi->DMACR = 0;
sahilmgandhi 18:6a4db94011d3 130 obj->spi->CR1 = SSP_CR1_SSE_Msk;
sahilmgandhi 18:6a4db94011d3 131 obj->spi->ICR = 0x3;
sahilmgandhi 18:6a4db94011d3 132 break;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
sahilmgandhi 18:6a4db94011d3 136 if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
sahilmgandhi 18:6a4db94011d3 137 if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
sahilmgandhi 18:6a4db94011d3 138 if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 // enable alt function
sahilmgandhi 18:6a4db94011d3 141 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 142 case (int)SPI_2:
sahilmgandhi 18:6a4db94011d3 143 CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2);
sahilmgandhi 18:6a4db94011d3 144 break;
sahilmgandhi 18:6a4db94011d3 145 case (int)SPI_3:
sahilmgandhi 18:6a4db94011d3 146 CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10);
sahilmgandhi 18:6a4db94011d3 147 break;
sahilmgandhi 18:6a4db94011d3 148 case (int)SPI_4:
sahilmgandhi 18:6a4db94011d3 149 CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]);
sahilmgandhi 18:6a4db94011d3 150 break;
sahilmgandhi 18:6a4db94011d3 151 }
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 // set default format and frequency
sahilmgandhi 18:6a4db94011d3 154 if (ssel == NC) {
sahilmgandhi 18:6a4db94011d3 155 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
sahilmgandhi 18:6a4db94011d3 156 } else {
sahilmgandhi 18:6a4db94011d3 157 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159 spi_frequency(obj, 1000000);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 // enable the ssp channel
sahilmgandhi 18:6a4db94011d3 162 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 // pin out the spi pins
sahilmgandhi 18:6a4db94011d3 165 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 166 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 167 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 168 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 169 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171 }
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 void spi_free(spi_t *obj) {}
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 176 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 177 if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
sahilmgandhi 18:6a4db94011d3 178 error("SPI format error");
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 182 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 // set it up
sahilmgandhi 18:6a4db94011d3 185 int DSS = bits - 1; // DSS (data select size)
sahilmgandhi 18:6a4db94011d3 186 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sahilmgandhi 18:6a4db94011d3 187 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 int FRF = 0; // FRF (frame format) = SPI
sahilmgandhi 18:6a4db94011d3 190 uint32_t tmp = obj->spi->CR0;
sahilmgandhi 18:6a4db94011d3 191 tmp &= ~(0xFFFF);
sahilmgandhi 18:6a4db94011d3 192 tmp |= DSS << 0
sahilmgandhi 18:6a4db94011d3 193 | FRF << 4
sahilmgandhi 18:6a4db94011d3 194 | SPO << 6
sahilmgandhi 18:6a4db94011d3 195 | SPH << 7;
sahilmgandhi 18:6a4db94011d3 196 obj->spi->CR0 = tmp;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 tmp = obj->spi->CR1;
sahilmgandhi 18:6a4db94011d3 199 tmp &= ~(0xD);
sahilmgandhi 18:6a4db94011d3 200 tmp |= 0 << 0 // LBM - loop back mode - off
sahilmgandhi 18:6a4db94011d3 201 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
sahilmgandhi 18:6a4db94011d3 202 | 0 << 3; // SOD - slave output disable - na
sahilmgandhi 18:6a4db94011d3 203 obj->spi->CR1 = tmp;
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 206 }
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 209 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 int prescaler;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
sahilmgandhi 18:6a4db94011d3 216 int prescale_hz = PCLK / prescaler;
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 // calculate the divider
sahilmgandhi 18:6a4db94011d3 219 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 // check we can support the divider
sahilmgandhi 18:6a4db94011d3 222 if (divider < 256) {
sahilmgandhi 18:6a4db94011d3 223 // prescaler
sahilmgandhi 18:6a4db94011d3 224 obj->spi->CPSR = prescaler;
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 // divider
sahilmgandhi 18:6a4db94011d3 227 obj->spi->CR0 &= ~(0xFFFF << 8);
sahilmgandhi 18:6a4db94011d3 228 obj->spi->CR0 |= (divider - 1) << 8;
sahilmgandhi 18:6a4db94011d3 229 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 230 return;
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 error("Couldn't setup requested SPI frequency");
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 static inline int ssp_disable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 237 return obj->spi->CR1 &= ~(1 << 1);
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 static inline int ssp_enable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 241 return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 static inline int ssp_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 245 return obj->spi->SR & (1 << 2);
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 static inline int ssp_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 249 return obj->spi->SR & SSP_SR_BSY_Msk;
sahilmgandhi 18:6a4db94011d3 250 }
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 static inline void ssp_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 253 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 254 while (ssp_writeable(obj));
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256 static inline int ssp_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 257 int read_DR = obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 258 return read_DR;
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 static inline int ssp_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 262 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 266 ssp_write(obj, value);
sahilmgandhi 18:6a4db94011d3 267 while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
sahilmgandhi 18:6a4db94011d3 268 return (ssp_read(obj));
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 272 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 276 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 280 while (ssp_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 281 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 282 }
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 int spi_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 285 return ssp_busy(obj);
sahilmgandhi 18:6a4db94011d3 286 }