MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 /*
sahilmgandhi 18:6a4db94011d3 17 * SSP interface Support
sahilmgandhi 18:6a4db94011d3 18 * =====================
sahilmgandhi 18:6a4db94011d3 19 */
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #ifndef MBED_SPI_DEF_H
sahilmgandhi 18:6a4db94011d3 22 #define MBED_SPI_DEF_H
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 #include <stdint.h> /* standard types definitions */
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #define Module_ID 0x00090108
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 typedef struct beetle_spi
sahilmgandhi 18:6a4db94011d3 29 {
sahilmgandhi 18:6a4db94011d3 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
sahilmgandhi 18:6a4db94011d3 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
sahilmgandhi 18:6a4db94011d3 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
sahilmgandhi 18:6a4db94011d3 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
sahilmgandhi 18:6a4db94011d3 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
sahilmgandhi 18:6a4db94011d3 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
sahilmgandhi 18:6a4db94011d3 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
sahilmgandhi 18:6a4db94011d3 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
sahilmgandhi 18:6a4db94011d3 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
sahilmgandhi 18:6a4db94011d3 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
sahilmgandhi 18:6a4db94011d3 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
sahilmgandhi 18:6a4db94011d3 42 uint32_t reserved[208];
sahilmgandhi 18:6a4db94011d3 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
sahilmgandhi 18:6a4db94011d3 44 }SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
sahilmgandhi 18:6a4db94011d3 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
sahilmgandhi 18:6a4db94011d3 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /* Configuration Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
sahilmgandhi 18:6a4db94011d3 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
sahilmgandhi 18:6a4db94011d3 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
sahilmgandhi 18:6a4db94011d3 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
sahilmgandhi 18:6a4db94011d3 58 #define CONFIG_MBRD_0 0x00008
sahilmgandhi 18:6a4db94011d3 59 #define CONFIG_MBRD_1 0x00010
sahilmgandhi 18:6a4db94011d3 60 #define CONFIG_MBRD_2 0x00020
sahilmgandhi 18:6a4db94011d3 61 #define CONFIG_MBRD_SHIFT 3
sahilmgandhi 18:6a4db94011d3 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
sahilmgandhi 18:6a4db94011d3 63 #define CONFIG_TWS_0 0x00000
sahilmgandhi 18:6a4db94011d3 64 #define CONFIG_TWS_1 0x00040
sahilmgandhi 18:6a4db94011d3 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
sahilmgandhi 18:6a4db94011d3 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
sahilmgandhi 18:6a4db94011d3 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
sahilmgandhi 18:6a4db94011d3 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
sahilmgandhi 18:6a4db94011d3 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
sahilmgandhi 18:6a4db94011d3 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
sahilmgandhi 18:6a4db94011d3 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
sahilmgandhi 18:6a4db94011d3 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Interrupt Status Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
sahilmgandhi 18:6a4db94011d3 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
sahilmgandhi 18:6a4db94011d3 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
sahilmgandhi 18:6a4db94011d3 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
sahilmgandhi 18:6a4db94011d3 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
sahilmgandhi 18:6a4db94011d3 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
sahilmgandhi 18:6a4db94011d3 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /* Interrupt Enable Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
sahilmgandhi 18:6a4db94011d3 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
sahilmgandhi 18:6a4db94011d3 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
sahilmgandhi 18:6a4db94011d3 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
sahilmgandhi 18:6a4db94011d3 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
sahilmgandhi 18:6a4db94011d3 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
sahilmgandhi 18:6a4db94011d3 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /* Interrupt Disable Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
sahilmgandhi 18:6a4db94011d3 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
sahilmgandhi 18:6a4db94011d3 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
sahilmgandhi 18:6a4db94011d3 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
sahilmgandhi 18:6a4db94011d3 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
sahilmgandhi 18:6a4db94011d3 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
sahilmgandhi 18:6a4db94011d3 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Interrupt Mask Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
sahilmgandhi 18:6a4db94011d3 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
sahilmgandhi 18:6a4db94011d3 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
sahilmgandhi 18:6a4db94011d3 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
sahilmgandhi 18:6a4db94011d3 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
sahilmgandhi 18:6a4db94011d3 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
sahilmgandhi 18:6a4db94011d3 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /* SPI Enable Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /* Delay Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
sahilmgandhi 18:6a4db94011d3 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
sahilmgandhi 18:6a4db94011d3 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
sahilmgandhi 18:6a4db94011d3 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /* Transmit Data Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 120 #define TX_DATA_TDATA 0xFF
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /* Receive Data Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 123 #define RX_DATA_RDATA 0xFF
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /* Slave Idle Count Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* TX Threshold Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /* RX Threshold Register Bit Masks */
sahilmgandhi 18:6a4db94011d3 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #endif