Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | #include <math.h> |
sahilmgandhi | 18:6a4db94011d3 | 17 | |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "spi_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "spi_def.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | #include "pinmap.h" |
sahilmgandhi | 18:6a4db94011d3 | 22 | #include "mbed_error.h" |
sahilmgandhi | 18:6a4db94011d3 | 23 | #include "mbed_wait_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | /* |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Driver private data structure that should not be shared by multiple |
sahilmgandhi | 18:6a4db94011d3 | 27 | * instances of the driver (same driver for multiple instances of the IP) |
sahilmgandhi | 18:6a4db94011d3 | 28 | */ |
sahilmgandhi | 18:6a4db94011d3 | 29 | typedef struct { |
sahilmgandhi | 18:6a4db94011d3 | 30 | uint32_t size; /* size of an SPI frame in bits: can be 8 or 16 */ |
sahilmgandhi | 18:6a4db94011d3 | 31 | } private_spi_t; |
sahilmgandhi | 18:6a4db94011d3 | 32 | |
sahilmgandhi | 18:6a4db94011d3 | 33 | static const PinMap PinMap_SPI_SCLK[] = { |
sahilmgandhi | 18:6a4db94011d3 | 34 | {SHIELD_SPI_SCK , SPI_0, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 35 | {ADC_SPI_SCK , SPI_1, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 36 | {NC, NC, 0} |
sahilmgandhi | 18:6a4db94011d3 | 37 | }; |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | static const PinMap PinMap_SPI_MOSI[] = { |
sahilmgandhi | 18:6a4db94011d3 | 40 | {SHIELD_SPI_MOSI, SPI_0, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 41 | {ADC_SPI_MOSI, SPI_1, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 42 | {NC, NC, 0} |
sahilmgandhi | 18:6a4db94011d3 | 43 | }; |
sahilmgandhi | 18:6a4db94011d3 | 44 | |
sahilmgandhi | 18:6a4db94011d3 | 45 | static const PinMap PinMap_SPI_MISO[] = { |
sahilmgandhi | 18:6a4db94011d3 | 46 | {SHIELD_SPI_MISO, SPI_0, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 47 | {ADC_SPI_MISO, SPI_1, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 48 | {NC, NC, 0} |
sahilmgandhi | 18:6a4db94011d3 | 49 | }; |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | static const PinMap PinMap_SPI_SSEL[] = { |
sahilmgandhi | 18:6a4db94011d3 | 52 | {SHIELD_SPI_nCS, SPI_0, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 53 | {ADC_SPI_nCS, SPI_1, 0}, |
sahilmgandhi | 18:6a4db94011d3 | 54 | {NC, NC, 0} |
sahilmgandhi | 18:6a4db94011d3 | 55 | }; |
sahilmgandhi | 18:6a4db94011d3 | 56 | |
sahilmgandhi | 18:6a4db94011d3 | 57 | /* |
sahilmgandhi | 18:6a4db94011d3 | 58 | * Retrieve the private data of the instance related to a given IP |
sahilmgandhi | 18:6a4db94011d3 | 59 | */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | static private_spi_t* get_spi_private(spi_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 61 | static private_spi_t data0, data1; |
sahilmgandhi | 18:6a4db94011d3 | 62 | /* |
sahilmgandhi | 18:6a4db94011d3 | 63 | * Select which instance to give using the base |
sahilmgandhi | 18:6a4db94011d3 | 64 | * address of registers |
sahilmgandhi | 18:6a4db94011d3 | 65 | */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | switch ((intptr_t)obj->spi) { |
sahilmgandhi | 18:6a4db94011d3 | 67 | case SPI0_BASE: |
sahilmgandhi | 18:6a4db94011d3 | 68 | return &data0; |
sahilmgandhi | 18:6a4db94011d3 | 69 | case SPI1_BASE: |
sahilmgandhi | 18:6a4db94011d3 | 70 | return &data1; |
sahilmgandhi | 18:6a4db94011d3 | 71 | default: |
sahilmgandhi | 18:6a4db94011d3 | 72 | error("SPI driver private data structure not found for this registers base address"); |
sahilmgandhi | 18:6a4db94011d3 | 73 | return (void*)0; |
sahilmgandhi | 18:6a4db94011d3 | 74 | } |
sahilmgandhi | 18:6a4db94011d3 | 75 | } |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | void spi_init(spi_t *obj, PinName mosi, |
sahilmgandhi | 18:6a4db94011d3 | 78 | PinName miso, PinName sclk, PinName ssel) { |
sahilmgandhi | 18:6a4db94011d3 | 79 | // determine the SPI to use |
sahilmgandhi | 18:6a4db94011d3 | 80 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
sahilmgandhi | 18:6a4db94011d3 | 81 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
sahilmgandhi | 18:6a4db94011d3 | 82 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
sahilmgandhi | 18:6a4db94011d3 | 83 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
sahilmgandhi | 18:6a4db94011d3 | 84 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
sahilmgandhi | 18:6a4db94011d3 | 85 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
sahilmgandhi | 18:6a4db94011d3 | 86 | obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl); |
sahilmgandhi | 18:6a4db94011d3 | 87 | if ((int)obj->spi == NC) { |
sahilmgandhi | 18:6a4db94011d3 | 88 | error("SPI pinout mapping failed"); |
sahilmgandhi | 18:6a4db94011d3 | 89 | } |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | /* Set default format and frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | if (ssel == NC) { |
sahilmgandhi | 18:6a4db94011d3 | 93 | spi_format(obj, 8, 0, 0); // 8 bits, mode SPI_MSB, master |
sahilmgandhi | 18:6a4db94011d3 | 94 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 95 | spi_format(obj, 8, 0, 1); // 8 bits, mode SPI_LSB, slave |
sahilmgandhi | 18:6a4db94011d3 | 96 | } |
sahilmgandhi | 18:6a4db94011d3 | 97 | spi_frequency(obj, 1562500); |
sahilmgandhi | 18:6a4db94011d3 | 98 | |
sahilmgandhi | 18:6a4db94011d3 | 99 | /* Pin out the spi pins */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
sahilmgandhi | 18:6a4db94011d3 | 101 | pinmap_pinout(miso, PinMap_SPI_MISO); |
sahilmgandhi | 18:6a4db94011d3 | 102 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
sahilmgandhi | 18:6a4db94011d3 | 103 | if (ssel != NC) { |
sahilmgandhi | 18:6a4db94011d3 | 104 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
sahilmgandhi | 18:6a4db94011d3 | 105 | } |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | /* |
sahilmgandhi | 18:6a4db94011d3 | 108 | * Set desired enabled IRQs: |
sahilmgandhi | 18:6a4db94011d3 | 109 | * MF: Mode Fail |
sahilmgandhi | 18:6a4db94011d3 | 110 | * TF: TX FIFO Full |
sahilmgandhi | 18:6a4db94011d3 | 111 | * TNF: TX FIFO Not Full |
sahilmgandhi | 18:6a4db94011d3 | 112 | * RNE: RX FIFO Not Empty |
sahilmgandhi | 18:6a4db94011d3 | 113 | */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | uint32_t irqs = (IRQ_ENABLE_MFE | IRQ_ENABLE_TFE |
sahilmgandhi | 18:6a4db94011d3 | 115 | | IRQ_ENABLE_TNFE | IRQ_ENABLE_RNEE); |
sahilmgandhi | 18:6a4db94011d3 | 116 | |
sahilmgandhi | 18:6a4db94011d3 | 117 | /* |
sahilmgandhi | 18:6a4db94011d3 | 118 | * Enable: |
sahilmgandhi | 18:6a4db94011d3 | 119 | * - Master mode |
sahilmgandhi | 18:6a4db94011d3 | 120 | * - Manual start mode |
sahilmgandhi | 18:6a4db94011d3 | 121 | * - Manual chip select |
sahilmgandhi | 18:6a4db94011d3 | 122 | * - Peripheral select decode |
sahilmgandhi | 18:6a4db94011d3 | 123 | */ |
sahilmgandhi | 18:6a4db94011d3 | 124 | obj->spi->CONFIG |= (CONFIG_MSEL | CONFIG_MSE |
sahilmgandhi | 18:6a4db94011d3 | 125 | /*| CONFIG_MCSE | CONFIG_PSD*/); |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | /* Set all peripheral select lines high - these should be unused */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | obj->spi->CONFIG |= 0x00000; //CONFIG_PCSL; |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | obj->spi->IRQ_ENABLE = irqs; |
sahilmgandhi | 18:6a4db94011d3 | 131 | obj->spi->IRQ_DISABLE = ~irqs; |
sahilmgandhi | 18:6a4db94011d3 | 132 | obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE; |
sahilmgandhi | 18:6a4db94011d3 | 133 | } |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | void spi_free(spi_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 136 | } |
sahilmgandhi | 18:6a4db94011d3 | 137 | |
sahilmgandhi | 18:6a4db94011d3 | 138 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
sahilmgandhi | 18:6a4db94011d3 | 139 | private_spi_t *private_spi = get_spi_private(obj); |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | obj->spi->SPI_ENABLE &= ~SPI_ENABLE_SPIE; |
sahilmgandhi | 18:6a4db94011d3 | 142 | |
sahilmgandhi | 18:6a4db94011d3 | 143 | /* |
sahilmgandhi | 18:6a4db94011d3 | 144 | * The mbed API specifies 'bits' as being 4-16 per frame. This |
sahilmgandhi | 18:6a4db94011d3 | 145 | * controller supports only 8 or 16 bit frames. Therefore we will |
sahilmgandhi | 18:6a4db94011d3 | 146 | * assume 8 bits and, if anything larger is specified, we will use |
sahilmgandhi | 18:6a4db94011d3 | 147 | * 16 bits. |
sahilmgandhi | 18:6a4db94011d3 | 148 | */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | obj->spi->CONFIG &= ~CONFIG_TWS; /* 00 = 8 bit frame */ |
sahilmgandhi | 18:6a4db94011d3 | 150 | private_spi->size = 8; |
sahilmgandhi | 18:6a4db94011d3 | 151 | |
sahilmgandhi | 18:6a4db94011d3 | 152 | if (bits > 8) { |
sahilmgandhi | 18:6a4db94011d3 | 153 | switch (bits) { |
sahilmgandhi | 18:6a4db94011d3 | 154 | case 16: |
sahilmgandhi | 18:6a4db94011d3 | 155 | private_spi->size = 16; |
sahilmgandhi | 18:6a4db94011d3 | 156 | break; |
sahilmgandhi | 18:6a4db94011d3 | 157 | default: |
sahilmgandhi | 18:6a4db94011d3 | 158 | obj->spi->CONFIG |= CONFIG_TWS_1; /* 01 = 16 bit frame */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | break; |
sahilmgandhi | 18:6a4db94011d3 | 160 | } |
sahilmgandhi | 18:6a4db94011d3 | 161 | } |
sahilmgandhi | 18:6a4db94011d3 | 162 | |
sahilmgandhi | 18:6a4db94011d3 | 163 | switch (mode) { |
sahilmgandhi | 18:6a4db94011d3 | 164 | default: |
sahilmgandhi | 18:6a4db94011d3 | 165 | case 0: |
sahilmgandhi | 18:6a4db94011d3 | 166 | obj->spi->CONFIG &= ~CONFIG_CPOL; |
sahilmgandhi | 18:6a4db94011d3 | 167 | obj->spi->CONFIG &= ~CONFIG_CPHA; |
sahilmgandhi | 18:6a4db94011d3 | 168 | break; |
sahilmgandhi | 18:6a4db94011d3 | 169 | case 1: |
sahilmgandhi | 18:6a4db94011d3 | 170 | obj->spi->CONFIG &= ~CONFIG_CPOL; |
sahilmgandhi | 18:6a4db94011d3 | 171 | obj->spi->CONFIG |= CONFIG_CPHA; |
sahilmgandhi | 18:6a4db94011d3 | 172 | break; |
sahilmgandhi | 18:6a4db94011d3 | 173 | case 2: |
sahilmgandhi | 18:6a4db94011d3 | 174 | obj->spi->CONFIG |= CONFIG_CPOL; |
sahilmgandhi | 18:6a4db94011d3 | 175 | obj->spi->CONFIG &= ~CONFIG_CPHA; |
sahilmgandhi | 18:6a4db94011d3 | 176 | break; |
sahilmgandhi | 18:6a4db94011d3 | 177 | case 3: |
sahilmgandhi | 18:6a4db94011d3 | 178 | obj->spi->CONFIG |= CONFIG_CPOL; |
sahilmgandhi | 18:6a4db94011d3 | 179 | obj->spi->CONFIG |= CONFIG_CPHA; |
sahilmgandhi | 18:6a4db94011d3 | 180 | break; |
sahilmgandhi | 18:6a4db94011d3 | 181 | } |
sahilmgandhi | 18:6a4db94011d3 | 182 | |
sahilmgandhi | 18:6a4db94011d3 | 183 | obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE; |
sahilmgandhi | 18:6a4db94011d3 | 184 | } |
sahilmgandhi | 18:6a4db94011d3 | 185 | |
sahilmgandhi | 18:6a4db94011d3 | 186 | void spi_frequency(spi_t *obj, int hz) { |
sahilmgandhi | 18:6a4db94011d3 | 187 | /* |
sahilmgandhi | 18:6a4db94011d3 | 188 | * Valid frequencies are derived from a 25MHz peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 189 | * Frequency | Divisor | MBRD Value | Hz |
sahilmgandhi | 18:6a4db94011d3 | 190 | * 12.0 MHz 2 000 12000000 |
sahilmgandhi | 18:6a4db94011d3 | 191 | * 6.0 MHz 4 001 6000000 |
sahilmgandhi | 18:6a4db94011d3 | 192 | * 3.0 MHz 8 010 3000000 |
sahilmgandhi | 18:6a4db94011d3 | 193 | * 1.5 MHz 16 011 1500000 |
sahilmgandhi | 18:6a4db94011d3 | 194 | * 750.0 KHz 32 100 750000 |
sahilmgandhi | 18:6a4db94011d3 | 195 | * 375.0 KHz 64 101 375000 |
sahilmgandhi | 18:6a4db94011d3 | 196 | * 187.500 KHz 128 110 187500 |
sahilmgandhi | 18:6a4db94011d3 | 197 | * 93.750 KHz 256 111 93750 |
sahilmgandhi | 18:6a4db94011d3 | 198 | */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | int valid_frequencies[] = {12000000, 6000000, 3000000, 1500000, |
sahilmgandhi | 18:6a4db94011d3 | 200 | 750000, 375000, 187500, 93750}; |
sahilmgandhi | 18:6a4db94011d3 | 201 | uint16_t mbrd_value = 0; |
sahilmgandhi | 18:6a4db94011d3 | 202 | uint32_t config = (obj->spi->CONFIG & ~CONFIG_MBRD); |
sahilmgandhi | 18:6a4db94011d3 | 203 | |
sahilmgandhi | 18:6a4db94011d3 | 204 | /* Store the index of the minimum supported frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 205 | uint32_t index = 7; |
sahilmgandhi | 18:6a4db94011d3 | 206 | |
sahilmgandhi | 18:6a4db94011d3 | 207 | for (int i = 0; i < 8; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 208 | if (hz >= valid_frequencies[i]) { |
sahilmgandhi | 18:6a4db94011d3 | 209 | /* |
sahilmgandhi | 18:6a4db94011d3 | 210 | * Store the index of the closest lower or equal supported |
sahilmgandhi | 18:6a4db94011d3 | 211 | * frequency. |
sahilmgandhi | 18:6a4db94011d3 | 212 | */ |
sahilmgandhi | 18:6a4db94011d3 | 213 | index = i; |
sahilmgandhi | 18:6a4db94011d3 | 214 | break; |
sahilmgandhi | 18:6a4db94011d3 | 215 | } |
sahilmgandhi | 18:6a4db94011d3 | 216 | |
sahilmgandhi | 18:6a4db94011d3 | 217 | mbrd_value++; |
sahilmgandhi | 18:6a4db94011d3 | 218 | } |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | /* |
sahilmgandhi | 18:6a4db94011d3 | 221 | * Set the selected frequency. If the frequency is below the minimum |
sahilmgandhi | 18:6a4db94011d3 | 222 | * supported the driver sets the minumum. |
sahilmgandhi | 18:6a4db94011d3 | 223 | */ |
sahilmgandhi | 18:6a4db94011d3 | 224 | config |= index << CONFIG_MBRD_SHIFT; |
sahilmgandhi | 18:6a4db94011d3 | 225 | |
sahilmgandhi | 18:6a4db94011d3 | 226 | /* |
sahilmgandhi | 18:6a4db94011d3 | 227 | * If the specified frequency didn't match any of the valid frequencies |
sahilmgandhi | 18:6a4db94011d3 | 228 | * then leave CONFIG_MBRD to the closest lower frequency supported. |
sahilmgandhi | 18:6a4db94011d3 | 229 | */ |
sahilmgandhi | 18:6a4db94011d3 | 230 | obj->spi->CONFIG = config; |
sahilmgandhi | 18:6a4db94011d3 | 231 | } |
sahilmgandhi | 18:6a4db94011d3 | 232 | |
sahilmgandhi | 18:6a4db94011d3 | 233 | int spi_master_write(spi_t *obj, int value) { |
sahilmgandhi | 18:6a4db94011d3 | 234 | private_spi_t *private_spi = get_spi_private(obj); |
sahilmgandhi | 18:6a4db94011d3 | 235 | |
sahilmgandhi | 18:6a4db94011d3 | 236 | int data = 0; |
sahilmgandhi | 18:6a4db94011d3 | 237 | if(private_spi->size == 16) { |
sahilmgandhi | 18:6a4db94011d3 | 238 | obj->spi->TX_DATA = (uint8_t)((value >> 8) & TX_DATA_TDATA); |
sahilmgandhi | 18:6a4db94011d3 | 239 | obj->spi->TX_DATA = (uint8_t)(value & TX_DATA_TDATA); |
sahilmgandhi | 18:6a4db94011d3 | 240 | |
sahilmgandhi | 18:6a4db94011d3 | 241 | /* Manually trigger start */ |
sahilmgandhi | 18:6a4db94011d3 | 242 | obj->spi->CONFIG |= CONFIG_MSC; |
sahilmgandhi | 18:6a4db94011d3 | 243 | |
sahilmgandhi | 18:6a4db94011d3 | 244 | while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF)) |
sahilmgandhi | 18:6a4db94011d3 | 245 | continue; |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | data = (obj->spi->RX_DATA & RX_DATA_RDATA) << 8; |
sahilmgandhi | 18:6a4db94011d3 | 248 | data = data | (obj->spi->RX_DATA & RX_DATA_RDATA); |
sahilmgandhi | 18:6a4db94011d3 | 249 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 250 | |
sahilmgandhi | 18:6a4db94011d3 | 251 | obj->spi->TX_DATA = (uint16_t)(value & TX_DATA_TDATA); |
sahilmgandhi | 18:6a4db94011d3 | 252 | |
sahilmgandhi | 18:6a4db94011d3 | 253 | /* Manually trigger start */ |
sahilmgandhi | 18:6a4db94011d3 | 254 | obj->spi->CONFIG |= CONFIG_MSC; |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF)) |
sahilmgandhi | 18:6a4db94011d3 | 257 | continue; |
sahilmgandhi | 18:6a4db94011d3 | 258 | |
sahilmgandhi | 18:6a4db94011d3 | 259 | data = obj->spi->RX_DATA & RX_DATA_RDATA; |
sahilmgandhi | 18:6a4db94011d3 | 260 | } |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | return data; |
sahilmgandhi | 18:6a4db94011d3 | 263 | } |
sahilmgandhi | 18:6a4db94011d3 | 264 | |
sahilmgandhi | 18:6a4db94011d3 | 265 | uint8_t spi_get_module(spi_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 266 | return obj->spi->MID; |
sahilmgandhi | 18:6a4db94011d3 | 267 | } |
sahilmgandhi | 18:6a4db94011d3 | 268 | |
sahilmgandhi | 18:6a4db94011d3 | 269 | int spi_busy(spi_t *obj) { |
sahilmgandhi | 18:6a4db94011d3 | 270 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 271 | } |