MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/system_core_beetle.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * PackageLicenseDeclared: Apache-2.0
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 6 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 7 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 12 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 14 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 15 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 16 */
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 #include "CMSDK_BEETLE.h"
sahilmgandhi 18:6a4db94011d3 19 #include "system_core_beetle.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 /*
sahilmgandhi 18:6a4db94011d3 22 * SystemCoreConfig(): Configure the System Core
sahilmgandhi 18:6a4db94011d3 23 */
sahilmgandhi 18:6a4db94011d3 24 void SystemCoreConfig()
sahilmgandhi 18:6a4db94011d3 25 {
sahilmgandhi 18:6a4db94011d3 26 /* Set GPIO Alternate Functions */
sahilmgandhi 18:6a4db94011d3 27 CMSDK_GPIO0->ALTFUNCSET = (1<<0); /* Sheild 0 UART 0 RXD */
sahilmgandhi 18:6a4db94011d3 28 CMSDK_GPIO0->ALTFUNCSET |= (1<<1); /* Sheild 0 UART 0 TXD */
sahilmgandhi 18:6a4db94011d3 29 CMSDK_GPIO0->ALTFUNCSET |= (1<<14); /* Sheild 0 I2C SDA SBCON2 */
sahilmgandhi 18:6a4db94011d3 30 CMSDK_GPIO0->ALTFUNCSET |= (1<<15); /* Sheild 0 I2C SCL SBCON2 */
sahilmgandhi 18:6a4db94011d3 31 CMSDK_GPIO0->ALTFUNCSET |= (1<<10); /* Sheild 0 SPI_3 nCS */
sahilmgandhi 18:6a4db94011d3 32 CMSDK_GPIO0->ALTFUNCSET |= (1<<11); /* Sheild 0 SPI_3 MOSI */
sahilmgandhi 18:6a4db94011d3 33 CMSDK_GPIO0->ALTFUNCSET |= (1<<12); /* Sheild 0 SPI_3 MISO */
sahilmgandhi 18:6a4db94011d3 34 CMSDK_GPIO0->ALTFUNCSET |= (1<<13); /* Sheild 0 SPI_3 SCK */
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 CMSDK_GPIO1->ALTFUNCSET = (1<<0); /* UART 1 RXD */
sahilmgandhi 18:6a4db94011d3 37 CMSDK_GPIO1->ALTFUNCSET |= (1<<1); /* UART 1 TXD */
sahilmgandhi 18:6a4db94011d3 38 CMSDK_GPIO1->ALTFUNCSET |= (1<<6); /* Sheild 1 I2C SDA */
sahilmgandhi 18:6a4db94011d3 39 CMSDK_GPIO1->ALTFUNCSET |= (1<<7); /* Sheild 1 I2C SCL */
sahilmgandhi 18:6a4db94011d3 40 CMSDK_GPIO1->ALTFUNCSET |= (1<<2); /* ADC SPI_2 nCS */
sahilmgandhi 18:6a4db94011d3 41 CMSDK_GPIO1->ALTFUNCSET |= (1<<3); /* ADC SPI_2 MOSI */
sahilmgandhi 18:6a4db94011d3 42 CMSDK_GPIO1->ALTFUNCSET |= (1<<4); /* ADC SPI_2 MISO */
sahilmgandhi 18:6a4db94011d3 43 CMSDK_GPIO1->ALTFUNCSET |= (1<<5); /* ADC SPI_2 SCK */
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 CMSDK_GPIO1->ALTFUNCSET |= (1<<8); /* QSPI CS 2 */
sahilmgandhi 18:6a4db94011d3 46 CMSDK_GPIO1->ALTFUNCSET |= (1<<9); /* QSPI CS 1 */
sahilmgandhi 18:6a4db94011d3 47 CMSDK_GPIO1->ALTFUNCSET |= (1<<10); /* QSPI IO 0 */
sahilmgandhi 18:6a4db94011d3 48 CMSDK_GPIO1->ALTFUNCSET |= (1<<11); /* QSPI IO 1 */
sahilmgandhi 18:6a4db94011d3 49 CMSDK_GPIO1->ALTFUNCSET |= (1<<12); /* QSPI IO 2 */
sahilmgandhi 18:6a4db94011d3 50 CMSDK_GPIO1->ALTFUNCSET |= (1<<13); /* QSPI IO 3 */
sahilmgandhi 18:6a4db94011d3 51 CMSDK_GPIO1->ALTFUNCSET |= (1<<14); /* QSPI SCK */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /* Set the ARD_PWR_EN GPIO1[15] as an output */
sahilmgandhi 18:6a4db94011d3 54 CMSDK_GPIO1->OUTENABLESET |= (0x1 << 15);
sahilmgandhi 18:6a4db94011d3 55 /* Set on 3v3 (for ARDUINO HDR compliancy) */
sahilmgandhi 18:6a4db94011d3 56 CMSDK_GPIO1->DATA |= (0x1 << 15);
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /* POWER MANAGEMENT */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /*
sahilmgandhi 18:6a4db94011d3 62 * SystemPowerConfig(): Configures the System Power Modes
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64 void SystemPowerConfig()
sahilmgandhi 18:6a4db94011d3 65 {
sahilmgandhi 18:6a4db94011d3 66 /* Configure APB Peripheral Clock in sleep state */
sahilmgandhi 18:6a4db94011d3 67 CMSDK_SYSCON->APBCLKCFG1SET = SYSTEM_CORE_TIMER0
sahilmgandhi 18:6a4db94011d3 68 | SYSTEM_CORE_TIMER1
sahilmgandhi 18:6a4db94011d3 69 | SYSTEM_CORE_DUALTIMER0
sahilmgandhi 18:6a4db94011d3 70 | SYSTEM_CORE_UART1
sahilmgandhi 18:6a4db94011d3 71 | SYSTEM_CORE_I2C0
sahilmgandhi 18:6a4db94011d3 72 | SYSTEM_CORE_QSPI
sahilmgandhi 18:6a4db94011d3 73 | SYSTEM_CORE_SPI0
sahilmgandhi 18:6a4db94011d3 74 | SYSTEM_CORE_SPI1
sahilmgandhi 18:6a4db94011d3 75 | SYSTEM_CORE_I2C1;
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /* Configure APB Peripheral Clock in deep sleep state */
sahilmgandhi 18:6a4db94011d3 78 CMSDK_SYSCON->APBCLKCFG2SET = SYSTEM_CORE_TIMER0
sahilmgandhi 18:6a4db94011d3 79 | SYSTEM_CORE_TIMER1
sahilmgandhi 18:6a4db94011d3 80 | SYSTEM_CORE_DUALTIMER0
sahilmgandhi 18:6a4db94011d3 81 | SYSTEM_CORE_UART1
sahilmgandhi 18:6a4db94011d3 82 | SYSTEM_CORE_I2C0
sahilmgandhi 18:6a4db94011d3 83 | SYSTEM_CORE_QSPI
sahilmgandhi 18:6a4db94011d3 84 | SYSTEM_CORE_SPI0
sahilmgandhi 18:6a4db94011d3 85 | SYSTEM_CORE_SPI1
sahilmgandhi 18:6a4db94011d3 86 | SYSTEM_CORE_I2C1;
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Configure Wakeup Sources */
sahilmgandhi 18:6a4db94011d3 89 CMSDK_SYSCON->PWRDNCFG1SET = SYSTEM_CORE_DUALTIMER0;
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /*
sahilmgandhi 18:6a4db94011d3 93 * SystemPowerSuspend(): Enters in System Suspend
sahilmgandhi 18:6a4db94011d3 94 */
sahilmgandhi 18:6a4db94011d3 95 void SystemPowerSuspend(power_mode_t mode)
sahilmgandhi 18:6a4db94011d3 96 {
sahilmgandhi 18:6a4db94011d3 97 if (mode == POWER_MODE_DEEP_SLEEP) {
sahilmgandhi 18:6a4db94011d3 98 /* Enable deepsleep */
sahilmgandhi 18:6a4db94011d3 99 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
sahilmgandhi 18:6a4db94011d3 100 /* Ensure effect of last store takes effect */
sahilmgandhi 18:6a4db94011d3 101 __DSB();
sahilmgandhi 18:6a4db94011d3 102 /* Enter sleep mode */
sahilmgandhi 18:6a4db94011d3 103 __WFI();
sahilmgandhi 18:6a4db94011d3 104 } else {
sahilmgandhi 18:6a4db94011d3 105 /* Enter sleep mode */
sahilmgandhi 18:6a4db94011d3 106 __WFI();
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /*
sahilmgandhi 18:6a4db94011d3 111 * SystemPowerResume(): Returns from System Suspend
sahilmgandhi 18:6a4db94011d3 112 */
sahilmgandhi 18:6a4db94011d3 113 void SystemPowerResume(power_mode_t mode)
sahilmgandhi 18:6a4db94011d3 114 {
sahilmgandhi 18:6a4db94011d3 115 if (mode == POWER_MODE_DEEP_SLEEP) {
sahilmgandhi 18:6a4db94011d3 116 /* Disable sleeponexit */
sahilmgandhi 18:6a4db94011d3 117 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
sahilmgandhi 18:6a4db94011d3 118 /* Ensure effect of last store takes effect */
sahilmgandhi 18:6a4db94011d3 119 __DSB();
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /*
sahilmgandhi 18:6a4db94011d3 125 * System config data storage functions
sahilmgandhi 18:6a4db94011d3 126 * Reserved as the data is not strictly persistent
sahilmgandhi 18:6a4db94011d3 127 */
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /*
sahilmgandhi 18:6a4db94011d3 130 * __System_Config_GetBDAddr(): Address for the BLE device on the air.
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132 void __System_Config_GetBDAddr(uint8_t *addr, uint8_t byte_len)
sahilmgandhi 18:6a4db94011d3 133 {
sahilmgandhi 18:6a4db94011d3 134 SystemCoreConfigData *p;
sahilmgandhi 18:6a4db94011d3 135 int bank1addr = EFlash_ReturnBank1BaseAddress();
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 if (byte_len > 6)
sahilmgandhi 18:6a4db94011d3 138 {
sahilmgandhi 18:6a4db94011d3 139 return;
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 if (bank1addr < 0)
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 memset(addr, 0xFF, byte_len);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146 else
sahilmgandhi 18:6a4db94011d3 147 {
sahilmgandhi 18:6a4db94011d3 148 /* 2x bank1 address is the top as banks have to be symmetric sizes */
sahilmgandhi 18:6a4db94011d3 149 /* The data is stored at the end.*/
sahilmgandhi 18:6a4db94011d3 150 p = (SystemCoreConfigData *) ((2 * bank1addr) - SYSTEM_CORE_CONFIG_DATA_SIZE);
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 memcpy(addr, p->BD_ADDR, byte_len);
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154 }