MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/fcache_api.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #ifndef _FCACHE_DRV_H
sahilmgandhi 18:6a4db94011d3 18 #define _FCACHE_DRV_H
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 extern "C" {
sahilmgandhi 18:6a4db94011d3 23 #else
sahilmgandhi 18:6a4db94011d3 24 #include <stdio.h>
sahilmgandhi 18:6a4db94011d3 25 #endif
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 /* Flash Cache Address Map */
sahilmgandhi 18:6a4db94011d3 28 #define SYS_FCACHE_BASE 0x40003000
sahilmgandhi 18:6a4db94011d3 29 /* Configuration and Control Register */
sahilmgandhi 18:6a4db94011d3 30 #define SYS_FCACHE_CCR (SYS_FCACHE_BASE)
sahilmgandhi 18:6a4db94011d3 31 /* Status Register */
sahilmgandhi 18:6a4db94011d3 32 #define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4)
sahilmgandhi 18:6a4db94011d3 33 /* Interrupt Req Status Register */
sahilmgandhi 18:6a4db94011d3 34 #define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8)
sahilmgandhi 18:6a4db94011d3 35 /* Cache Statistic Hit Register */
sahilmgandhi 18:6a4db94011d3 36 #define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14)
sahilmgandhi 18:6a4db94011d3 37 /* Cache Statistic Miss Register */
sahilmgandhi 18:6a4db94011d3 38 #define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18)
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 /* SYS_FCACHE_CCR (RW): Configuration and Control Register */
sahilmgandhi 18:6a4db94011d3 41 #define FCACHE_EN 1 /* FCache Enable */
sahilmgandhi 18:6a4db94011d3 42 #define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */
sahilmgandhi 18:6a4db94011d3 43 #define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */
sahilmgandhi 18:6a4db94011d3 44 #define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */
sahilmgandhi 18:6a4db94011d3 45 #define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */
sahilmgandhi 18:6a4db94011d3 46 #define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */
sahilmgandhi 18:6a4db94011d3 47 #define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /* SYS_FCACHE_SR (RO): Status Register */
sahilmgandhi 18:6a4db94011d3 50 #define FCACHE_CS 0x3 /* Cache Status Mask */
sahilmgandhi 18:6a4db94011d3 51 #define FCACHE_CS_DISABLED 0x0
sahilmgandhi 18:6a4db94011d3 52 #define FCACHE_CS_ENABLING 0x1
sahilmgandhi 18:6a4db94011d3 53 #define FCACHE_CS_ENABLED 0x2
sahilmgandhi 18:6a4db94011d3 54 #define FCACHE_CS_DISABLING 0x3
sahilmgandhi 18:6a4db94011d3 55 #define FCACHE_INV_STAT 0x4 /* Invalidating Status */
sahilmgandhi 18:6a4db94011d3 56 #define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */
sahilmgandhi 18:6a4db94011d3 59 #define FCACHE_POW_ERR 1 /* SRAM Power Error */
sahilmgandhi 18:6a4db94011d3 60 #define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* Macros */
sahilmgandhi 18:6a4db94011d3 63 #define FCache_Readl(reg) *(volatile unsigned int *)reg
sahilmgandhi 18:6a4db94011d3 64 #define FCache_Writel(reg, val) *(volatile unsigned int *)reg = val;
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /* Functions */
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 /*
sahilmgandhi 18:6a4db94011d3 69 * FCache_DriverInitialize: flash cache driver initialize funtion
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71 void FCache_DriverInitialize(void);
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /*
sahilmgandhi 18:6a4db94011d3 74 * FCache_Enable: Enables the flash cache mode
sahilmgandhi 18:6a4db94011d3 75 * mode: supported modes:
sahilmgandhi 18:6a4db94011d3 76 * 0 - auto-power auto-invalidate
sahilmgandhi 18:6a4db94011d3 77 * 1 - manual-power, manual-invalidate
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 void FCache_Enable(int mode);
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /*
sahilmgandhi 18:6a4db94011d3 82 * FCache_Disable: Disables the flash cache mode previously enabled
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 void FCache_Disable(void);
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /*
sahilmgandhi 18:6a4db94011d3 87 * FCache_Invalidate: to be invalidated the cache needs to be disabled.
sahilmgandhi 18:6a4db94011d3 88 * return -1: flash cannot be disabled
sahilmgandhi 18:6a4db94011d3 89 * -2: flash cannot be enabled
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91 int FCache_Invalidate(void);
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /*
sahilmgandhi 18:6a4db94011d3 94 * FCache_GetStats: provides cache stats
sahilmgandhi 18:6a4db94011d3 95 */
sahilmgandhi 18:6a4db94011d3 96 unsigned int * FCache_GetStats(void);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /*
sahilmgandhi 18:6a4db94011d3 99 * FCache_isEnabled: returns 1 if FCache is enabled
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101 unsigned int FCache_isEnabled(void);
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 104 }
sahilmgandhi 18:6a4db94011d3 105 #endif
sahilmgandhi 18:6a4db94011d3 106 #endif /* _FCACHE_DRV_H */