MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_sc300.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_sc300.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V4.10
sahilmgandhi 18:6a4db94011d3 5 * @date 18. March 2015
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #if defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 39 #pragma system_include /* treat file as system include file for MISRA check */
sahilmgandhi 18:6a4db94011d3 40 #endif
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifndef __CORE_SC300_H_GENERIC
sahilmgandhi 18:6a4db94011d3 43 #define __CORE_SC300_H_GENERIC
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 46 extern "C" {
sahilmgandhi 18:6a4db94011d3 47 #endif
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sahilmgandhi 18:6a4db94011d3 50 CMSIS violates the following MISRA-C:2004 rules:
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 \li Required Rule 8.5, object/function definition in header file.<br>
sahilmgandhi 18:6a4db94011d3 53 Function definitions in header files are used to allow 'inlining'.
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sahilmgandhi 18:6a4db94011d3 56 Unions are used for effective representation of core registers.
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
sahilmgandhi 18:6a4db94011d3 59 Function-like macros are used to allow more efficient code.
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 64 * CMSIS definitions
sahilmgandhi 18:6a4db94011d3 65 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 66 /** \ingroup SC3000
sahilmgandhi 18:6a4db94011d3 67 @{
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /* CMSIS SC300 definitions */
sahilmgandhi 18:6a4db94011d3 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
sahilmgandhi 18:6a4db94011d3 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
sahilmgandhi 18:6a4db94011d3 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
sahilmgandhi 18:6a4db94011d3 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 82 #define __STATIC_INLINE static __inline
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 87 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
sahilmgandhi 18:6a4db94011d3 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
sahilmgandhi 18:6a4db94011d3 92 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
sahilmgandhi 18:6a4db94011d3 96 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 101 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 #elif defined ( __CSMC__ )
sahilmgandhi 18:6a4db94011d3 104 #define __packed
sahilmgandhi 18:6a4db94011d3 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
sahilmgandhi 18:6a4db94011d3 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
sahilmgandhi 18:6a4db94011d3 107 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 #endif
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /** __FPU_USED indicates whether an FPU is used or not.
sahilmgandhi 18:6a4db94011d3 112 This core does not support an FPU at all
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 117 #if defined __TARGET_FPU_VFP
sahilmgandhi 18:6a4db94011d3 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
sahilmgandhi 18:6a4db94011d3 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 124 #endif
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 127 #if defined __ARMVFP__
sahilmgandhi 18:6a4db94011d3 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 129 #endif
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 132 #if defined __TI__VFP_SUPPORT____
sahilmgandhi 18:6a4db94011d3 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 134 #endif
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 137 #if defined __FPU_VFP__
sahilmgandhi 18:6a4db94011d3 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 139 #endif
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 #elif defined ( __CSMC__ ) /* Cosmic */
sahilmgandhi 18:6a4db94011d3 142 #if ( __CSMC__ & 0x400) // FPU present for parser
sahilmgandhi 18:6a4db94011d3 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 144 #endif
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 #include <stdint.h> /* standard types definitions */
sahilmgandhi 18:6a4db94011d3 148 #include <core_cmInstr.h> /* Core Instruction Access */
sahilmgandhi 18:6a4db94011d3 149 #include <core_cmFunc.h> /* Core Function Access */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 #endif
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #endif /* __CORE_SC300_H_GENERIC */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 #ifndef __CMSIS_GENERIC
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 #ifndef __CORE_SC300_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 160 #define __CORE_SC300_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 163 extern "C" {
sahilmgandhi 18:6a4db94011d3 164 #endif
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* check device defines and use defaults */
sahilmgandhi 18:6a4db94011d3 167 #if defined __CHECK_DEVICE_DEFINES
sahilmgandhi 18:6a4db94011d3 168 #ifndef __SC300_REV
sahilmgandhi 18:6a4db94011d3 169 #define __SC300_REV 0x0000
sahilmgandhi 18:6a4db94011d3 170 #warning "__SC300_REV not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 171 #endif
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 #ifndef __MPU_PRESENT
sahilmgandhi 18:6a4db94011d3 174 #define __MPU_PRESENT 0
sahilmgandhi 18:6a4db94011d3 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 176 #endif
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 #ifndef __NVIC_PRIO_BITS
sahilmgandhi 18:6a4db94011d3 179 #define __NVIC_PRIO_BITS 4
sahilmgandhi 18:6a4db94011d3 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 181 #endif
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 #ifndef __Vendor_SysTickConfig
sahilmgandhi 18:6a4db94011d3 184 #define __Vendor_SysTickConfig 0
sahilmgandhi 18:6a4db94011d3 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 186 #endif
sahilmgandhi 18:6a4db94011d3 187 #endif
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /* IO definitions (access restrictions to peripheral registers) */
sahilmgandhi 18:6a4db94011d3 190 /**
sahilmgandhi 18:6a4db94011d3 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 <strong>IO Type Qualifiers</strong> are used
sahilmgandhi 18:6a4db94011d3 194 \li to specify the access to peripheral variables.
sahilmgandhi 18:6a4db94011d3 195 \li for automatic generation of peripheral register debug information.
sahilmgandhi 18:6a4db94011d3 196 */
sahilmgandhi 18:6a4db94011d3 197 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 198 #define __I volatile /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 199 #else
sahilmgandhi 18:6a4db94011d3 200 #define __I volatile const /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 201 #endif
sahilmgandhi 18:6a4db94011d3 202 #define __O volatile /*!< Defines 'write only' permissions */
sahilmgandhi 18:6a4db94011d3 203 #define __IO volatile /*!< Defines 'read / write' permissions */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /*@} end of group SC300 */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 210 * Register Abstraction
sahilmgandhi 18:6a4db94011d3 211 Core Register contain:
sahilmgandhi 18:6a4db94011d3 212 - Core Register
sahilmgandhi 18:6a4db94011d3 213 - Core NVIC Register
sahilmgandhi 18:6a4db94011d3 214 - Core SCB Register
sahilmgandhi 18:6a4db94011d3 215 - Core SysTick Register
sahilmgandhi 18:6a4db94011d3 216 - Core Debug Register
sahilmgandhi 18:6a4db94011d3 217 - Core MPU Register
sahilmgandhi 18:6a4db94011d3 218 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
sahilmgandhi 18:6a4db94011d3 220 \brief Type definitions and defines for Cortex-M processor based devices.
sahilmgandhi 18:6a4db94011d3 221 */
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 224 \defgroup CMSIS_CORE Status and Control Registers
sahilmgandhi 18:6a4db94011d3 225 \brief Core Register type definitions.
sahilmgandhi 18:6a4db94011d3 226 @{
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 /** \brief Union type to access the Application Program Status Register (APSR).
sahilmgandhi 18:6a4db94011d3 230 */
sahilmgandhi 18:6a4db94011d3 231 typedef union
sahilmgandhi 18:6a4db94011d3 232 {
sahilmgandhi 18:6a4db94011d3 233 struct
sahilmgandhi 18:6a4db94011d3 234 {
sahilmgandhi 18:6a4db94011d3 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
sahilmgandhi 18:6a4db94011d3 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
sahilmgandhi 18:6a4db94011d3 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sahilmgandhi 18:6a4db94011d3 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sahilmgandhi 18:6a4db94011d3 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sahilmgandhi 18:6a4db94011d3 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sahilmgandhi 18:6a4db94011d3 241 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 242 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 243 } APSR_Type;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /* APSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
sahilmgandhi 18:6a4db94011d3 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
sahilmgandhi 18:6a4db94011d3 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
sahilmgandhi 18:6a4db94011d3 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
sahilmgandhi 18:6a4db94011d3 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
sahilmgandhi 18:6a4db94011d3 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 typedef union
sahilmgandhi 18:6a4db94011d3 265 {
sahilmgandhi 18:6a4db94011d3 266 struct
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sahilmgandhi 18:6a4db94011d3 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
sahilmgandhi 18:6a4db94011d3 270 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 271 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 272 } IPSR_Type;
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* IPSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
sahilmgandhi 18:6a4db94011d3 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
sahilmgandhi 18:6a4db94011d3 280 */
sahilmgandhi 18:6a4db94011d3 281 typedef union
sahilmgandhi 18:6a4db94011d3 282 {
sahilmgandhi 18:6a4db94011d3 283 struct
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sahilmgandhi 18:6a4db94011d3 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
sahilmgandhi 18:6a4db94011d3 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
sahilmgandhi 18:6a4db94011d3 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
sahilmgandhi 18:6a4db94011d3 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
sahilmgandhi 18:6a4db94011d3 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sahilmgandhi 18:6a4db94011d3 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sahilmgandhi 18:6a4db94011d3 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sahilmgandhi 18:6a4db94011d3 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sahilmgandhi 18:6a4db94011d3 294 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 295 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 296 } xPSR_Type;
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* xPSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
sahilmgandhi 18:6a4db94011d3 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
sahilmgandhi 18:6a4db94011d3 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
sahilmgandhi 18:6a4db94011d3 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
sahilmgandhi 18:6a4db94011d3 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
sahilmgandhi 18:6a4db94011d3 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
sahilmgandhi 18:6a4db94011d3 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
sahilmgandhi 18:6a4db94011d3 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
sahilmgandhi 18:6a4db94011d3 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /** \brief Union type to access the Control Registers (CONTROL).
sahilmgandhi 18:6a4db94011d3 325 */
sahilmgandhi 18:6a4db94011d3 326 typedef union
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 struct
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
sahilmgandhi 18:6a4db94011d3 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
sahilmgandhi 18:6a4db94011d3 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
sahilmgandhi 18:6a4db94011d3 333 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 334 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 335 } CONTROL_Type;
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 /* CONTROL Register Definitions */
sahilmgandhi 18:6a4db94011d3 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
sahilmgandhi 18:6a4db94011d3 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
sahilmgandhi 18:6a4db94011d3 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 /*@} end of group CMSIS_CORE */
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
sahilmgandhi 18:6a4db94011d3 349 \brief Type definitions for the NVIC Registers
sahilmgandhi 18:6a4db94011d3 350 @{
sahilmgandhi 18:6a4db94011d3 351 */
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355 typedef struct
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
sahilmgandhi 18:6a4db94011d3 358 uint32_t RESERVED0[24];
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
sahilmgandhi 18:6a4db94011d3 360 uint32_t RSERVED1[24];
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
sahilmgandhi 18:6a4db94011d3 362 uint32_t RESERVED2[24];
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
sahilmgandhi 18:6a4db94011d3 364 uint32_t RESERVED3[24];
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
sahilmgandhi 18:6a4db94011d3 366 uint32_t RESERVED4[56];
sahilmgandhi 18:6a4db94011d3 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
sahilmgandhi 18:6a4db94011d3 368 uint32_t RESERVED5[644];
sahilmgandhi 18:6a4db94011d3 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
sahilmgandhi 18:6a4db94011d3 370 } NVIC_Type;
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /* Software Triggered Interrupt Register Definitions */
sahilmgandhi 18:6a4db94011d3 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
sahilmgandhi 18:6a4db94011d3 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /*@} end of group CMSIS_NVIC */
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 380 \defgroup CMSIS_SCB System Control Block (SCB)
sahilmgandhi 18:6a4db94011d3 381 \brief Type definitions for the System Control Block Registers
sahilmgandhi 18:6a4db94011d3 382 @{
sahilmgandhi 18:6a4db94011d3 383 */
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /** \brief Structure type to access the System Control Block (SCB).
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387 typedef struct
sahilmgandhi 18:6a4db94011d3 388 {
sahilmgandhi 18:6a4db94011d3 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
sahilmgandhi 18:6a4db94011d3 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
sahilmgandhi 18:6a4db94011d3 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
sahilmgandhi 18:6a4db94011d3 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
sahilmgandhi 18:6a4db94011d3 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
sahilmgandhi 18:6a4db94011d3 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
sahilmgandhi 18:6a4db94011d3 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
sahilmgandhi 18:6a4db94011d3 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
sahilmgandhi 18:6a4db94011d3 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
sahilmgandhi 18:6a4db94011d3 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
sahilmgandhi 18:6a4db94011d3 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
sahilmgandhi 18:6a4db94011d3 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
sahilmgandhi 18:6a4db94011d3 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
sahilmgandhi 18:6a4db94011d3 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
sahilmgandhi 18:6a4db94011d3 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
sahilmgandhi 18:6a4db94011d3 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
sahilmgandhi 18:6a4db94011d3 408 uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
sahilmgandhi 18:6a4db94011d3 410 uint32_t RESERVED1[129];
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
sahilmgandhi 18:6a4db94011d3 412 } SCB_Type;
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 /* SCB CPUID Register Definitions */
sahilmgandhi 18:6a4db94011d3 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
sahilmgandhi 18:6a4db94011d3 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
sahilmgandhi 18:6a4db94011d3 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
sahilmgandhi 18:6a4db94011d3 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
sahilmgandhi 18:6a4db94011d3 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
sahilmgandhi 18:6a4db94011d3 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 /* SCB Interrupt Control State Register Definitions */
sahilmgandhi 18:6a4db94011d3 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
sahilmgandhi 18:6a4db94011d3 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
sahilmgandhi 18:6a4db94011d3 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
sahilmgandhi 18:6a4db94011d3 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
sahilmgandhi 18:6a4db94011d3 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
sahilmgandhi 18:6a4db94011d3 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
sahilmgandhi 18:6a4db94011d3 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
sahilmgandhi 18:6a4db94011d3 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
sahilmgandhi 18:6a4db94011d3 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
sahilmgandhi 18:6a4db94011d3 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
sahilmgandhi 18:6a4db94011d3 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* SCB Vector Table Offset Register Definitions */
sahilmgandhi 18:6a4db94011d3 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
sahilmgandhi 18:6a4db94011d3 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
sahilmgandhi 18:6a4db94011d3 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /* SCB Application Interrupt and Reset Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
sahilmgandhi 18:6a4db94011d3 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
sahilmgandhi 18:6a4db94011d3 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
sahilmgandhi 18:6a4db94011d3 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
sahilmgandhi 18:6a4db94011d3 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
sahilmgandhi 18:6a4db94011d3 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
sahilmgandhi 18:6a4db94011d3 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
sahilmgandhi 18:6a4db94011d3 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /* SCB System Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
sahilmgandhi 18:6a4db94011d3 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
sahilmgandhi 18:6a4db94011d3 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
sahilmgandhi 18:6a4db94011d3 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /* SCB Configuration Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
sahilmgandhi 18:6a4db94011d3 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
sahilmgandhi 18:6a4db94011d3 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
sahilmgandhi 18:6a4db94011d3 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
sahilmgandhi 18:6a4db94011d3 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
sahilmgandhi 18:6a4db94011d3 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
sahilmgandhi 18:6a4db94011d3 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 /* SCB System Handler Control and State Register Definitions */
sahilmgandhi 18:6a4db94011d3 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
sahilmgandhi 18:6a4db94011d3 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
sahilmgandhi 18:6a4db94011d3 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
sahilmgandhi 18:6a4db94011d3 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
sahilmgandhi 18:6a4db94011d3 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
sahilmgandhi 18:6a4db94011d3 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
sahilmgandhi 18:6a4db94011d3 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
sahilmgandhi 18:6a4db94011d3 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
sahilmgandhi 18:6a4db94011d3 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
sahilmgandhi 18:6a4db94011d3 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
sahilmgandhi 18:6a4db94011d3 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
sahilmgandhi 18:6a4db94011d3 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
sahilmgandhi 18:6a4db94011d3 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
sahilmgandhi 18:6a4db94011d3 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
sahilmgandhi 18:6a4db94011d3 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* SCB Configurable Fault Status Registers Definitions */
sahilmgandhi 18:6a4db94011d3 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
sahilmgandhi 18:6a4db94011d3 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
sahilmgandhi 18:6a4db94011d3 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
sahilmgandhi 18:6a4db94011d3 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* SCB Hard Fault Status Registers Definitions */
sahilmgandhi 18:6a4db94011d3 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
sahilmgandhi 18:6a4db94011d3 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
sahilmgandhi 18:6a4db94011d3 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
sahilmgandhi 18:6a4db94011d3 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 /* SCB Debug Fault Status Register Definitions */
sahilmgandhi 18:6a4db94011d3 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
sahilmgandhi 18:6a4db94011d3 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
sahilmgandhi 18:6a4db94011d3 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
sahilmgandhi 18:6a4db94011d3 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
sahilmgandhi 18:6a4db94011d3 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
sahilmgandhi 18:6a4db94011d3 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 /*@} end of group CMSIS_SCB */
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
sahilmgandhi 18:6a4db94011d3 603 \brief Type definitions for the System Control and ID Register not in the SCB
sahilmgandhi 18:6a4db94011d3 604 @{
sahilmgandhi 18:6a4db94011d3 605 */
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
sahilmgandhi 18:6a4db94011d3 608 */
sahilmgandhi 18:6a4db94011d3 609 typedef struct
sahilmgandhi 18:6a4db94011d3 610 {
sahilmgandhi 18:6a4db94011d3 611 uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
sahilmgandhi 18:6a4db94011d3 613 uint32_t RESERVED1[1];
sahilmgandhi 18:6a4db94011d3 614 } SCnSCB_Type;
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 /* Interrupt Controller Type Register Definitions */
sahilmgandhi 18:6a4db94011d3 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
sahilmgandhi 18:6a4db94011d3 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /*@} end of group CMSIS_SCnotSCB */
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
sahilmgandhi 18:6a4db94011d3 625 \brief Type definitions for the System Timer Registers.
sahilmgandhi 18:6a4db94011d3 626 @{
sahilmgandhi 18:6a4db94011d3 627 */
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /** \brief Structure type to access the System Timer (SysTick).
sahilmgandhi 18:6a4db94011d3 630 */
sahilmgandhi 18:6a4db94011d3 631 typedef struct
sahilmgandhi 18:6a4db94011d3 632 {
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
sahilmgandhi 18:6a4db94011d3 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
sahilmgandhi 18:6a4db94011d3 637 } SysTick_Type;
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 /* SysTick Control / Status Register Definitions */
sahilmgandhi 18:6a4db94011d3 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
sahilmgandhi 18:6a4db94011d3 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
sahilmgandhi 18:6a4db94011d3 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
sahilmgandhi 18:6a4db94011d3 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
sahilmgandhi 18:6a4db94011d3 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 /* SysTick Reload Register Definitions */
sahilmgandhi 18:6a4db94011d3 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
sahilmgandhi 18:6a4db94011d3 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /* SysTick Current Register Definitions */
sahilmgandhi 18:6a4db94011d3 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
sahilmgandhi 18:6a4db94011d3 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 /* SysTick Calibration Register Definitions */
sahilmgandhi 18:6a4db94011d3 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
sahilmgandhi 18:6a4db94011d3 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
sahilmgandhi 18:6a4db94011d3 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
sahilmgandhi 18:6a4db94011d3 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /*@} end of group CMSIS_SysTick */
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
sahilmgandhi 18:6a4db94011d3 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
sahilmgandhi 18:6a4db94011d3 676 @{
sahilmgandhi 18:6a4db94011d3 677 */
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
sahilmgandhi 18:6a4db94011d3 680 */
sahilmgandhi 18:6a4db94011d3 681 typedef struct
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 __O union
sahilmgandhi 18:6a4db94011d3 684 {
sahilmgandhi 18:6a4db94011d3 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
sahilmgandhi 18:6a4db94011d3 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
sahilmgandhi 18:6a4db94011d3 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
sahilmgandhi 18:6a4db94011d3 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
sahilmgandhi 18:6a4db94011d3 689 uint32_t RESERVED0[864];
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
sahilmgandhi 18:6a4db94011d3 691 uint32_t RESERVED1[15];
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
sahilmgandhi 18:6a4db94011d3 693 uint32_t RESERVED2[15];
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
sahilmgandhi 18:6a4db94011d3 695 uint32_t RESERVED3[29];
sahilmgandhi 18:6a4db94011d3 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
sahilmgandhi 18:6a4db94011d3 699 uint32_t RESERVED4[43];
sahilmgandhi 18:6a4db94011d3 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
sahilmgandhi 18:6a4db94011d3 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
sahilmgandhi 18:6a4db94011d3 702 uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
sahilmgandhi 18:6a4db94011d3 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
sahilmgandhi 18:6a4db94011d3 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
sahilmgandhi 18:6a4db94011d3 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
sahilmgandhi 18:6a4db94011d3 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
sahilmgandhi 18:6a4db94011d3 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
sahilmgandhi 18:6a4db94011d3 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
sahilmgandhi 18:6a4db94011d3 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
sahilmgandhi 18:6a4db94011d3 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
sahilmgandhi 18:6a4db94011d3 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
sahilmgandhi 18:6a4db94011d3 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
sahilmgandhi 18:6a4db94011d3 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
sahilmgandhi 18:6a4db94011d3 715 } ITM_Type;
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /* ITM Trace Privilege Register Definitions */
sahilmgandhi 18:6a4db94011d3 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
sahilmgandhi 18:6a4db94011d3 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 /* ITM Trace Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
sahilmgandhi 18:6a4db94011d3 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
sahilmgandhi 18:6a4db94011d3 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
sahilmgandhi 18:6a4db94011d3 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
sahilmgandhi 18:6a4db94011d3 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
sahilmgandhi 18:6a4db94011d3 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
sahilmgandhi 18:6a4db94011d3 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
sahilmgandhi 18:6a4db94011d3 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
sahilmgandhi 18:6a4db94011d3 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
sahilmgandhi 18:6a4db94011d3 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 /* ITM Integration Write Register Definitions */
sahilmgandhi 18:6a4db94011d3 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
sahilmgandhi 18:6a4db94011d3 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 /* ITM Integration Read Register Definitions */
sahilmgandhi 18:6a4db94011d3 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
sahilmgandhi 18:6a4db94011d3 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
sahilmgandhi 18:6a4db94011d3 756
sahilmgandhi 18:6a4db94011d3 757 /* ITM Integration Mode Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
sahilmgandhi 18:6a4db94011d3 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /* ITM Lock Status Register Definitions */
sahilmgandhi 18:6a4db94011d3 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
sahilmgandhi 18:6a4db94011d3 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
sahilmgandhi 18:6a4db94011d3 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
sahilmgandhi 18:6a4db94011d3 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 /*@}*/ /* end of group CMSIS_ITM */
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
sahilmgandhi 18:6a4db94011d3 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
sahilmgandhi 18:6a4db94011d3 777 @{
sahilmgandhi 18:6a4db94011d3 778 */
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
sahilmgandhi 18:6a4db94011d3 781 */
sahilmgandhi 18:6a4db94011d3 782 typedef struct
sahilmgandhi 18:6a4db94011d3 783 {
sahilmgandhi 18:6a4db94011d3 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
sahilmgandhi 18:6a4db94011d3 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
sahilmgandhi 18:6a4db94011d3 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
sahilmgandhi 18:6a4db94011d3 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
sahilmgandhi 18:6a4db94011d3 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
sahilmgandhi 18:6a4db94011d3 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
sahilmgandhi 18:6a4db94011d3 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
sahilmgandhi 18:6a4db94011d3 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
sahilmgandhi 18:6a4db94011d3 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
sahilmgandhi 18:6a4db94011d3 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
sahilmgandhi 18:6a4db94011d3 795 uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
sahilmgandhi 18:6a4db94011d3 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
sahilmgandhi 18:6a4db94011d3 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
sahilmgandhi 18:6a4db94011d3 799 uint32_t RESERVED1[1];
sahilmgandhi 18:6a4db94011d3 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
sahilmgandhi 18:6a4db94011d3 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
sahilmgandhi 18:6a4db94011d3 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
sahilmgandhi 18:6a4db94011d3 803 uint32_t RESERVED2[1];
sahilmgandhi 18:6a4db94011d3 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
sahilmgandhi 18:6a4db94011d3 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
sahilmgandhi 18:6a4db94011d3 807 } DWT_Type;
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 /* DWT Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
sahilmgandhi 18:6a4db94011d3 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
sahilmgandhi 18:6a4db94011d3 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
sahilmgandhi 18:6a4db94011d3 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
sahilmgandhi 18:6a4db94011d3 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
sahilmgandhi 18:6a4db94011d3 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
sahilmgandhi 18:6a4db94011d3 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
sahilmgandhi 18:6a4db94011d3 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
sahilmgandhi 18:6a4db94011d3 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
sahilmgandhi 18:6a4db94011d3 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
sahilmgandhi 18:6a4db94011d3 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
sahilmgandhi 18:6a4db94011d3 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
sahilmgandhi 18:6a4db94011d3 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
sahilmgandhi 18:6a4db94011d3 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
sahilmgandhi 18:6a4db94011d3 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
sahilmgandhi 18:6a4db94011d3 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
sahilmgandhi 18:6a4db94011d3 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
sahilmgandhi 18:6a4db94011d3 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
sahilmgandhi 18:6a4db94011d3 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 /* DWT CPI Count Register Definitions */
sahilmgandhi 18:6a4db94011d3 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
sahilmgandhi 18:6a4db94011d3 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /* DWT Exception Overhead Count Register Definitions */
sahilmgandhi 18:6a4db94011d3 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
sahilmgandhi 18:6a4db94011d3 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
sahilmgandhi 18:6a4db94011d3 871
sahilmgandhi 18:6a4db94011d3 872 /* DWT Sleep Count Register Definitions */
sahilmgandhi 18:6a4db94011d3 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
sahilmgandhi 18:6a4db94011d3 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /* DWT LSU Count Register Definitions */
sahilmgandhi 18:6a4db94011d3 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
sahilmgandhi 18:6a4db94011d3 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 /* DWT Folded-instruction Count Register Definitions */
sahilmgandhi 18:6a4db94011d3 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
sahilmgandhi 18:6a4db94011d3 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /* DWT Comparator Mask Register Definitions */
sahilmgandhi 18:6a4db94011d3 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
sahilmgandhi 18:6a4db94011d3 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 /* DWT Comparator Function Register Definitions */
sahilmgandhi 18:6a4db94011d3 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
sahilmgandhi 18:6a4db94011d3 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
sahilmgandhi 18:6a4db94011d3 891
sahilmgandhi 18:6a4db94011d3 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
sahilmgandhi 18:6a4db94011d3 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
sahilmgandhi 18:6a4db94011d3 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
sahilmgandhi 18:6a4db94011d3 897
sahilmgandhi 18:6a4db94011d3 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
sahilmgandhi 18:6a4db94011d3 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
sahilmgandhi 18:6a4db94011d3 900
sahilmgandhi 18:6a4db94011d3 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
sahilmgandhi 18:6a4db94011d3 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
sahilmgandhi 18:6a4db94011d3 903
sahilmgandhi 18:6a4db94011d3 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
sahilmgandhi 18:6a4db94011d3 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
sahilmgandhi 18:6a4db94011d3 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
sahilmgandhi 18:6a4db94011d3 909
sahilmgandhi 18:6a4db94011d3 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
sahilmgandhi 18:6a4db94011d3 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
sahilmgandhi 18:6a4db94011d3 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /*@}*/ /* end of group CMSIS_DWT */
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
sahilmgandhi 18:6a4db94011d3 921 \brief Type definitions for the Trace Port Interface (TPI)
sahilmgandhi 18:6a4db94011d3 922 @{
sahilmgandhi 18:6a4db94011d3 923 */
sahilmgandhi 18:6a4db94011d3 924
sahilmgandhi 18:6a4db94011d3 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
sahilmgandhi 18:6a4db94011d3 926 */
sahilmgandhi 18:6a4db94011d3 927 typedef struct
sahilmgandhi 18:6a4db94011d3 928 {
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
sahilmgandhi 18:6a4db94011d3 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
sahilmgandhi 18:6a4db94011d3 931 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
sahilmgandhi 18:6a4db94011d3 933 uint32_t RESERVED1[55];
sahilmgandhi 18:6a4db94011d3 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
sahilmgandhi 18:6a4db94011d3 935 uint32_t RESERVED2[131];
sahilmgandhi 18:6a4db94011d3 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
sahilmgandhi 18:6a4db94011d3 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
sahilmgandhi 18:6a4db94011d3 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
sahilmgandhi 18:6a4db94011d3 939 uint32_t RESERVED3[759];
sahilmgandhi 18:6a4db94011d3 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
sahilmgandhi 18:6a4db94011d3 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
sahilmgandhi 18:6a4db94011d3 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
sahilmgandhi 18:6a4db94011d3 943 uint32_t RESERVED4[1];
sahilmgandhi 18:6a4db94011d3 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
sahilmgandhi 18:6a4db94011d3 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
sahilmgandhi 18:6a4db94011d3 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
sahilmgandhi 18:6a4db94011d3 947 uint32_t RESERVED5[39];
sahilmgandhi 18:6a4db94011d3 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
sahilmgandhi 18:6a4db94011d3 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
sahilmgandhi 18:6a4db94011d3 950 uint32_t RESERVED7[8];
sahilmgandhi 18:6a4db94011d3 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
sahilmgandhi 18:6a4db94011d3 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
sahilmgandhi 18:6a4db94011d3 953 } TPI_Type;
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
sahilmgandhi 18:6a4db94011d3 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
sahilmgandhi 18:6a4db94011d3 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 /* TPI Selected Pin Protocol Register Definitions */
sahilmgandhi 18:6a4db94011d3 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
sahilmgandhi 18:6a4db94011d3 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /* TPI Formatter and Flush Status Register Definitions */
sahilmgandhi 18:6a4db94011d3 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
sahilmgandhi 18:6a4db94011d3 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
sahilmgandhi 18:6a4db94011d3 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
sahilmgandhi 18:6a4db94011d3 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
sahilmgandhi 18:6a4db94011d3 972
sahilmgandhi 18:6a4db94011d3 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
sahilmgandhi 18:6a4db94011d3 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /* TPI Formatter and Flush Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
sahilmgandhi 18:6a4db94011d3 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
sahilmgandhi 18:6a4db94011d3 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
sahilmgandhi 18:6a4db94011d3 982
sahilmgandhi 18:6a4db94011d3 983 /* TPI TRIGGER Register Definitions */
sahilmgandhi 18:6a4db94011d3 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
sahilmgandhi 18:6a4db94011d3 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
sahilmgandhi 18:6a4db94011d3 986
sahilmgandhi 18:6a4db94011d3 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
sahilmgandhi 18:6a4db94011d3 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
sahilmgandhi 18:6a4db94011d3 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
sahilmgandhi 18:6a4db94011d3 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
sahilmgandhi 18:6a4db94011d3 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
sahilmgandhi 18:6a4db94011d3 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
sahilmgandhi 18:6a4db94011d3 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
sahilmgandhi 18:6a4db94011d3 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
sahilmgandhi 18:6a4db94011d3 1005
sahilmgandhi 18:6a4db94011d3 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
sahilmgandhi 18:6a4db94011d3 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 /* TPI ITATBCTR2 Register Definitions */
sahilmgandhi 18:6a4db94011d3 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
sahilmgandhi 18:6a4db94011d3 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
sahilmgandhi 18:6a4db94011d3 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
sahilmgandhi 18:6a4db94011d3 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
sahilmgandhi 18:6a4db94011d3 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
sahilmgandhi 18:6a4db94011d3 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
sahilmgandhi 18:6a4db94011d3 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
sahilmgandhi 18:6a4db94011d3 1025
sahilmgandhi 18:6a4db94011d3 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
sahilmgandhi 18:6a4db94011d3 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
sahilmgandhi 18:6a4db94011d3 1028
sahilmgandhi 18:6a4db94011d3 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
sahilmgandhi 18:6a4db94011d3 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
sahilmgandhi 18:6a4db94011d3 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 /* TPI ITATBCTR0 Register Definitions */
sahilmgandhi 18:6a4db94011d3 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
sahilmgandhi 18:6a4db94011d3 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /* TPI Integration Mode Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
sahilmgandhi 18:6a4db94011d3 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
sahilmgandhi 18:6a4db94011d3 1042
sahilmgandhi 18:6a4db94011d3 1043 /* TPI DEVID Register Definitions */
sahilmgandhi 18:6a4db94011d3 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
sahilmgandhi 18:6a4db94011d3 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
sahilmgandhi 18:6a4db94011d3 1046
sahilmgandhi 18:6a4db94011d3 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
sahilmgandhi 18:6a4db94011d3 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
sahilmgandhi 18:6a4db94011d3 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
sahilmgandhi 18:6a4db94011d3 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
sahilmgandhi 18:6a4db94011d3 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
sahilmgandhi 18:6a4db94011d3 1058
sahilmgandhi 18:6a4db94011d3 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
sahilmgandhi 18:6a4db94011d3 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /* TPI DEVTYPE Register Definitions */
sahilmgandhi 18:6a4db94011d3 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
sahilmgandhi 18:6a4db94011d3 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
sahilmgandhi 18:6a4db94011d3 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /*@}*/ /* end of group CMSIS_TPI */
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 1073 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
sahilmgandhi 18:6a4db94011d3 1075 \brief Type definitions for the Memory Protection Unit (MPU)
sahilmgandhi 18:6a4db94011d3 1076 @{
sahilmgandhi 18:6a4db94011d3 1077 */
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
sahilmgandhi 18:6a4db94011d3 1080 */
sahilmgandhi 18:6a4db94011d3 1081 typedef struct
sahilmgandhi 18:6a4db94011d3 1082 {
sahilmgandhi 18:6a4db94011d3 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
sahilmgandhi 18:6a4db94011d3 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
sahilmgandhi 18:6a4db94011d3 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
sahilmgandhi 18:6a4db94011d3 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 1094 } MPU_Type;
sahilmgandhi 18:6a4db94011d3 1095
sahilmgandhi 18:6a4db94011d3 1096 /* MPU Type Register */
sahilmgandhi 18:6a4db94011d3 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
sahilmgandhi 18:6a4db94011d3 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
sahilmgandhi 18:6a4db94011d3 1099
sahilmgandhi 18:6a4db94011d3 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
sahilmgandhi 18:6a4db94011d3 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
sahilmgandhi 18:6a4db94011d3 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
sahilmgandhi 18:6a4db94011d3 1105
sahilmgandhi 18:6a4db94011d3 1106 /* MPU Control Register */
sahilmgandhi 18:6a4db94011d3 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
sahilmgandhi 18:6a4db94011d3 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
sahilmgandhi 18:6a4db94011d3 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
sahilmgandhi 18:6a4db94011d3 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
sahilmgandhi 18:6a4db94011d3 1115
sahilmgandhi 18:6a4db94011d3 1116 /* MPU Region Number Register */
sahilmgandhi 18:6a4db94011d3 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
sahilmgandhi 18:6a4db94011d3 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /* MPU Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
sahilmgandhi 18:6a4db94011d3 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
sahilmgandhi 18:6a4db94011d3 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
sahilmgandhi 18:6a4db94011d3 1126
sahilmgandhi 18:6a4db94011d3 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
sahilmgandhi 18:6a4db94011d3 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130 /* MPU Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
sahilmgandhi 18:6a4db94011d3 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
sahilmgandhi 18:6a4db94011d3 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
sahilmgandhi 18:6a4db94011d3 1136
sahilmgandhi 18:6a4db94011d3 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
sahilmgandhi 18:6a4db94011d3 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
sahilmgandhi 18:6a4db94011d3 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
sahilmgandhi 18:6a4db94011d3 1142
sahilmgandhi 18:6a4db94011d3 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
sahilmgandhi 18:6a4db94011d3 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
sahilmgandhi 18:6a4db94011d3 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
sahilmgandhi 18:6a4db94011d3 1148
sahilmgandhi 18:6a4db94011d3 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
sahilmgandhi 18:6a4db94011d3 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
sahilmgandhi 18:6a4db94011d3 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
sahilmgandhi 18:6a4db94011d3 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
sahilmgandhi 18:6a4db94011d3 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /*@} end of group CMSIS_MPU */
sahilmgandhi 18:6a4db94011d3 1162 #endif
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
sahilmgandhi 18:6a4db94011d3 1167 \brief Type definitions for the Core Debug Registers
sahilmgandhi 18:6a4db94011d3 1168 @{
sahilmgandhi 18:6a4db94011d3 1169 */
sahilmgandhi 18:6a4db94011d3 1170
sahilmgandhi 18:6a4db94011d3 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
sahilmgandhi 18:6a4db94011d3 1172 */
sahilmgandhi 18:6a4db94011d3 1173 typedef struct
sahilmgandhi 18:6a4db94011d3 1174 {
sahilmgandhi 18:6a4db94011d3 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
sahilmgandhi 18:6a4db94011d3 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
sahilmgandhi 18:6a4db94011d3 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
sahilmgandhi 18:6a4db94011d3 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
sahilmgandhi 18:6a4db94011d3 1179 } CoreDebug_Type;
sahilmgandhi 18:6a4db94011d3 1180
sahilmgandhi 18:6a4db94011d3 1181 /* Debug Halting Control and Status Register */
sahilmgandhi 18:6a4db94011d3 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
sahilmgandhi 18:6a4db94011d3 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
sahilmgandhi 18:6a4db94011d3 1184
sahilmgandhi 18:6a4db94011d3 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
sahilmgandhi 18:6a4db94011d3 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
sahilmgandhi 18:6a4db94011d3 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
sahilmgandhi 18:6a4db94011d3 1190
sahilmgandhi 18:6a4db94011d3 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
sahilmgandhi 18:6a4db94011d3 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
sahilmgandhi 18:6a4db94011d3 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
sahilmgandhi 18:6a4db94011d3 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
sahilmgandhi 18:6a4db94011d3 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
sahilmgandhi 18:6a4db94011d3 1202
sahilmgandhi 18:6a4db94011d3 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
sahilmgandhi 18:6a4db94011d3 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
sahilmgandhi 18:6a4db94011d3 1205
sahilmgandhi 18:6a4db94011d3 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
sahilmgandhi 18:6a4db94011d3 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
sahilmgandhi 18:6a4db94011d3 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
sahilmgandhi 18:6a4db94011d3 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
sahilmgandhi 18:6a4db94011d3 1214
sahilmgandhi 18:6a4db94011d3 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
sahilmgandhi 18:6a4db94011d3 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
sahilmgandhi 18:6a4db94011d3 1217
sahilmgandhi 18:6a4db94011d3 1218 /* Debug Core Register Selector Register */
sahilmgandhi 18:6a4db94011d3 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
sahilmgandhi 18:6a4db94011d3 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
sahilmgandhi 18:6a4db94011d3 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
sahilmgandhi 18:6a4db94011d3 1224
sahilmgandhi 18:6a4db94011d3 1225 /* Debug Exception and Monitor Control Register */
sahilmgandhi 18:6a4db94011d3 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
sahilmgandhi 18:6a4db94011d3 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
sahilmgandhi 18:6a4db94011d3 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
sahilmgandhi 18:6a4db94011d3 1231
sahilmgandhi 18:6a4db94011d3 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
sahilmgandhi 18:6a4db94011d3 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
sahilmgandhi 18:6a4db94011d3 1234
sahilmgandhi 18:6a4db94011d3 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
sahilmgandhi 18:6a4db94011d3 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
sahilmgandhi 18:6a4db94011d3 1237
sahilmgandhi 18:6a4db94011d3 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
sahilmgandhi 18:6a4db94011d3 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
sahilmgandhi 18:6a4db94011d3 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
sahilmgandhi 18:6a4db94011d3 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
sahilmgandhi 18:6a4db94011d3 1246
sahilmgandhi 18:6a4db94011d3 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
sahilmgandhi 18:6a4db94011d3 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
sahilmgandhi 18:6a4db94011d3 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
sahilmgandhi 18:6a4db94011d3 1252
sahilmgandhi 18:6a4db94011d3 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
sahilmgandhi 18:6a4db94011d3 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
sahilmgandhi 18:6a4db94011d3 1255
sahilmgandhi 18:6a4db94011d3 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
sahilmgandhi 18:6a4db94011d3 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
sahilmgandhi 18:6a4db94011d3 1258
sahilmgandhi 18:6a4db94011d3 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
sahilmgandhi 18:6a4db94011d3 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
sahilmgandhi 18:6a4db94011d3 1261
sahilmgandhi 18:6a4db94011d3 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
sahilmgandhi 18:6a4db94011d3 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
sahilmgandhi 18:6a4db94011d3 1264
sahilmgandhi 18:6a4db94011d3 1265 /*@} end of group CMSIS_CoreDebug */
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267
sahilmgandhi 18:6a4db94011d3 1268 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 1269 \defgroup CMSIS_core_base Core Definitions
sahilmgandhi 18:6a4db94011d3 1270 \brief Definitions for base addresses, unions, and structures.
sahilmgandhi 18:6a4db94011d3 1271 @{
sahilmgandhi 18:6a4db94011d3 1272 */
sahilmgandhi 18:6a4db94011d3 1273
sahilmgandhi 18:6a4db94011d3 1274 /* Memory mapping of Cortex-M3 Hardware */
sahilmgandhi 18:6a4db94011d3 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
sahilmgandhi 18:6a4db94011d3 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
sahilmgandhi 18:6a4db94011d3 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
sahilmgandhi 18:6a4db94011d3 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
sahilmgandhi 18:6a4db94011d3 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
sahilmgandhi 18:6a4db94011d3 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
sahilmgandhi 18:6a4db94011d3 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
sahilmgandhi 18:6a4db94011d3 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
sahilmgandhi 18:6a4db94011d3 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
sahilmgandhi 18:6a4db94011d3 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
sahilmgandhi 18:6a4db94011d3 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
sahilmgandhi 18:6a4db94011d3 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
sahilmgandhi 18:6a4db94011d3 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
sahilmgandhi 18:6a4db94011d3 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
sahilmgandhi 18:6a4db94011d3 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
sahilmgandhi 18:6a4db94011d3 1292
sahilmgandhi 18:6a4db94011d3 1293 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
sahilmgandhi 18:6a4db94011d3 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
sahilmgandhi 18:6a4db94011d3 1296 #endif
sahilmgandhi 18:6a4db94011d3 1297
sahilmgandhi 18:6a4db94011d3 1298 /*@} */
sahilmgandhi 18:6a4db94011d3 1299
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301
sahilmgandhi 18:6a4db94011d3 1302 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 1303 * Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 1304 Core Function Interface contains:
sahilmgandhi 18:6a4db94011d3 1305 - Core NVIC Functions
sahilmgandhi 18:6a4db94011d3 1306 - Core SysTick Functions
sahilmgandhi 18:6a4db94011d3 1307 - Core Debug Functions
sahilmgandhi 18:6a4db94011d3 1308 - Core Register Access Functions
sahilmgandhi 18:6a4db94011d3 1309 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
sahilmgandhi 18:6a4db94011d3 1311 */
sahilmgandhi 18:6a4db94011d3 1312
sahilmgandhi 18:6a4db94011d3 1313
sahilmgandhi 18:6a4db94011d3 1314
sahilmgandhi 18:6a4db94011d3 1315 /* ########################## NVIC functions #################################### */
sahilmgandhi 18:6a4db94011d3 1316 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
sahilmgandhi 18:6a4db94011d3 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
sahilmgandhi 18:6a4db94011d3 1319 @{
sahilmgandhi 18:6a4db94011d3 1320 */
sahilmgandhi 18:6a4db94011d3 1321
sahilmgandhi 18:6a4db94011d3 1322 /** \brief Set Priority Grouping
sahilmgandhi 18:6a4db94011d3 1323
sahilmgandhi 18:6a4db94011d3 1324 The function sets the priority grouping field using the required unlock sequence.
sahilmgandhi 18:6a4db94011d3 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
sahilmgandhi 18:6a4db94011d3 1326 Only values from 0..7 are used.
sahilmgandhi 18:6a4db94011d3 1327 In case of a conflict between priority grouping and available
sahilmgandhi 18:6a4db94011d3 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
sahilmgandhi 18:6a4db94011d3 1329
sahilmgandhi 18:6a4db94011d3 1330 \param [in] PriorityGroup Priority grouping field.
sahilmgandhi 18:6a4db94011d3 1331 */
sahilmgandhi 18:6a4db94011d3 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
sahilmgandhi 18:6a4db94011d3 1333 {
sahilmgandhi 18:6a4db94011d3 1334 uint32_t reg_value;
sahilmgandhi 18:6a4db94011d3 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi 18:6a4db94011d3 1336
sahilmgandhi 18:6a4db94011d3 1337 reg_value = SCB->AIRCR; /* read old register configuration */
sahilmgandhi 18:6a4db94011d3 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
sahilmgandhi 18:6a4db94011d3 1339 reg_value = (reg_value |
sahilmgandhi 18:6a4db94011d3 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
sahilmgandhi 18:6a4db94011d3 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
sahilmgandhi 18:6a4db94011d3 1342 SCB->AIRCR = reg_value;
sahilmgandhi 18:6a4db94011d3 1343 }
sahilmgandhi 18:6a4db94011d3 1344
sahilmgandhi 18:6a4db94011d3 1345
sahilmgandhi 18:6a4db94011d3 1346 /** \brief Get Priority Grouping
sahilmgandhi 18:6a4db94011d3 1347
sahilmgandhi 18:6a4db94011d3 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
sahilmgandhi 18:6a4db94011d3 1351 */
sahilmgandhi 18:6a4db94011d3 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
sahilmgandhi 18:6a4db94011d3 1353 {
sahilmgandhi 18:6a4db94011d3 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
sahilmgandhi 18:6a4db94011d3 1355 }
sahilmgandhi 18:6a4db94011d3 1356
sahilmgandhi 18:6a4db94011d3 1357
sahilmgandhi 18:6a4db94011d3 1358 /** \brief Enable External Interrupt
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 1361
sahilmgandhi 18:6a4db94011d3 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 1363 */
sahilmgandhi 18:6a4db94011d3 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1365 {
sahilmgandhi 18:6a4db94011d3 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 1367 }
sahilmgandhi 18:6a4db94011d3 1368
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 /** \brief Disable External Interrupt
sahilmgandhi 18:6a4db94011d3 1371
sahilmgandhi 18:6a4db94011d3 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 1373
sahilmgandhi 18:6a4db94011d3 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 1375 */
sahilmgandhi 18:6a4db94011d3 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1377 {
sahilmgandhi 18:6a4db94011d3 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 1379 __DSB();
sahilmgandhi 18:6a4db94011d3 1380 __ISB();
sahilmgandhi 18:6a4db94011d3 1381 }
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383
sahilmgandhi 18:6a4db94011d3 1384 /** \brief Get Pending Interrupt
sahilmgandhi 18:6a4db94011d3 1385
sahilmgandhi 18:6a4db94011d3 1386 The function reads the pending register in the NVIC and returns the pending bit
sahilmgandhi 18:6a4db94011d3 1387 for the specified interrupt.
sahilmgandhi 18:6a4db94011d3 1388
sahilmgandhi 18:6a4db94011d3 1389 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 1390
sahilmgandhi 18:6a4db94011d3 1391 \return 0 Interrupt status is not pending.
sahilmgandhi 18:6a4db94011d3 1392 \return 1 Interrupt status is pending.
sahilmgandhi 18:6a4db94011d3 1393 */
sahilmgandhi 18:6a4db94011d3 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1395 {
sahilmgandhi 18:6a4db94011d3 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
sahilmgandhi 18:6a4db94011d3 1397 }
sahilmgandhi 18:6a4db94011d3 1398
sahilmgandhi 18:6a4db94011d3 1399
sahilmgandhi 18:6a4db94011d3 1400 /** \brief Set Pending Interrupt
sahilmgandhi 18:6a4db94011d3 1401
sahilmgandhi 18:6a4db94011d3 1402 The function sets the pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 1403
sahilmgandhi 18:6a4db94011d3 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 1405 */
sahilmgandhi 18:6a4db94011d3 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1407 {
sahilmgandhi 18:6a4db94011d3 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 1409 }
sahilmgandhi 18:6a4db94011d3 1410
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 /** \brief Clear Pending Interrupt
sahilmgandhi 18:6a4db94011d3 1413
sahilmgandhi 18:6a4db94011d3 1414 The function clears the pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 1415
sahilmgandhi 18:6a4db94011d3 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 1417 */
sahilmgandhi 18:6a4db94011d3 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1419 {
sahilmgandhi 18:6a4db94011d3 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 1421 }
sahilmgandhi 18:6a4db94011d3 1422
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 /** \brief Get Active Interrupt
sahilmgandhi 18:6a4db94011d3 1425
sahilmgandhi 18:6a4db94011d3 1426 The function reads the active register in NVIC and returns the active bit.
sahilmgandhi 18:6a4db94011d3 1427
sahilmgandhi 18:6a4db94011d3 1428 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 1429
sahilmgandhi 18:6a4db94011d3 1430 \return 0 Interrupt status is not active.
sahilmgandhi 18:6a4db94011d3 1431 \return 1 Interrupt status is active.
sahilmgandhi 18:6a4db94011d3 1432 */
sahilmgandhi 18:6a4db94011d3 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1434 {
sahilmgandhi 18:6a4db94011d3 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
sahilmgandhi 18:6a4db94011d3 1436 }
sahilmgandhi 18:6a4db94011d3 1437
sahilmgandhi 18:6a4db94011d3 1438
sahilmgandhi 18:6a4db94011d3 1439 /** \brief Set Interrupt Priority
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441 The function sets the priority of an interrupt.
sahilmgandhi 18:6a4db94011d3 1442
sahilmgandhi 18:6a4db94011d3 1443 \note The priority cannot be set for every core interrupt.
sahilmgandhi 18:6a4db94011d3 1444
sahilmgandhi 18:6a4db94011d3 1445 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 1446 \param [in] priority Priority to set.
sahilmgandhi 18:6a4db94011d3 1447 */
sahilmgandhi 18:6a4db94011d3 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
sahilmgandhi 18:6a4db94011d3 1449 {
sahilmgandhi 18:6a4db94011d3 1450 if((int32_t)IRQn < 0) {
sahilmgandhi 18:6a4db94011d3 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
sahilmgandhi 18:6a4db94011d3 1452 }
sahilmgandhi 18:6a4db94011d3 1453 else {
sahilmgandhi 18:6a4db94011d3 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
sahilmgandhi 18:6a4db94011d3 1455 }
sahilmgandhi 18:6a4db94011d3 1456 }
sahilmgandhi 18:6a4db94011d3 1457
sahilmgandhi 18:6a4db94011d3 1458
sahilmgandhi 18:6a4db94011d3 1459 /** \brief Get Interrupt Priority
sahilmgandhi 18:6a4db94011d3 1460
sahilmgandhi 18:6a4db94011d3 1461 The function reads the priority of an interrupt. The interrupt
sahilmgandhi 18:6a4db94011d3 1462 number can be positive to specify an external (device specific)
sahilmgandhi 18:6a4db94011d3 1463 interrupt, or negative to specify an internal (core) interrupt.
sahilmgandhi 18:6a4db94011d3 1464
sahilmgandhi 18:6a4db94011d3 1465
sahilmgandhi 18:6a4db94011d3 1466 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
sahilmgandhi 18:6a4db94011d3 1468 priority bits of the microcontroller.
sahilmgandhi 18:6a4db94011d3 1469 */
sahilmgandhi 18:6a4db94011d3 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 1471 {
sahilmgandhi 18:6a4db94011d3 1472
sahilmgandhi 18:6a4db94011d3 1473 if((int32_t)IRQn < 0) {
sahilmgandhi 18:6a4db94011d3 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi 18:6a4db94011d3 1475 }
sahilmgandhi 18:6a4db94011d3 1476 else {
sahilmgandhi 18:6a4db94011d3 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi 18:6a4db94011d3 1478 }
sahilmgandhi 18:6a4db94011d3 1479 }
sahilmgandhi 18:6a4db94011d3 1480
sahilmgandhi 18:6a4db94011d3 1481
sahilmgandhi 18:6a4db94011d3 1482 /** \brief Encode Priority
sahilmgandhi 18:6a4db94011d3 1483
sahilmgandhi 18:6a4db94011d3 1484 The function encodes the priority for an interrupt with the given priority group,
sahilmgandhi 18:6a4db94011d3 1485 preemptive priority value, and subpriority value.
sahilmgandhi 18:6a4db94011d3 1486 In case of a conflict between priority grouping and available
sahilmgandhi 18:6a4db94011d3 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
sahilmgandhi 18:6a4db94011d3 1488
sahilmgandhi 18:6a4db94011d3 1489 \param [in] PriorityGroup Used priority group.
sahilmgandhi 18:6a4db94011d3 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 1491 \param [in] SubPriority Subpriority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
sahilmgandhi 18:6a4db94011d3 1493 */
sahilmgandhi 18:6a4db94011d3 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
sahilmgandhi 18:6a4db94011d3 1495 {
sahilmgandhi 18:6a4db94011d3 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi 18:6a4db94011d3 1497 uint32_t PreemptPriorityBits;
sahilmgandhi 18:6a4db94011d3 1498 uint32_t SubPriorityBits;
sahilmgandhi 18:6a4db94011d3 1499
sahilmgandhi 18:6a4db94011d3 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
sahilmgandhi 18:6a4db94011d3 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
sahilmgandhi 18:6a4db94011d3 1502
sahilmgandhi 18:6a4db94011d3 1503 return (
sahilmgandhi 18:6a4db94011d3 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
sahilmgandhi 18:6a4db94011d3 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
sahilmgandhi 18:6a4db94011d3 1506 );
sahilmgandhi 18:6a4db94011d3 1507 }
sahilmgandhi 18:6a4db94011d3 1508
sahilmgandhi 18:6a4db94011d3 1509
sahilmgandhi 18:6a4db94011d3 1510 /** \brief Decode Priority
sahilmgandhi 18:6a4db94011d3 1511
sahilmgandhi 18:6a4db94011d3 1512 The function decodes an interrupt priority value with a given priority group to
sahilmgandhi 18:6a4db94011d3 1513 preemptive priority value and subpriority value.
sahilmgandhi 18:6a4db94011d3 1514 In case of a conflict between priority grouping and available
sahilmgandhi 18:6a4db94011d3 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
sahilmgandhi 18:6a4db94011d3 1516
sahilmgandhi 18:6a4db94011d3 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
sahilmgandhi 18:6a4db94011d3 1518 \param [in] PriorityGroup Used priority group.
sahilmgandhi 18:6a4db94011d3 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 1520 \param [out] pSubPriority Subpriority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 1521 */
sahilmgandhi 18:6a4db94011d3 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
sahilmgandhi 18:6a4db94011d3 1523 {
sahilmgandhi 18:6a4db94011d3 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi 18:6a4db94011d3 1525 uint32_t PreemptPriorityBits;
sahilmgandhi 18:6a4db94011d3 1526 uint32_t SubPriorityBits;
sahilmgandhi 18:6a4db94011d3 1527
sahilmgandhi 18:6a4db94011d3 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
sahilmgandhi 18:6a4db94011d3 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
sahilmgandhi 18:6a4db94011d3 1530
sahilmgandhi 18:6a4db94011d3 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
sahilmgandhi 18:6a4db94011d3 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
sahilmgandhi 18:6a4db94011d3 1533 }
sahilmgandhi 18:6a4db94011d3 1534
sahilmgandhi 18:6a4db94011d3 1535
sahilmgandhi 18:6a4db94011d3 1536 /** \brief System Reset
sahilmgandhi 18:6a4db94011d3 1537
sahilmgandhi 18:6a4db94011d3 1538 The function initiates a system reset request to reset the MCU.
sahilmgandhi 18:6a4db94011d3 1539 */
sahilmgandhi 18:6a4db94011d3 1540 __STATIC_INLINE void NVIC_SystemReset(void)
sahilmgandhi 18:6a4db94011d3 1541 {
sahilmgandhi 18:6a4db94011d3 1542 __DSB(); /* Ensure all outstanding memory accesses included
sahilmgandhi 18:6a4db94011d3 1543 buffered write are completed before reset */
sahilmgandhi 18:6a4db94011d3 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
sahilmgandhi 18:6a4db94011d3 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
sahilmgandhi 18:6a4db94011d3 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
sahilmgandhi 18:6a4db94011d3 1547 __DSB(); /* Ensure completion of memory access */
sahilmgandhi 18:6a4db94011d3 1548 while(1) { __NOP(); } /* wait until reset */
sahilmgandhi 18:6a4db94011d3 1549 }
sahilmgandhi 18:6a4db94011d3 1550
sahilmgandhi 18:6a4db94011d3 1551 /*@} end of CMSIS_Core_NVICFunctions */
sahilmgandhi 18:6a4db94011d3 1552
sahilmgandhi 18:6a4db94011d3 1553
sahilmgandhi 18:6a4db94011d3 1554
sahilmgandhi 18:6a4db94011d3 1555 /* ################################## SysTick function ############################################ */
sahilmgandhi 18:6a4db94011d3 1556 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
sahilmgandhi 18:6a4db94011d3 1558 \brief Functions that configure the System.
sahilmgandhi 18:6a4db94011d3 1559 @{
sahilmgandhi 18:6a4db94011d3 1560 */
sahilmgandhi 18:6a4db94011d3 1561
sahilmgandhi 18:6a4db94011d3 1562 #if (__Vendor_SysTickConfig == 0)
sahilmgandhi 18:6a4db94011d3 1563
sahilmgandhi 18:6a4db94011d3 1564 /** \brief System Tick Configuration
sahilmgandhi 18:6a4db94011d3 1565
sahilmgandhi 18:6a4db94011d3 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
sahilmgandhi 18:6a4db94011d3 1567 Counter is in free running mode to generate periodic interrupts.
sahilmgandhi 18:6a4db94011d3 1568
sahilmgandhi 18:6a4db94011d3 1569 \param [in] ticks Number of ticks between two interrupts.
sahilmgandhi 18:6a4db94011d3 1570
sahilmgandhi 18:6a4db94011d3 1571 \return 0 Function succeeded.
sahilmgandhi 18:6a4db94011d3 1572 \return 1 Function failed.
sahilmgandhi 18:6a4db94011d3 1573
sahilmgandhi 18:6a4db94011d3 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
sahilmgandhi 18:6a4db94011d3 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
sahilmgandhi 18:6a4db94011d3 1576 must contain a vendor-specific implementation of this function.
sahilmgandhi 18:6a4db94011d3 1577
sahilmgandhi 18:6a4db94011d3 1578 */
sahilmgandhi 18:6a4db94011d3 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
sahilmgandhi 18:6a4db94011d3 1580 {
sahilmgandhi 18:6a4db94011d3 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
sahilmgandhi 18:6a4db94011d3 1582
sahilmgandhi 18:6a4db94011d3 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
sahilmgandhi 18:6a4db94011d3 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
sahilmgandhi 18:6a4db94011d3 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
sahilmgandhi 18:6a4db94011d3 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
sahilmgandhi 18:6a4db94011d3 1587 SysTick_CTRL_TICKINT_Msk |
sahilmgandhi 18:6a4db94011d3 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
sahilmgandhi 18:6a4db94011d3 1589 return (0UL); /* Function successful */
sahilmgandhi 18:6a4db94011d3 1590 }
sahilmgandhi 18:6a4db94011d3 1591
sahilmgandhi 18:6a4db94011d3 1592 #endif
sahilmgandhi 18:6a4db94011d3 1593
sahilmgandhi 18:6a4db94011d3 1594 /*@} end of CMSIS_Core_SysTickFunctions */
sahilmgandhi 18:6a4db94011d3 1595
sahilmgandhi 18:6a4db94011d3 1596
sahilmgandhi 18:6a4db94011d3 1597
sahilmgandhi 18:6a4db94011d3 1598 /* ##################################### Debug In/Output function ########################################### */
sahilmgandhi 18:6a4db94011d3 1599 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
sahilmgandhi 18:6a4db94011d3 1601 \brief Functions that access the ITM debug interface.
sahilmgandhi 18:6a4db94011d3 1602 @{
sahilmgandhi 18:6a4db94011d3 1603 */
sahilmgandhi 18:6a4db94011d3 1604
sahilmgandhi 18:6a4db94011d3 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
sahilmgandhi 18:6a4db94011d3 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
sahilmgandhi 18:6a4db94011d3 1607
sahilmgandhi 18:6a4db94011d3 1608
sahilmgandhi 18:6a4db94011d3 1609 /** \brief ITM Send Character
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 The function transmits a character via the ITM channel 0, and
sahilmgandhi 18:6a4db94011d3 1612 \li Just returns when no debugger is connected that has booked the output.
sahilmgandhi 18:6a4db94011d3 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
sahilmgandhi 18:6a4db94011d3 1614
sahilmgandhi 18:6a4db94011d3 1615 \param [in] ch Character to transmit.
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 \returns Character to transmit.
sahilmgandhi 18:6a4db94011d3 1618 */
sahilmgandhi 18:6a4db94011d3 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
sahilmgandhi 18:6a4db94011d3 1620 {
sahilmgandhi 18:6a4db94011d3 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
sahilmgandhi 18:6a4db94011d3 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
sahilmgandhi 18:6a4db94011d3 1623 {
sahilmgandhi 18:6a4db94011d3 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
sahilmgandhi 18:6a4db94011d3 1625 ITM->PORT[0].u8 = (uint8_t)ch;
sahilmgandhi 18:6a4db94011d3 1626 }
sahilmgandhi 18:6a4db94011d3 1627 return (ch);
sahilmgandhi 18:6a4db94011d3 1628 }
sahilmgandhi 18:6a4db94011d3 1629
sahilmgandhi 18:6a4db94011d3 1630
sahilmgandhi 18:6a4db94011d3 1631 /** \brief ITM Receive Character
sahilmgandhi 18:6a4db94011d3 1632
sahilmgandhi 18:6a4db94011d3 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
sahilmgandhi 18:6a4db94011d3 1634
sahilmgandhi 18:6a4db94011d3 1635 \return Received character.
sahilmgandhi 18:6a4db94011d3 1636 \return -1 No character pending.
sahilmgandhi 18:6a4db94011d3 1637 */
sahilmgandhi 18:6a4db94011d3 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
sahilmgandhi 18:6a4db94011d3 1639 int32_t ch = -1; /* no character available */
sahilmgandhi 18:6a4db94011d3 1640
sahilmgandhi 18:6a4db94011d3 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
sahilmgandhi 18:6a4db94011d3 1642 ch = ITM_RxBuffer;
sahilmgandhi 18:6a4db94011d3 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
sahilmgandhi 18:6a4db94011d3 1644 }
sahilmgandhi 18:6a4db94011d3 1645
sahilmgandhi 18:6a4db94011d3 1646 return (ch);
sahilmgandhi 18:6a4db94011d3 1647 }
sahilmgandhi 18:6a4db94011d3 1648
sahilmgandhi 18:6a4db94011d3 1649
sahilmgandhi 18:6a4db94011d3 1650 /** \brief ITM Check Character
sahilmgandhi 18:6a4db94011d3 1651
sahilmgandhi 18:6a4db94011d3 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
sahilmgandhi 18:6a4db94011d3 1653
sahilmgandhi 18:6a4db94011d3 1654 \return 0 No character available.
sahilmgandhi 18:6a4db94011d3 1655 \return 1 Character available.
sahilmgandhi 18:6a4db94011d3 1656 */
sahilmgandhi 18:6a4db94011d3 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
sahilmgandhi 18:6a4db94011d3 1658
sahilmgandhi 18:6a4db94011d3 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
sahilmgandhi 18:6a4db94011d3 1660 return (0); /* no character available */
sahilmgandhi 18:6a4db94011d3 1661 } else {
sahilmgandhi 18:6a4db94011d3 1662 return (1); /* character available */
sahilmgandhi 18:6a4db94011d3 1663 }
sahilmgandhi 18:6a4db94011d3 1664 }
sahilmgandhi 18:6a4db94011d3 1665
sahilmgandhi 18:6a4db94011d3 1666 /*@} end of CMSIS_core_DebugFunctions */
sahilmgandhi 18:6a4db94011d3 1667
sahilmgandhi 18:6a4db94011d3 1668
sahilmgandhi 18:6a4db94011d3 1669
sahilmgandhi 18:6a4db94011d3 1670
sahilmgandhi 18:6a4db94011d3 1671 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1672 }
sahilmgandhi 18:6a4db94011d3 1673 #endif
sahilmgandhi 18:6a4db94011d3 1674
sahilmgandhi 18:6a4db94011d3 1675 #endif /* __CORE_SC300_H_DEPENDANT */
sahilmgandhi 18:6a4db94011d3 1676
sahilmgandhi 18:6a4db94011d3 1677 #endif /* __CMSIS_GENERIC */