MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 2
sahilmgandhi 18:6a4db94011d3 3 All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 5 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 6 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 7 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 8 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 9 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 10 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 11 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 12 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 13 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 25 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 26 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 29 * Functions
sahilmgandhi 18:6a4db94011d3 30 *---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 31 .text
sahilmgandhi 18:6a4db94011d3 32 .global __v7_all_cache
sahilmgandhi 18:6a4db94011d3 33 /*
sahilmgandhi 18:6a4db94011d3 34 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
sahilmgandhi 18:6a4db94011d3 35 */
sahilmgandhi 18:6a4db94011d3 36 __v7_all_cache:
sahilmgandhi 18:6a4db94011d3 37 .arm
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 PUSH {R4-R11}
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
sahilmgandhi 18:6a4db94011d3 42 ANDS R3, R6, #0x07000000 /* Extract coherency level */
sahilmgandhi 18:6a4db94011d3 43 MOV R3, R3, LSR #23 /* Total cache levels << 1 */
sahilmgandhi 18:6a4db94011d3 44 BEQ Finished /* If 0, no need to clean */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 MOV R10, #0 /* R10 holds current cache level << 1 */
sahilmgandhi 18:6a4db94011d3 47 Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
sahilmgandhi 18:6a4db94011d3 48 MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
sahilmgandhi 18:6a4db94011d3 49 AND R1, R1, #7 /* Isolate those lower 3 bits */
sahilmgandhi 18:6a4db94011d3 50 CMP R1, #2
sahilmgandhi 18:6a4db94011d3 51 BLT Skip /* No cache or only instruction cache at this level */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
sahilmgandhi 18:6a4db94011d3 54 ISB /* ISB to sync the change to the CacheSizeID reg */
sahilmgandhi 18:6a4db94011d3 55 MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
sahilmgandhi 18:6a4db94011d3 56 AND R2, R1, #7 /* Extract the line length field */
sahilmgandhi 18:6a4db94011d3 57 ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
sahilmgandhi 18:6a4db94011d3 58 LDR R4, =0x3FF
sahilmgandhi 18:6a4db94011d3 59 ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
sahilmgandhi 18:6a4db94011d3 60 CLZ R5, R4 /* R5 is the bit position of the way size increment */
sahilmgandhi 18:6a4db94011d3 61 LDR R7, =0x7FFF
sahilmgandhi 18:6a4db94011d3 62 ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
sahilmgandhi 18:6a4db94011d3 67 ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
sahilmgandhi 18:6a4db94011d3 68 CMP R0, #0
sahilmgandhi 18:6a4db94011d3 69 BNE Dccsw
sahilmgandhi 18:6a4db94011d3 70 MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
sahilmgandhi 18:6a4db94011d3 71 B cont
sahilmgandhi 18:6a4db94011d3 72 Dccsw: CMP R0, #1
sahilmgandhi 18:6a4db94011d3 73 BNE Dccisw
sahilmgandhi 18:6a4db94011d3 74 MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
sahilmgandhi 18:6a4db94011d3 75 B cont
sahilmgandhi 18:6a4db94011d3 76 Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
sahilmgandhi 18:6a4db94011d3 77 cont: SUBS R9, R9, #1 /* Decrement the Way number */
sahilmgandhi 18:6a4db94011d3 78 BGE Loop3
sahilmgandhi 18:6a4db94011d3 79 SUBS R7, R7, #1 /* Decrement the Set number */
sahilmgandhi 18:6a4db94011d3 80 BGE Loop2
sahilmgandhi 18:6a4db94011d3 81 Skip: ADD R10, R10, #2 /* increment the cache number */
sahilmgandhi 18:6a4db94011d3 82 CMP R3, R10
sahilmgandhi 18:6a4db94011d3 83 BGT Loop1
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 Finished:
sahilmgandhi 18:6a4db94011d3 86 DSB
sahilmgandhi 18:6a4db94011d3 87 POP {R4-R11}
sahilmgandhi 18:6a4db94011d3 88 BX lr
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 .END
sahilmgandhi 18:6a4db94011d3 92 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 93 * end of file
sahilmgandhi 18:6a4db94011d3 94 *---------------------------------------------------------------------------*/