MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/drivers/SPI.cpp@32:69acb14778ea, 2017-05-26 (annotated)

Committer:
kyleliangus
Date:
Fri May 26 03:46:03 2017 +0000
Revision:
32:69acb14778ea
Parent:
18:6a4db94011d3 
PID values still wonky. IR PID vs Encoder PID also wonky

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "drivers/SPI.h"
sahilmgandhi 18:6a4db94011d3 17 #include "platform/mbed_critical.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 namespace mbed {
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 24 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
sahilmgandhi 18:6a4db94011d3 25 #endif
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
sahilmgandhi 18:6a4db94011d3 28 _spi(),
sahilmgandhi 18:6a4db94011d3 29 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 30 _irq(this),
sahilmgandhi 18:6a4db94011d3 31 _usage(DMA_USAGE_NEVER),
sahilmgandhi 18:6a4db94011d3 32 #endif
sahilmgandhi 18:6a4db94011d3 33 _bits(8),
sahilmgandhi 18:6a4db94011d3 34 _mode(0),
sahilmgandhi 18:6a4db94011d3 35 _hz(1000000) {
sahilmgandhi 18:6a4db94011d3 36 // No lock needed in the constructor
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 spi_init(&_spi, mosi, miso, sclk, ssel);
sahilmgandhi 18:6a4db94011d3 39 aquire();
sahilmgandhi 18:6a4db94011d3 40 }
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 void SPI::format(int bits, int mode) {
sahilmgandhi 18:6a4db94011d3 43 lock();
sahilmgandhi 18:6a4db94011d3 44 _bits = bits;
sahilmgandhi 18:6a4db94011d3 45 _mode = mode;
sahilmgandhi 18:6a4db94011d3 46 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
sahilmgandhi 18:6a4db94011d3 47 aquire();
sahilmgandhi 18:6a4db94011d3 48 unlock();
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 void SPI::frequency(int hz) {
sahilmgandhi 18:6a4db94011d3 52 lock();
sahilmgandhi 18:6a4db94011d3 53 _hz = hz;
sahilmgandhi 18:6a4db94011d3 54 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
sahilmgandhi 18:6a4db94011d3 55 aquire();
sahilmgandhi 18:6a4db94011d3 56 unlock();
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 SPI* SPI::_owner = NULL;
sahilmgandhi 18:6a4db94011d3 60 SingletonPtr<PlatformMutex> SPI::_mutex;
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
sahilmgandhi 18:6a4db94011d3 63 void SPI::aquire() {
sahilmgandhi 18:6a4db94011d3 64 lock();
sahilmgandhi 18:6a4db94011d3 65 if (_owner != this) {
sahilmgandhi 18:6a4db94011d3 66 spi_format(&_spi, _bits, _mode, 0);
sahilmgandhi 18:6a4db94011d3 67 spi_frequency(&_spi, _hz);
sahilmgandhi 18:6a4db94011d3 68 _owner = this;
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70 unlock();
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 int SPI::write(int value) {
sahilmgandhi 18:6a4db94011d3 74 lock();
sahilmgandhi 18:6a4db94011d3 75 aquire();
sahilmgandhi 18:6a4db94011d3 76 int ret = spi_master_write(&_spi, value);
sahilmgandhi 18:6a4db94011d3 77 unlock();
sahilmgandhi 18:6a4db94011d3 78 return ret;
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 void SPI::lock() {
sahilmgandhi 18:6a4db94011d3 82 _mutex->lock();
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 void SPI::unlock() {
sahilmgandhi 18:6a4db94011d3 86 _mutex->unlock();
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
sahilmgandhi 18:6a4db94011d3 92 {
sahilmgandhi 18:6a4db94011d3 93 if (spi_active(&_spi)) {
sahilmgandhi 18:6a4db94011d3 94 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
sahilmgandhi 18:6a4db94011d3 95 }
sahilmgandhi 18:6a4db94011d3 96 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
sahilmgandhi 18:6a4db94011d3 97 return 0;
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 void SPI::abort_transfer()
sahilmgandhi 18:6a4db94011d3 101 {
sahilmgandhi 18:6a4db94011d3 102 spi_abort_asynch(&_spi);
sahilmgandhi 18:6a4db94011d3 103 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 104 dequeue_transaction();
sahilmgandhi 18:6a4db94011d3 105 #endif
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 void SPI::clear_transfer_buffer()
sahilmgandhi 18:6a4db94011d3 110 {
sahilmgandhi 18:6a4db94011d3 111 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 112 _transaction_buffer.reset();
sahilmgandhi 18:6a4db94011d3 113 #endif
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 void SPI::abort_all_transfers()
sahilmgandhi 18:6a4db94011d3 117 {
sahilmgandhi 18:6a4db94011d3 118 clear_transfer_buffer();
sahilmgandhi 18:6a4db94011d3 119 abort_transfer();
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 int SPI::set_dma_usage(DMAUsage usage)
sahilmgandhi 18:6a4db94011d3 123 {
sahilmgandhi 18:6a4db94011d3 124 if (spi_active(&_spi)) {
sahilmgandhi 18:6a4db94011d3 125 return -1;
sahilmgandhi 18:6a4db94011d3 126 }
sahilmgandhi 18:6a4db94011d3 127 _usage = usage;
sahilmgandhi 18:6a4db94011d3 128 return 0;
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
sahilmgandhi 18:6a4db94011d3 132 {
sahilmgandhi 18:6a4db94011d3 133 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 134 transaction_t t;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 t.tx_buffer = const_cast<void *>(tx_buffer);
sahilmgandhi 18:6a4db94011d3 137 t.tx_length = tx_length;
sahilmgandhi 18:6a4db94011d3 138 t.rx_buffer = rx_buffer;
sahilmgandhi 18:6a4db94011d3 139 t.rx_length = rx_length;
sahilmgandhi 18:6a4db94011d3 140 t.event = event;
sahilmgandhi 18:6a4db94011d3 141 t.callback = callback;
sahilmgandhi 18:6a4db94011d3 142 t.width = bit_width;
sahilmgandhi 18:6a4db94011d3 143 Transaction<SPI> transaction(this, t);
sahilmgandhi 18:6a4db94011d3 144 if (_transaction_buffer.full()) {
sahilmgandhi 18:6a4db94011d3 145 return -1; // the buffer is full
sahilmgandhi 18:6a4db94011d3 146 } else {
sahilmgandhi 18:6a4db94011d3 147 core_util_critical_section_enter();
sahilmgandhi 18:6a4db94011d3 148 _transaction_buffer.push(transaction);
sahilmgandhi 18:6a4db94011d3 149 if (!spi_active(&_spi)) {
sahilmgandhi 18:6a4db94011d3 150 dequeue_transaction();
sahilmgandhi 18:6a4db94011d3 151 }
sahilmgandhi 18:6a4db94011d3 152 core_util_critical_section_exit();
sahilmgandhi 18:6a4db94011d3 153 return 0;
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155 #else
sahilmgandhi 18:6a4db94011d3 156 return -1;
sahilmgandhi 18:6a4db94011d3 157 #endif
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
sahilmgandhi 18:6a4db94011d3 161 {
sahilmgandhi 18:6a4db94011d3 162 aquire();
sahilmgandhi 18:6a4db94011d3 163 _callback = callback;
sahilmgandhi 18:6a4db94011d3 164 _irq.callback(&SPI::irq_handler_asynch);
sahilmgandhi 18:6a4db94011d3 165 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 void SPI::start_transaction(transaction_t *data)
sahilmgandhi 18:6a4db94011d3 171 {
sahilmgandhi 18:6a4db94011d3 172 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 void SPI::dequeue_transaction()
sahilmgandhi 18:6a4db94011d3 176 {
sahilmgandhi 18:6a4db94011d3 177 Transaction<SPI> t;
sahilmgandhi 18:6a4db94011d3 178 if (_transaction_buffer.pop(t)) {
sahilmgandhi 18:6a4db94011d3 179 SPI* obj = t.get_object();
sahilmgandhi 18:6a4db94011d3 180 transaction_t* data = t.get_transaction();
sahilmgandhi 18:6a4db94011d3 181 obj->start_transaction(data);
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 #endif
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 void SPI::irq_handler_asynch(void)
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 int event = spi_irq_handler_asynch(&_spi);
sahilmgandhi 18:6a4db94011d3 190 if (_callback && (event & SPI_EVENT_ALL)) {
sahilmgandhi 18:6a4db94011d3 191 _callback.call(event & SPI_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 194 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
sahilmgandhi 18:6a4db94011d3 195 // SPI peripheral is free (event happend), dequeue transaction
sahilmgandhi 18:6a4db94011d3 196 dequeue_transaction();
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198 #endif
sahilmgandhi 18:6a4db94011d3 199 }
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #endif
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 } // namespace mbed
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 #endif