Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/stm_spi_api.c@34:69342782fb68, 2017-05-26 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Fri May 26 17:21:04 2017 +0000
- Revision:
- 34:69342782fb68
- Parent:
- 18:6a4db94011d3
Added small reverse turns before the break so that we can stop faster.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | ******************************************************************************* |
sahilmgandhi | 18:6a4db94011d3 | 3 | * Copyright (c) 2015, STMicroelectronics |
sahilmgandhi | 18:6a4db94011d3 | 4 | * All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 7 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 10 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 13 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 15 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 16 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 28 | ******************************************************************************* |
sahilmgandhi | 18:6a4db94011d3 | 29 | */ |
sahilmgandhi | 18:6a4db94011d3 | 30 | #include "mbed_assert.h" |
sahilmgandhi | 18:6a4db94011d3 | 31 | #include "mbed_error.h" |
sahilmgandhi | 18:6a4db94011d3 | 32 | #include "spi_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | #if DEVICE_SPI |
sahilmgandhi | 18:6a4db94011d3 | 35 | #include <stdbool.h> |
sahilmgandhi | 18:6a4db94011d3 | 36 | #include <math.h> |
sahilmgandhi | 18:6a4db94011d3 | 37 | #include <string.h> |
sahilmgandhi | 18:6a4db94011d3 | 38 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 39 | #include "pinmap.h" |
sahilmgandhi | 18:6a4db94011d3 | 40 | #include "PeripheralPins.h" |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | #if DEVICE_SPI_ASYNCH |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi)) |
sahilmgandhi | 18:6a4db94011d3 | 44 | #else |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi)) |
sahilmgandhi | 18:6a4db94011d3 | 46 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 47 | |
sahilmgandhi | 18:6a4db94011d3 | 48 | #if DEVICE_SPI_ASYNCH |
sahilmgandhi | 18:6a4db94011d3 | 49 | #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) |
sahilmgandhi | 18:6a4db94011d3 | 50 | #else |
sahilmgandhi | 18:6a4db94011d3 | 51 | #define SPI_S(obj) (( struct spi_s *)(obj)) |
sahilmgandhi | 18:6a4db94011d3 | 52 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 53 | |
sahilmgandhi | 18:6a4db94011d3 | 54 | #ifndef DEBUG_STDIO |
sahilmgandhi | 18:6a4db94011d3 | 55 | # define DEBUG_STDIO 0 |
sahilmgandhi | 18:6a4db94011d3 | 56 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 57 | |
sahilmgandhi | 18:6a4db94011d3 | 58 | #if DEBUG_STDIO |
sahilmgandhi | 18:6a4db94011d3 | 59 | # include <stdio.h> |
sahilmgandhi | 18:6a4db94011d3 | 60 | # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 61 | #else |
sahilmgandhi | 18:6a4db94011d3 | 62 | # define DEBUG_PRINTF(...) {} |
sahilmgandhi | 18:6a4db94011d3 | 63 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | void init_spi(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 66 | { |
sahilmgandhi | 18:6a4db94011d3 | 67 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 68 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | __HAL_SPI_DISABLE(handle); |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance); |
sahilmgandhi | 18:6a4db94011d3 | 73 | if (HAL_SPI_Init(handle) != HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 74 | error("Cannot initialize SPI"); |
sahilmgandhi | 18:6a4db94011d3 | 75 | } |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | __HAL_SPI_ENABLE(handle); |
sahilmgandhi | 18:6a4db94011d3 | 78 | } |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
sahilmgandhi | 18:6a4db94011d3 | 81 | { |
sahilmgandhi | 18:6a4db94011d3 | 82 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 83 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | // Determine the SPI to use |
sahilmgandhi | 18:6a4db94011d3 | 86 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
sahilmgandhi | 18:6a4db94011d3 | 87 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
sahilmgandhi | 18:6a4db94011d3 | 88 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
sahilmgandhi | 18:6a4db94011d3 | 89 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
sahilmgandhi | 18:6a4db94011d3 | 92 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); |
sahilmgandhi | 18:6a4db94011d3 | 95 | MBED_ASSERT(spiobj->spi != (SPIName)NC); |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | #if defined SPI1_BASE |
sahilmgandhi | 18:6a4db94011d3 | 98 | // Enable SPI clock |
sahilmgandhi | 18:6a4db94011d3 | 99 | if (spiobj->spi == SPI_1) { |
sahilmgandhi | 18:6a4db94011d3 | 100 | __HAL_RCC_SPI1_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 101 | spiobj->spiIRQ = SPI1_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 102 | } |
sahilmgandhi | 18:6a4db94011d3 | 103 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 104 | |
sahilmgandhi | 18:6a4db94011d3 | 105 | #if defined SPI2_BASE |
sahilmgandhi | 18:6a4db94011d3 | 106 | if (spiobj->spi == SPI_2) { |
sahilmgandhi | 18:6a4db94011d3 | 107 | __HAL_RCC_SPI2_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 108 | spiobj->spiIRQ = SPI2_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 109 | } |
sahilmgandhi | 18:6a4db94011d3 | 110 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | #if defined SPI3_BASE |
sahilmgandhi | 18:6a4db94011d3 | 113 | if (spiobj->spi == SPI_3) { |
sahilmgandhi | 18:6a4db94011d3 | 114 | __HAL_RCC_SPI3_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 115 | spiobj->spiIRQ = SPI3_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 116 | } |
sahilmgandhi | 18:6a4db94011d3 | 117 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | #if defined SPI4_BASE |
sahilmgandhi | 18:6a4db94011d3 | 120 | if (spiobj->spi == SPI_4) { |
sahilmgandhi | 18:6a4db94011d3 | 121 | __HAL_RCC_SPI4_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 122 | spiobj->spiIRQ = SPI4_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 123 | } |
sahilmgandhi | 18:6a4db94011d3 | 124 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | #if defined SPI5_BASE |
sahilmgandhi | 18:6a4db94011d3 | 127 | if (spiobj->spi == SPI_5) { |
sahilmgandhi | 18:6a4db94011d3 | 128 | __HAL_RCC_SPI5_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 129 | spiobj->spiIRQ = SPI5_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 130 | } |
sahilmgandhi | 18:6a4db94011d3 | 131 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | #if defined SPI6_BASE |
sahilmgandhi | 18:6a4db94011d3 | 134 | if (spiobj->spi == SPI_6) { |
sahilmgandhi | 18:6a4db94011d3 | 135 | __HAL_RCC_SPI6_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 136 | spiobj->spiIRQ = SPI6_IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 137 | } |
sahilmgandhi | 18:6a4db94011d3 | 138 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 139 | |
sahilmgandhi | 18:6a4db94011d3 | 140 | // Configure the SPI pins |
sahilmgandhi | 18:6a4db94011d3 | 141 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
sahilmgandhi | 18:6a4db94011d3 | 142 | pinmap_pinout(miso, PinMap_SPI_MISO); |
sahilmgandhi | 18:6a4db94011d3 | 143 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
sahilmgandhi | 18:6a4db94011d3 | 144 | spiobj->pin_miso = miso; |
sahilmgandhi | 18:6a4db94011d3 | 145 | spiobj->pin_mosi = mosi; |
sahilmgandhi | 18:6a4db94011d3 | 146 | spiobj->pin_sclk = sclk; |
sahilmgandhi | 18:6a4db94011d3 | 147 | spiobj->pin_ssel = ssel; |
sahilmgandhi | 18:6a4db94011d3 | 148 | if (ssel != NC) { |
sahilmgandhi | 18:6a4db94011d3 | 149 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
sahilmgandhi | 18:6a4db94011d3 | 150 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 151 | handle->Init.NSS = SPI_NSS_SOFT; |
sahilmgandhi | 18:6a4db94011d3 | 152 | } |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | /* Fill default value */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | handle->Instance = SPI_INST(obj); |
sahilmgandhi | 18:6a4db94011d3 | 156 | handle->Init.Mode = SPI_MODE_MASTER; |
sahilmgandhi | 18:6a4db94011d3 | 157 | handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; |
sahilmgandhi | 18:6a4db94011d3 | 158 | handle->Init.Direction = SPI_DIRECTION_2LINES; |
sahilmgandhi | 18:6a4db94011d3 | 159 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
sahilmgandhi | 18:6a4db94011d3 | 160 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
sahilmgandhi | 18:6a4db94011d3 | 161 | handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; |
sahilmgandhi | 18:6a4db94011d3 | 162 | handle->Init.CRCPolynomial = 7; |
sahilmgandhi | 18:6a4db94011d3 | 163 | handle->Init.DataSize = SPI_DATASIZE_8BIT; |
sahilmgandhi | 18:6a4db94011d3 | 164 | handle->Init.FirstBit = SPI_FIRSTBIT_MSB; |
sahilmgandhi | 18:6a4db94011d3 | 165 | handle->Init.TIMode = SPI_TIMODE_DISABLED; |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | init_spi(obj); |
sahilmgandhi | 18:6a4db94011d3 | 168 | } |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | void spi_free(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 171 | { |
sahilmgandhi | 18:6a4db94011d3 | 172 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 173 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | DEBUG_PRINTF("spi_free\r\n"); |
sahilmgandhi | 18:6a4db94011d3 | 176 | |
sahilmgandhi | 18:6a4db94011d3 | 177 | __HAL_SPI_DISABLE(handle); |
sahilmgandhi | 18:6a4db94011d3 | 178 | HAL_SPI_DeInit(handle); |
sahilmgandhi | 18:6a4db94011d3 | 179 | |
sahilmgandhi | 18:6a4db94011d3 | 180 | #if defined SPI1_BASE |
sahilmgandhi | 18:6a4db94011d3 | 181 | // Reset SPI and disable clock |
sahilmgandhi | 18:6a4db94011d3 | 182 | if (spiobj->spi == SPI_1) { |
sahilmgandhi | 18:6a4db94011d3 | 183 | __HAL_RCC_SPI1_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 184 | __HAL_RCC_SPI1_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 185 | __HAL_RCC_SPI1_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 186 | } |
sahilmgandhi | 18:6a4db94011d3 | 187 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 188 | #if defined SPI2_BASE |
sahilmgandhi | 18:6a4db94011d3 | 189 | if (spiobj->spi == SPI_2) { |
sahilmgandhi | 18:6a4db94011d3 | 190 | __HAL_RCC_SPI2_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 191 | __HAL_RCC_SPI2_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 192 | __HAL_RCC_SPI2_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 193 | } |
sahilmgandhi | 18:6a4db94011d3 | 194 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 195 | |
sahilmgandhi | 18:6a4db94011d3 | 196 | #if defined SPI3_BASE |
sahilmgandhi | 18:6a4db94011d3 | 197 | if (spiobj->spi == SPI_3) { |
sahilmgandhi | 18:6a4db94011d3 | 198 | __HAL_RCC_SPI3_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 199 | __HAL_RCC_SPI3_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 200 | __HAL_RCC_SPI3_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 201 | } |
sahilmgandhi | 18:6a4db94011d3 | 202 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 203 | |
sahilmgandhi | 18:6a4db94011d3 | 204 | #if defined SPI4_BASE |
sahilmgandhi | 18:6a4db94011d3 | 205 | if (spiobj->spi == SPI_4) { |
sahilmgandhi | 18:6a4db94011d3 | 206 | __HAL_RCC_SPI4_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 207 | __HAL_RCC_SPI4_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 208 | __HAL_RCC_SPI4_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 209 | } |
sahilmgandhi | 18:6a4db94011d3 | 210 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | #if defined SPI5_BASE |
sahilmgandhi | 18:6a4db94011d3 | 213 | if (spiobj->spi == SPI_5) { |
sahilmgandhi | 18:6a4db94011d3 | 214 | __HAL_RCC_SPI5_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 215 | __HAL_RCC_SPI5_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 216 | __HAL_RCC_SPI5_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 217 | } |
sahilmgandhi | 18:6a4db94011d3 | 218 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | #if defined SPI6_BASE |
sahilmgandhi | 18:6a4db94011d3 | 221 | if (spiobj->spi == SPI_6) { |
sahilmgandhi | 18:6a4db94011d3 | 222 | __HAL_RCC_SPI6_FORCE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 223 | __HAL_RCC_SPI6_RELEASE_RESET(); |
sahilmgandhi | 18:6a4db94011d3 | 224 | __HAL_RCC_SPI6_CLK_DISABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 225 | } |
sahilmgandhi | 18:6a4db94011d3 | 226 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 227 | |
sahilmgandhi | 18:6a4db94011d3 | 228 | // Configure GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 229 | pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
sahilmgandhi | 18:6a4db94011d3 | 230 | pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
sahilmgandhi | 18:6a4db94011d3 | 231 | pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
sahilmgandhi | 18:6a4db94011d3 | 232 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
sahilmgandhi | 18:6a4db94011d3 | 233 | pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
sahilmgandhi | 18:6a4db94011d3 | 234 | } |
sahilmgandhi | 18:6a4db94011d3 | 235 | } |
sahilmgandhi | 18:6a4db94011d3 | 236 | |
sahilmgandhi | 18:6a4db94011d3 | 237 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
sahilmgandhi | 18:6a4db94011d3 | 238 | { |
sahilmgandhi | 18:6a4db94011d3 | 239 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 240 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 241 | |
sahilmgandhi | 18:6a4db94011d3 | 242 | DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave); |
sahilmgandhi | 18:6a4db94011d3 | 243 | |
sahilmgandhi | 18:6a4db94011d3 | 244 | // Save new values |
sahilmgandhi | 18:6a4db94011d3 | 245 | handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT; |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | switch (mode) { |
sahilmgandhi | 18:6a4db94011d3 | 248 | case 0: |
sahilmgandhi | 18:6a4db94011d3 | 249 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
sahilmgandhi | 18:6a4db94011d3 | 250 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
sahilmgandhi | 18:6a4db94011d3 | 251 | break; |
sahilmgandhi | 18:6a4db94011d3 | 252 | case 1: |
sahilmgandhi | 18:6a4db94011d3 | 253 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
sahilmgandhi | 18:6a4db94011d3 | 254 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
sahilmgandhi | 18:6a4db94011d3 | 255 | break; |
sahilmgandhi | 18:6a4db94011d3 | 256 | case 2: |
sahilmgandhi | 18:6a4db94011d3 | 257 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
sahilmgandhi | 18:6a4db94011d3 | 258 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
sahilmgandhi | 18:6a4db94011d3 | 259 | break; |
sahilmgandhi | 18:6a4db94011d3 | 260 | default: |
sahilmgandhi | 18:6a4db94011d3 | 261 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
sahilmgandhi | 18:6a4db94011d3 | 262 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
sahilmgandhi | 18:6a4db94011d3 | 263 | break; |
sahilmgandhi | 18:6a4db94011d3 | 264 | } |
sahilmgandhi | 18:6a4db94011d3 | 265 | |
sahilmgandhi | 18:6a4db94011d3 | 266 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
sahilmgandhi | 18:6a4db94011d3 | 267 | handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; |
sahilmgandhi | 18:6a4db94011d3 | 268 | } |
sahilmgandhi | 18:6a4db94011d3 | 269 | |
sahilmgandhi | 18:6a4db94011d3 | 270 | handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; |
sahilmgandhi | 18:6a4db94011d3 | 271 | |
sahilmgandhi | 18:6a4db94011d3 | 272 | init_spi(obj); |
sahilmgandhi | 18:6a4db94011d3 | 273 | } |
sahilmgandhi | 18:6a4db94011d3 | 274 | |
sahilmgandhi | 18:6a4db94011d3 | 275 | /* |
sahilmgandhi | 18:6a4db94011d3 | 276 | * Only the IP clock input is family dependant so it computed |
sahilmgandhi | 18:6a4db94011d3 | 277 | * separately in spi_get_clock_freq |
sahilmgandhi | 18:6a4db94011d3 | 278 | */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | extern int spi_get_clock_freq(spi_t *obj); |
sahilmgandhi | 18:6a4db94011d3 | 280 | |
sahilmgandhi | 18:6a4db94011d3 | 281 | static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2, |
sahilmgandhi | 18:6a4db94011d3 | 282 | SPI_BAUDRATEPRESCALER_4, |
sahilmgandhi | 18:6a4db94011d3 | 283 | SPI_BAUDRATEPRESCALER_8, |
sahilmgandhi | 18:6a4db94011d3 | 284 | SPI_BAUDRATEPRESCALER_16, |
sahilmgandhi | 18:6a4db94011d3 | 285 | SPI_BAUDRATEPRESCALER_32, |
sahilmgandhi | 18:6a4db94011d3 | 286 | SPI_BAUDRATEPRESCALER_64, |
sahilmgandhi | 18:6a4db94011d3 | 287 | SPI_BAUDRATEPRESCALER_128, |
sahilmgandhi | 18:6a4db94011d3 | 288 | SPI_BAUDRATEPRESCALER_256}; |
sahilmgandhi | 18:6a4db94011d3 | 289 | |
sahilmgandhi | 18:6a4db94011d3 | 290 | void spi_frequency(spi_t *obj, int hz) { |
sahilmgandhi | 18:6a4db94011d3 | 291 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 292 | int spi_hz = 0; |
sahilmgandhi | 18:6a4db94011d3 | 293 | uint8_t prescaler_rank = 0; |
sahilmgandhi | 18:6a4db94011d3 | 294 | uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1; |
sahilmgandhi | 18:6a4db94011d3 | 295 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 296 | |
sahilmgandhi | 18:6a4db94011d3 | 297 | /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | spi_hz = spi_get_clock_freq(obj) / 2; |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | /* Define pre-scaler in order to get highest available frequency below requested frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | while ((spi_hz > hz) && (prescaler_rank < last_index)) { |
sahilmgandhi | 18:6a4db94011d3 | 302 | spi_hz = spi_hz / 2; |
sahilmgandhi | 18:6a4db94011d3 | 303 | prescaler_rank++; |
sahilmgandhi | 18:6a4db94011d3 | 304 | } |
sahilmgandhi | 18:6a4db94011d3 | 305 | |
sahilmgandhi | 18:6a4db94011d3 | 306 | /* Use the best fit pre-scaler */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank]; |
sahilmgandhi | 18:6a4db94011d3 | 308 | |
sahilmgandhi | 18:6a4db94011d3 | 309 | /* In case maximum pre-scaler still gives too high freq, raise an error */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | if (spi_hz > hz) { |
sahilmgandhi | 18:6a4db94011d3 | 311 | DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz); |
sahilmgandhi | 18:6a4db94011d3 | 312 | } |
sahilmgandhi | 18:6a4db94011d3 | 313 | |
sahilmgandhi | 18:6a4db94011d3 | 314 | DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz); |
sahilmgandhi | 18:6a4db94011d3 | 315 | |
sahilmgandhi | 18:6a4db94011d3 | 316 | init_spi(obj); |
sahilmgandhi | 18:6a4db94011d3 | 317 | } |
sahilmgandhi | 18:6a4db94011d3 | 318 | |
sahilmgandhi | 18:6a4db94011d3 | 319 | static inline int ssp_readable(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 320 | { |
sahilmgandhi | 18:6a4db94011d3 | 321 | int status; |
sahilmgandhi | 18:6a4db94011d3 | 322 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 323 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 324 | |
sahilmgandhi | 18:6a4db94011d3 | 325 | // Check if data is received |
sahilmgandhi | 18:6a4db94011d3 | 326 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); |
sahilmgandhi | 18:6a4db94011d3 | 327 | return status; |
sahilmgandhi | 18:6a4db94011d3 | 328 | } |
sahilmgandhi | 18:6a4db94011d3 | 329 | |
sahilmgandhi | 18:6a4db94011d3 | 330 | static inline int ssp_writeable(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 331 | { |
sahilmgandhi | 18:6a4db94011d3 | 332 | int status; |
sahilmgandhi | 18:6a4db94011d3 | 333 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 334 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 335 | |
sahilmgandhi | 18:6a4db94011d3 | 336 | // Check if data is transmitted |
sahilmgandhi | 18:6a4db94011d3 | 337 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0); |
sahilmgandhi | 18:6a4db94011d3 | 338 | return status; |
sahilmgandhi | 18:6a4db94011d3 | 339 | } |
sahilmgandhi | 18:6a4db94011d3 | 340 | |
sahilmgandhi | 18:6a4db94011d3 | 341 | static inline int ssp_busy(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 342 | { |
sahilmgandhi | 18:6a4db94011d3 | 343 | int status; |
sahilmgandhi | 18:6a4db94011d3 | 344 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 345 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 346 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0); |
sahilmgandhi | 18:6a4db94011d3 | 347 | return status; |
sahilmgandhi | 18:6a4db94011d3 | 348 | } |
sahilmgandhi | 18:6a4db94011d3 | 349 | |
sahilmgandhi | 18:6a4db94011d3 | 350 | int spi_master_write(spi_t *obj, int value) |
sahilmgandhi | 18:6a4db94011d3 | 351 | { |
sahilmgandhi | 18:6a4db94011d3 | 352 | uint16_t size, ret; |
sahilmgandhi | 18:6a4db94011d3 | 353 | int Rx = 0; |
sahilmgandhi | 18:6a4db94011d3 | 354 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 355 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 356 | |
sahilmgandhi | 18:6a4db94011d3 | 357 | size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1; |
sahilmgandhi | 18:6a4db94011d3 | 358 | |
sahilmgandhi | 18:6a4db94011d3 | 359 | /* Use 10ms timeout */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10); |
sahilmgandhi | 18:6a4db94011d3 | 361 | |
sahilmgandhi | 18:6a4db94011d3 | 362 | if(ret == HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 363 | return Rx; |
sahilmgandhi | 18:6a4db94011d3 | 364 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 365 | DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance); |
sahilmgandhi | 18:6a4db94011d3 | 366 | return -1; |
sahilmgandhi | 18:6a4db94011d3 | 367 | } |
sahilmgandhi | 18:6a4db94011d3 | 368 | } |
sahilmgandhi | 18:6a4db94011d3 | 369 | |
sahilmgandhi | 18:6a4db94011d3 | 370 | int spi_slave_receive(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 371 | { |
sahilmgandhi | 18:6a4db94011d3 | 372 | return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); |
sahilmgandhi | 18:6a4db94011d3 | 373 | }; |
sahilmgandhi | 18:6a4db94011d3 | 374 | |
sahilmgandhi | 18:6a4db94011d3 | 375 | int spi_slave_read(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 376 | { |
sahilmgandhi | 18:6a4db94011d3 | 377 | SPI_TypeDef *spi = SPI_INST(obj); |
sahilmgandhi | 18:6a4db94011d3 | 378 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 379 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 380 | while (!ssp_readable(obj)); |
sahilmgandhi | 18:6a4db94011d3 | 381 | if (handle->Init.DataSize == SPI_DATASIZE_8BIT) { |
sahilmgandhi | 18:6a4db94011d3 | 382 | // Force 8-bit access to the data register |
sahilmgandhi | 18:6a4db94011d3 | 383 | uint8_t *p_spi_dr = 0; |
sahilmgandhi | 18:6a4db94011d3 | 384 | p_spi_dr = (uint8_t *) & (spi->DR); |
sahilmgandhi | 18:6a4db94011d3 | 385 | return (int)(*p_spi_dr); |
sahilmgandhi | 18:6a4db94011d3 | 386 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 387 | return (int)spi->DR; |
sahilmgandhi | 18:6a4db94011d3 | 388 | } |
sahilmgandhi | 18:6a4db94011d3 | 389 | } |
sahilmgandhi | 18:6a4db94011d3 | 390 | |
sahilmgandhi | 18:6a4db94011d3 | 391 | void spi_slave_write(spi_t *obj, int value) |
sahilmgandhi | 18:6a4db94011d3 | 392 | { |
sahilmgandhi | 18:6a4db94011d3 | 393 | SPI_TypeDef *spi = SPI_INST(obj); |
sahilmgandhi | 18:6a4db94011d3 | 394 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 395 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 396 | while (!ssp_writeable(obj)); |
sahilmgandhi | 18:6a4db94011d3 | 397 | if (handle->Init.DataSize == SPI_DATASIZE_8BIT) { |
sahilmgandhi | 18:6a4db94011d3 | 398 | // Force 8-bit access to the data register |
sahilmgandhi | 18:6a4db94011d3 | 399 | uint8_t *p_spi_dr = 0; |
sahilmgandhi | 18:6a4db94011d3 | 400 | p_spi_dr = (uint8_t *) & (spi->DR); |
sahilmgandhi | 18:6a4db94011d3 | 401 | *p_spi_dr = (uint8_t)value; |
sahilmgandhi | 18:6a4db94011d3 | 402 | } else { // SPI_DATASIZE_16BIT |
sahilmgandhi | 18:6a4db94011d3 | 403 | spi->DR = (uint16_t)value; |
sahilmgandhi | 18:6a4db94011d3 | 404 | } |
sahilmgandhi | 18:6a4db94011d3 | 405 | } |
sahilmgandhi | 18:6a4db94011d3 | 406 | |
sahilmgandhi | 18:6a4db94011d3 | 407 | int spi_busy(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 408 | { |
sahilmgandhi | 18:6a4db94011d3 | 409 | return ssp_busy(obj); |
sahilmgandhi | 18:6a4db94011d3 | 410 | } |
sahilmgandhi | 18:6a4db94011d3 | 411 | |
sahilmgandhi | 18:6a4db94011d3 | 412 | #ifdef DEVICE_SPI_ASYNCH |
sahilmgandhi | 18:6a4db94011d3 | 413 | typedef enum { |
sahilmgandhi | 18:6a4db94011d3 | 414 | SPI_TRANSFER_TYPE_NONE = 0, |
sahilmgandhi | 18:6a4db94011d3 | 415 | SPI_TRANSFER_TYPE_TX = 1, |
sahilmgandhi | 18:6a4db94011d3 | 416 | SPI_TRANSFER_TYPE_RX = 2, |
sahilmgandhi | 18:6a4db94011d3 | 417 | SPI_TRANSFER_TYPE_TXRX = 3, |
sahilmgandhi | 18:6a4db94011d3 | 418 | } transfer_type_t; |
sahilmgandhi | 18:6a4db94011d3 | 419 | |
sahilmgandhi | 18:6a4db94011d3 | 420 | |
sahilmgandhi | 18:6a4db94011d3 | 421 | /// @returns the number of bytes transferred, or `0` if nothing transferred |
sahilmgandhi | 18:6a4db94011d3 | 422 | static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length) |
sahilmgandhi | 18:6a4db94011d3 | 423 | { |
sahilmgandhi | 18:6a4db94011d3 | 424 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 425 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 426 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
sahilmgandhi | 18:6a4db94011d3 | 427 | // the HAL expects number of transfers instead of number of bytes |
sahilmgandhi | 18:6a4db94011d3 | 428 | // so for 16 bit transfer width the count needs to be halved |
sahilmgandhi | 18:6a4db94011d3 | 429 | size_t words; |
sahilmgandhi | 18:6a4db94011d3 | 430 | |
sahilmgandhi | 18:6a4db94011d3 | 431 | DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length); |
sahilmgandhi | 18:6a4db94011d3 | 432 | |
sahilmgandhi | 18:6a4db94011d3 | 433 | obj->spi.transfer_type = transfer_type; |
sahilmgandhi | 18:6a4db94011d3 | 434 | |
sahilmgandhi | 18:6a4db94011d3 | 435 | if (is16bit) { |
sahilmgandhi | 18:6a4db94011d3 | 436 | words = length / 2; |
sahilmgandhi | 18:6a4db94011d3 | 437 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 438 | words = length; |
sahilmgandhi | 18:6a4db94011d3 | 439 | } |
sahilmgandhi | 18:6a4db94011d3 | 440 | |
sahilmgandhi | 18:6a4db94011d3 | 441 | // enable the interrupt |
sahilmgandhi | 18:6a4db94011d3 | 442 | IRQn_Type irq_n = spiobj->spiIRQ; |
sahilmgandhi | 18:6a4db94011d3 | 443 | NVIC_DisableIRQ(irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 444 | NVIC_ClearPendingIRQ(irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 445 | NVIC_SetPriority(irq_n, 1); |
sahilmgandhi | 18:6a4db94011d3 | 446 | NVIC_EnableIRQ(irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 447 | |
sahilmgandhi | 18:6a4db94011d3 | 448 | // enable the right hal transfer |
sahilmgandhi | 18:6a4db94011d3 | 449 | int rc = 0; |
sahilmgandhi | 18:6a4db94011d3 | 450 | switch(transfer_type) { |
sahilmgandhi | 18:6a4db94011d3 | 451 | case SPI_TRANSFER_TYPE_TXRX: |
sahilmgandhi | 18:6a4db94011d3 | 452 | rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words); |
sahilmgandhi | 18:6a4db94011d3 | 453 | break; |
sahilmgandhi | 18:6a4db94011d3 | 454 | case SPI_TRANSFER_TYPE_TX: |
sahilmgandhi | 18:6a4db94011d3 | 455 | rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words); |
sahilmgandhi | 18:6a4db94011d3 | 456 | break; |
sahilmgandhi | 18:6a4db94011d3 | 457 | case SPI_TRANSFER_TYPE_RX: |
sahilmgandhi | 18:6a4db94011d3 | 458 | // the receive function also "transmits" the receive buffer so in order |
sahilmgandhi | 18:6a4db94011d3 | 459 | // to guarantee that 0xff is on the line, we explicitly memset it here |
sahilmgandhi | 18:6a4db94011d3 | 460 | memset(rx, SPI_FILL_WORD, length); |
sahilmgandhi | 18:6a4db94011d3 | 461 | rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words); |
sahilmgandhi | 18:6a4db94011d3 | 462 | break; |
sahilmgandhi | 18:6a4db94011d3 | 463 | default: |
sahilmgandhi | 18:6a4db94011d3 | 464 | length = 0; |
sahilmgandhi | 18:6a4db94011d3 | 465 | } |
sahilmgandhi | 18:6a4db94011d3 | 466 | |
sahilmgandhi | 18:6a4db94011d3 | 467 | if (rc) { |
sahilmgandhi | 18:6a4db94011d3 | 468 | DEBUG_PRINTF("SPI: RC=%u\n", rc); |
sahilmgandhi | 18:6a4db94011d3 | 469 | length = 0; |
sahilmgandhi | 18:6a4db94011d3 | 470 | } |
sahilmgandhi | 18:6a4db94011d3 | 471 | |
sahilmgandhi | 18:6a4db94011d3 | 472 | return length; |
sahilmgandhi | 18:6a4db94011d3 | 473 | } |
sahilmgandhi | 18:6a4db94011d3 | 474 | |
sahilmgandhi | 18:6a4db94011d3 | 475 | // asynchronous API |
sahilmgandhi | 18:6a4db94011d3 | 476 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) |
sahilmgandhi | 18:6a4db94011d3 | 477 | { |
sahilmgandhi | 18:6a4db94011d3 | 478 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 479 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 480 | |
sahilmgandhi | 18:6a4db94011d3 | 481 | // TODO: DMA usage is currently ignored |
sahilmgandhi | 18:6a4db94011d3 | 482 | (void) hint; |
sahilmgandhi | 18:6a4db94011d3 | 483 | |
sahilmgandhi | 18:6a4db94011d3 | 484 | // check which use-case we have |
sahilmgandhi | 18:6a4db94011d3 | 485 | bool use_tx = (tx != NULL && tx_length > 0); |
sahilmgandhi | 18:6a4db94011d3 | 486 | bool use_rx = (rx != NULL && rx_length > 0); |
sahilmgandhi | 18:6a4db94011d3 | 487 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
sahilmgandhi | 18:6a4db94011d3 | 488 | |
sahilmgandhi | 18:6a4db94011d3 | 489 | // don't do anything, if the buffers aren't valid |
sahilmgandhi | 18:6a4db94011d3 | 490 | if (!use_tx && !use_rx) |
sahilmgandhi | 18:6a4db94011d3 | 491 | return; |
sahilmgandhi | 18:6a4db94011d3 | 492 | |
sahilmgandhi | 18:6a4db94011d3 | 493 | // copy the buffers to the SPI object |
sahilmgandhi | 18:6a4db94011d3 | 494 | obj->tx_buff.buffer = (void *) tx; |
sahilmgandhi | 18:6a4db94011d3 | 495 | obj->tx_buff.length = tx_length; |
sahilmgandhi | 18:6a4db94011d3 | 496 | obj->tx_buff.pos = 0; |
sahilmgandhi | 18:6a4db94011d3 | 497 | obj->tx_buff.width = is16bit ? 16 : 8; |
sahilmgandhi | 18:6a4db94011d3 | 498 | |
sahilmgandhi | 18:6a4db94011d3 | 499 | obj->rx_buff.buffer = rx; |
sahilmgandhi | 18:6a4db94011d3 | 500 | obj->rx_buff.length = rx_length; |
sahilmgandhi | 18:6a4db94011d3 | 501 | obj->rx_buff.pos = 0; |
sahilmgandhi | 18:6a4db94011d3 | 502 | obj->rx_buff.width = obj->tx_buff.width; |
sahilmgandhi | 18:6a4db94011d3 | 503 | |
sahilmgandhi | 18:6a4db94011d3 | 504 | obj->spi.event = event; |
sahilmgandhi | 18:6a4db94011d3 | 505 | |
sahilmgandhi | 18:6a4db94011d3 | 506 | DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length); |
sahilmgandhi | 18:6a4db94011d3 | 507 | |
sahilmgandhi | 18:6a4db94011d3 | 508 | // register the thunking handler |
sahilmgandhi | 18:6a4db94011d3 | 509 | IRQn_Type irq_n = spiobj->spiIRQ; |
sahilmgandhi | 18:6a4db94011d3 | 510 | NVIC_SetVector(irq_n, (uint32_t)handler); |
sahilmgandhi | 18:6a4db94011d3 | 511 | |
sahilmgandhi | 18:6a4db94011d3 | 512 | // enable the right hal transfer |
sahilmgandhi | 18:6a4db94011d3 | 513 | if (use_tx && use_rx) { |
sahilmgandhi | 18:6a4db94011d3 | 514 | // we cannot manage different rx / tx sizes, let's use smaller one |
sahilmgandhi | 18:6a4db94011d3 | 515 | size_t size = (tx_length < rx_length)? tx_length : rx_length; |
sahilmgandhi | 18:6a4db94011d3 | 516 | if(tx_length != rx_length) { |
sahilmgandhi | 18:6a4db94011d3 | 517 | DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size); |
sahilmgandhi | 18:6a4db94011d3 | 518 | obj->tx_buff.length = size; |
sahilmgandhi | 18:6a4db94011d3 | 519 | obj->rx_buff.length = size; |
sahilmgandhi | 18:6a4db94011d3 | 520 | } |
sahilmgandhi | 18:6a4db94011d3 | 521 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size); |
sahilmgandhi | 18:6a4db94011d3 | 522 | } else if (use_tx) { |
sahilmgandhi | 18:6a4db94011d3 | 523 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length); |
sahilmgandhi | 18:6a4db94011d3 | 524 | } else if (use_rx) { |
sahilmgandhi | 18:6a4db94011d3 | 525 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length); |
sahilmgandhi | 18:6a4db94011d3 | 526 | } |
sahilmgandhi | 18:6a4db94011d3 | 527 | } |
sahilmgandhi | 18:6a4db94011d3 | 528 | |
sahilmgandhi | 18:6a4db94011d3 | 529 | inline uint32_t spi_irq_handler_asynch(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 530 | { |
sahilmgandhi | 18:6a4db94011d3 | 531 | int event = 0; |
sahilmgandhi | 18:6a4db94011d3 | 532 | |
sahilmgandhi | 18:6a4db94011d3 | 533 | // call the CubeF4 handler, this will update the handle |
sahilmgandhi | 18:6a4db94011d3 | 534 | HAL_SPI_IRQHandler(&obj->spi.handle); |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | if (obj->spi.handle.State == HAL_SPI_STATE_READY) { |
sahilmgandhi | 18:6a4db94011d3 | 537 | // When HAL SPI is back to READY state, check if there was an error |
sahilmgandhi | 18:6a4db94011d3 | 538 | int error = obj->spi.handle.ErrorCode; |
sahilmgandhi | 18:6a4db94011d3 | 539 | if(error != HAL_SPI_ERROR_NONE) { |
sahilmgandhi | 18:6a4db94011d3 | 540 | // something went wrong and the transfer has definitely completed |
sahilmgandhi | 18:6a4db94011d3 | 541 | event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
sahilmgandhi | 18:6a4db94011d3 | 542 | |
sahilmgandhi | 18:6a4db94011d3 | 543 | if (error & HAL_SPI_ERROR_OVR) { |
sahilmgandhi | 18:6a4db94011d3 | 544 | // buffer overrun |
sahilmgandhi | 18:6a4db94011d3 | 545 | event |= SPI_EVENT_RX_OVERFLOW; |
sahilmgandhi | 18:6a4db94011d3 | 546 | } |
sahilmgandhi | 18:6a4db94011d3 | 547 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 548 | // else we're done |
sahilmgandhi | 18:6a4db94011d3 | 549 | event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
sahilmgandhi | 18:6a4db94011d3 | 550 | } |
sahilmgandhi | 18:6a4db94011d3 | 551 | // enable the interrupt |
sahilmgandhi | 18:6a4db94011d3 | 552 | NVIC_DisableIRQ(obj->spi.spiIRQ); |
sahilmgandhi | 18:6a4db94011d3 | 553 | NVIC_ClearPendingIRQ(obj->spi.spiIRQ); |
sahilmgandhi | 18:6a4db94011d3 | 554 | } |
sahilmgandhi | 18:6a4db94011d3 | 555 | |
sahilmgandhi | 18:6a4db94011d3 | 556 | |
sahilmgandhi | 18:6a4db94011d3 | 557 | return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)); |
sahilmgandhi | 18:6a4db94011d3 | 558 | } |
sahilmgandhi | 18:6a4db94011d3 | 559 | |
sahilmgandhi | 18:6a4db94011d3 | 560 | uint8_t spi_active(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 561 | { |
sahilmgandhi | 18:6a4db94011d3 | 562 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 563 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 564 | HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle); |
sahilmgandhi | 18:6a4db94011d3 | 565 | |
sahilmgandhi | 18:6a4db94011d3 | 566 | switch(state) { |
sahilmgandhi | 18:6a4db94011d3 | 567 | case HAL_SPI_STATE_RESET: |
sahilmgandhi | 18:6a4db94011d3 | 568 | case HAL_SPI_STATE_READY: |
sahilmgandhi | 18:6a4db94011d3 | 569 | case HAL_SPI_STATE_ERROR: |
sahilmgandhi | 18:6a4db94011d3 | 570 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 571 | default: |
sahilmgandhi | 18:6a4db94011d3 | 572 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 573 | } |
sahilmgandhi | 18:6a4db94011d3 | 574 | } |
sahilmgandhi | 18:6a4db94011d3 | 575 | |
sahilmgandhi | 18:6a4db94011d3 | 576 | void spi_abort_asynch(spi_t *obj) |
sahilmgandhi | 18:6a4db94011d3 | 577 | { |
sahilmgandhi | 18:6a4db94011d3 | 578 | struct spi_s *spiobj = SPI_S(obj); |
sahilmgandhi | 18:6a4db94011d3 | 579 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
sahilmgandhi | 18:6a4db94011d3 | 580 | |
sahilmgandhi | 18:6a4db94011d3 | 581 | // disable interrupt |
sahilmgandhi | 18:6a4db94011d3 | 582 | IRQn_Type irq_n = spiobj->spiIRQ; |
sahilmgandhi | 18:6a4db94011d3 | 583 | NVIC_ClearPendingIRQ(irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 584 | NVIC_DisableIRQ(irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 585 | |
sahilmgandhi | 18:6a4db94011d3 | 586 | // clean-up |
sahilmgandhi | 18:6a4db94011d3 | 587 | __HAL_SPI_DISABLE(handle); |
sahilmgandhi | 18:6a4db94011d3 | 588 | HAL_SPI_DeInit(handle); |
sahilmgandhi | 18:6a4db94011d3 | 589 | HAL_SPI_Init(handle); |
sahilmgandhi | 18:6a4db94011d3 | 590 | __HAL_SPI_ENABLE(handle); |
sahilmgandhi | 18:6a4db94011d3 | 591 | } |
sahilmgandhi | 18:6a4db94011d3 | 592 | |
sahilmgandhi | 18:6a4db94011d3 | 593 | #endif //DEVICE_SPI_ASYNCH |
sahilmgandhi | 18:6a4db94011d3 | 594 | |
sahilmgandhi | 18:6a4db94011d3 | 595 | #endif |