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EncoderDAGOZ.cpp@7:d7c793ec5c04, 2019-01-25 (annotated)

Committer:
irfantitok
Date:
Fri Jan 25 16:51:33 2019 +0000
Revision:
7:d7c793ec5c04
Initial Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
irfantitok 7:d7c793ec5c04 1 #include "EncoderDAGOZ.h"
irfantitok 7:d7c793ec5c04 2
irfantitok 7:d7c793ec5c04 3 namespace mbed
irfantitok 7:d7c793ec5c04 4 {
irfantitok 7:d7c793ec5c04 5
irfantitok 7:d7c793ec5c04 6 EncoderDAGOZ::EncoderDAGOZ(TIM_TypeDef * _TIM)
irfantitok 7:d7c793ec5c04 7 {
irfantitok 7:d7c793ec5c04 8 TIM = _TIM;
irfantitok 7:d7c793ec5c04 9 // Initialisation of the TIM module as an encoder counter
irfantitok 7:d7c793ec5c04 10 EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
irfantitok 7:d7c793ec5c04 11
irfantitok 7:d7c793ec5c04 12 // Update (aka over- and underflow) interrupt enabled
irfantitok 7:d7c793ec5c04 13 TIM->DIER |= 0x0001;
irfantitok 7:d7c793ec5c04 14 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
irfantitok 7:d7c793ec5c04 15 TIM->SR &= 0xfffe;
irfantitok 7:d7c793ec5c04 16 //generate update event
irfantitok 7:d7c793ec5c04 17 TIM->EGR = 1;
irfantitok 7:d7c793ec5c04 18 //enable counter
irfantitok 7:d7c793ec5c04 19 TIM->CR1 = 1;
irfantitok 7:d7c793ec5c04 20
irfantitok 7:d7c793ec5c04 21 }
irfantitok 7:d7c793ec5c04 22
irfantitok 7:d7c793ec5c04 23 EncoderDAGOZ::EncoderDAGOZ(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
irfantitok 7:d7c793ec5c04 24 {
irfantitok 7:d7c793ec5c04 25 TIM = _TIM;
irfantitok 7:d7c793ec5c04 26 // Initialisation of the TIM module as an encoder counter
irfantitok 7:d7c793ec5c04 27 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
irfantitok 7:d7c793ec5c04 28
irfantitok 7:d7c793ec5c04 29 // Update (aka over- and underflow) interrupt enabled
irfantitok 7:d7c793ec5c04 30 TIM->DIER |= 0x0001;
irfantitok 7:d7c793ec5c04 31 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
irfantitok 7:d7c793ec5c04 32 TIM->SR &= 0xfffe;
irfantitok 7:d7c793ec5c04 33 }
irfantitok 7:d7c793ec5c04 34
irfantitok 7:d7c793ec5c04 35 EncoderDAGOZ::EncoderDAGOZ(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
irfantitok 7:d7c793ec5c04 36 {
irfantitok 7:d7c793ec5c04 37 timer = *_timer;
irfantitok 7:d7c793ec5c04 38 encoder = *_encoder;
irfantitok 7:d7c793ec5c04 39 TIM = _TIM;
irfantitok 7:d7c793ec5c04 40 // Initialisation of the TIM module as an encoder counter
irfantitok 7:d7c793ec5c04 41 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
irfantitok 7:d7c793ec5c04 42
irfantitok 7:d7c793ec5c04 43 // Update (aka over- and underflow) interrupt enabled
irfantitok 7:d7c793ec5c04 44 TIM->DIER |= 0x0001;
irfantitok 7:d7c793ec5c04 45 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
irfantitok 7:d7c793ec5c04 46 TIM->SR &= 0xfffe;
irfantitok 7:d7c793ec5c04 47 }
irfantitok 7:d7c793ec5c04 48
irfantitok 7:d7c793ec5c04 49
irfantitok 7:d7c793ec5c04 50 int32_t EncoderDAGOZ::GetCounter(bool reset)
irfantitok 7:d7c793ec5c04 51 {
irfantitok 7:d7c793ec5c04 52 int16_t count = TIM->CNT;
irfantitok 7:d7c793ec5c04 53 if(reset){
irfantitok 7:d7c793ec5c04 54 switch((uint32_t)TIM){
irfantitok 7:d7c793ec5c04 55 case TIM1_BASE :
irfantitok 7:d7c793ec5c04 56 TIM1->CNT = 0;
irfantitok 7:d7c793ec5c04 57 break;
irfantitok 7:d7c793ec5c04 58
irfantitok 7:d7c793ec5c04 59 case TIM2_BASE :
irfantitok 7:d7c793ec5c04 60 TIM2->CNT = 0;
irfantitok 7:d7c793ec5c04 61 break;
irfantitok 7:d7c793ec5c04 62
irfantitok 7:d7c793ec5c04 63 case TIM3_BASE :
irfantitok 7:d7c793ec5c04 64 TIM3->CNT = 0;
irfantitok 7:d7c793ec5c04 65 break;
irfantitok 7:d7c793ec5c04 66
irfantitok 7:d7c793ec5c04 67 case TIM4_BASE :
irfantitok 7:d7c793ec5c04 68 TIM4->CNT = 0;
irfantitok 7:d7c793ec5c04 69 break;
irfantitok 7:d7c793ec5c04 70
irfantitok 7:d7c793ec5c04 71 case TIM5_BASE :
irfantitok 7:d7c793ec5c04 72 TIM5->CNT = 0;
irfantitok 7:d7c793ec5c04 73 break;
irfantitok 7:d7c793ec5c04 74
irfantitok 7:d7c793ec5c04 75 case TIM8_BASE :
irfantitok 7:d7c793ec5c04 76 TIM8->CNT = 0;
irfantitok 7:d7c793ec5c04 77 break;
irfantitok 7:d7c793ec5c04 78 }
irfantitok 7:d7c793ec5c04 79 }
irfantitok 7:d7c793ec5c04 80 else{
irfantitok 7:d7c793ec5c04 81 switch((uint32_t)TIM)
irfantitok 7:d7c793ec5c04 82 {
irfantitok 7:d7c793ec5c04 83 case TIM1_BASE :
irfantitok 7:d7c793ec5c04 84 return (int32_t)count;
irfantitok 7:d7c793ec5c04 85
irfantitok 7:d7c793ec5c04 86 case TIM2_BASE :
irfantitok 7:d7c793ec5c04 87 return (int32_t)count;
irfantitok 7:d7c793ec5c04 88
irfantitok 7:d7c793ec5c04 89 case TIM3_BASE :
irfantitok 7:d7c793ec5c04 90 return (int32_t)count;
irfantitok 7:d7c793ec5c04 91
irfantitok 7:d7c793ec5c04 92 case TIM4_BASE :
irfantitok 7:d7c793ec5c04 93 return (int32_t)count;
irfantitok 7:d7c793ec5c04 94
irfantitok 7:d7c793ec5c04 95 case TIM5_BASE :
irfantitok 7:d7c793ec5c04 96 return (int32_t)count;
irfantitok 7:d7c793ec5c04 97
irfantitok 7:d7c793ec5c04 98 case TIM8_BASE :
irfantitok 7:d7c793ec5c04 99 return (int32_t)count;
irfantitok 7:d7c793ec5c04 100 }
irfantitok 7:d7c793ec5c04 101 }
irfantitok 7:d7c793ec5c04 102
irfantitok 7:d7c793ec5c04 103 return (int32_t)count;
irfantitok 7:d7c793ec5c04 104 }
irfantitok 7:d7c793ec5c04 105
irfantitok 7:d7c793ec5c04 106
irfantitok 7:d7c793ec5c04 107 TIM_HandleTypeDef* EncoderDAGOZ::GetTimer()
irfantitok 7:d7c793ec5c04 108 {
irfantitok 7:d7c793ec5c04 109 return &timer;
irfantitok 7:d7c793ec5c04 110 }
irfantitok 7:d7c793ec5c04 111
irfantitok 7:d7c793ec5c04 112 }