Dagozilla to RoboCup / EncoderDAGOZ
Committer:
calmantara186
Date:
Thu Jan 17 05:20:49 2019 +0000
Revision:
5:a3349f37ef99
Parent:
4:9ce0e451aeff
new for stm32f7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kkoichy 0:ebd170807e11 1 #include "Nucleo_Encoder_16_bits.h"
kkoichy 0:ebd170807e11 2
kkoichy 0:ebd170807e11 3 namespace mbed
kkoichy 0:ebd170807e11 4 {
kkoichy 1:e82009479b5c 5
kkoichy 1:e82009479b5c 6 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM)
kkoichy 1:e82009479b5c 7 {
kkoichy 1:e82009479b5c 8 TIM = _TIM;
kkoichy 1:e82009479b5c 9 // Initialisation of the TIM module as an encoder counter
kkoichy 1:e82009479b5c 10 EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
kkoichy 1:e82009479b5c 11
kkoichy 1:e82009479b5c 12 // Update (aka over- and underflow) interrupt enabled
kkoichy 1:e82009479b5c 13 TIM->DIER |= 0x0001;
kkoichy 1:e82009479b5c 14 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 1:e82009479b5c 15 TIM->SR &= 0xfffe;
kkoichy 1:e82009479b5c 16 }
irfantitok 3:d43c60d01569 17
kkoichy 0:ebd170807e11 18 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 19 {
kkoichy 0:ebd170807e11 20 TIM = _TIM;
kkoichy 0:ebd170807e11 21 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 22 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 23
kkoichy 0:ebd170807e11 24 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 25 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 26 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 27 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 28 }
kkoichy 0:ebd170807e11 29
kkoichy 0:ebd170807e11 30 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 31 {
kkoichy 0:ebd170807e11 32 timer = *_timer;
kkoichy 0:ebd170807e11 33 encoder = *_encoder;
kkoichy 0:ebd170807e11 34 TIM = _TIM;
kkoichy 0:ebd170807e11 35 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 36 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 37
kkoichy 0:ebd170807e11 38 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 39 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 40 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 41 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 42 }
kkoichy 0:ebd170807e11 43
kkoichy 0:ebd170807e11 44
calmantara186 2:3fcf36c1b1af 45 int32_t Nucleo_Encoder_16_bits::GetCounter(bool reset)
kkoichy 0:ebd170807e11 46 {
irfantitok 3:d43c60d01569 47 int16_t count = TIM->CNT;
calmantara186 2:3fcf36c1b1af 48 if(reset){
calmantara186 2:3fcf36c1b1af 49 switch((uint32_t)TIM){
calmantara186 2:3fcf36c1b1af 50 case TIM1_BASE :
calmantara186 2:3fcf36c1b1af 51 TIM1->CNT = 0;
calmantara186 2:3fcf36c1b1af 52 break;
calmantara186 2:3fcf36c1b1af 53
calmantara186 2:3fcf36c1b1af 54 case TIM2_BASE :
calmantara186 2:3fcf36c1b1af 55 TIM2->CNT = 0;
calmantara186 2:3fcf36c1b1af 56 break;
calmantara186 2:3fcf36c1b1af 57
calmantara186 2:3fcf36c1b1af 58 case TIM3_BASE :
calmantara186 2:3fcf36c1b1af 59 TIM3->CNT = 0;
calmantara186 2:3fcf36c1b1af 60 break;
calmantara186 2:3fcf36c1b1af 61
calmantara186 2:3fcf36c1b1af 62 case TIM4_BASE :
calmantara186 2:3fcf36c1b1af 63 TIM4->CNT = 0;
calmantara186 2:3fcf36c1b1af 64 break;
calmantara186 2:3fcf36c1b1af 65
calmantara186 2:3fcf36c1b1af 66 case TIM5_BASE :
calmantara186 2:3fcf36c1b1af 67 TIM5->CNT = 0;
calmantara186 2:3fcf36c1b1af 68 break;
irfantitok 4:9ce0e451aeff 69
irfantitok 4:9ce0e451aeff 70 case TIM8_BASE :
irfantitok 4:9ce0e451aeff 71 TIM8->CNT = 0;
irfantitok 4:9ce0e451aeff 72 break;
calmantara186 5:a3349f37ef99 73
irfantitok 4:9ce0e451aeff 74 case TIM9_BASE :
irfantitok 4:9ce0e451aeff 75 TIM9->CNT = 0;
irfantitok 4:9ce0e451aeff 76 break;
irfantitok 4:9ce0e451aeff 77
irfantitok 4:9ce0e451aeff 78 case TIM12_BASE :
irfantitok 4:9ce0e451aeff 79 TIM12->CNT = 0;
irfantitok 4:9ce0e451aeff 80 break;
calmantara186 5:a3349f37ef99 81
calmantara186 2:3fcf36c1b1af 82 }
calmantara186 2:3fcf36c1b1af 83 }
calmantara186 2:3fcf36c1b1af 84 else{
calmantara186 2:3fcf36c1b1af 85 switch((uint32_t)TIM)
calmantara186 2:3fcf36c1b1af 86 {
calmantara186 2:3fcf36c1b1af 87 case TIM1_BASE :
irfantitok 3:d43c60d01569 88 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 89
calmantara186 2:3fcf36c1b1af 90 case TIM2_BASE :
irfantitok 3:d43c60d01569 91 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 92
calmantara186 2:3fcf36c1b1af 93 case TIM3_BASE :
irfantitok 3:d43c60d01569 94 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 95
calmantara186 2:3fcf36c1b1af 96 case TIM4_BASE :
irfantitok 3:d43c60d01569 97 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 98
calmantara186 2:3fcf36c1b1af 99 case TIM5_BASE :
irfantitok 3:d43c60d01569 100 return (int32_t)count;
irfantitok 4:9ce0e451aeff 101
irfantitok 4:9ce0e451aeff 102 case TIM8_BASE :
irfantitok 4:9ce0e451aeff 103 return (int32_t)count;
calmantara186 5:a3349f37ef99 104
irfantitok 4:9ce0e451aeff 105 case TIM9_BASE :
irfantitok 4:9ce0e451aeff 106 return (int32_t)count;
irfantitok 4:9ce0e451aeff 107
irfantitok 4:9ce0e451aeff 108 case TIM12_BASE :
irfantitok 4:9ce0e451aeff 109 return (int32_t)count;
calmantara186 5:a3349f37ef99 110
calmantara186 2:3fcf36c1b1af 111 }
kkoichy 0:ebd170807e11 112 }
kkoichy 0:ebd170807e11 113
kkoichy 0:ebd170807e11 114 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 115 }
kkoichy 0:ebd170807e11 116
irfantitok 3:d43c60d01569 117
kkoichy 0:ebd170807e11 118 TIM_HandleTypeDef* Nucleo_Encoder_16_bits::GetTimer()
kkoichy 0:ebd170807e11 119 {
kkoichy 0:ebd170807e11 120 return &timer;
kkoichy 0:ebd170807e11 121 }
kkoichy 0:ebd170807e11 122
kkoichy 0:ebd170807e11 123 }