DSP Book Yeditepe / mbed_f401re

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targets/cmsis/core_ca_mmu.h@0:7e2bd16f80af, 2015-01-17 (annotated)

Committer:
elessair
Date:
Sat Jan 17 18:03:58 2015 +0000
Revision:
0:7e2bd16f80af
nucleo f401re internal temperature added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:7e2bd16f80af 1 ;/**************************************************************************//**
elessair 0:7e2bd16f80af 2 ; * @file core_ca_mmu.h
elessair 0:7e2bd16f80af 3 ; * @brief MMU Startup File for
elessair 0:7e2bd16f80af 4 ; * VE_A9_MP Device Series
elessair 0:7e2bd16f80af 5 ; * @version V1.01
elessair 0:7e2bd16f80af 6 ; * @date 25 March 2013
elessair 0:7e2bd16f80af 7 ; *
elessair 0:7e2bd16f80af 8 ; * @note
elessair 0:7e2bd16f80af 9 ; *
elessair 0:7e2bd16f80af 10 ; ******************************************************************************/
elessair 0:7e2bd16f80af 11 ;/* Copyright (c) 2012 ARM LIMITED
elessair 0:7e2bd16f80af 12 ;
elessair 0:7e2bd16f80af 13 ; All rights reserved.
elessair 0:7e2bd16f80af 14 ; Redistribution and use in source and binary forms, with or without
elessair 0:7e2bd16f80af 15 ; modification, are permitted provided that the following conditions are met:
elessair 0:7e2bd16f80af 16 ; - Redistributions of source code must retain the above copyright
elessair 0:7e2bd16f80af 17 ; notice, this list of conditions and the following disclaimer.
elessair 0:7e2bd16f80af 18 ; - Redistributions in binary form must reproduce the above copyright
elessair 0:7e2bd16f80af 19 ; notice, this list of conditions and the following disclaimer in the
elessair 0:7e2bd16f80af 20 ; documentation and/or other materials provided with the distribution.
elessair 0:7e2bd16f80af 21 ; - Neither the name of ARM nor the names of its contributors may be used
elessair 0:7e2bd16f80af 22 ; to endorse or promote products derived from this software without
elessair 0:7e2bd16f80af 23 ; specific prior written permission.
elessair 0:7e2bd16f80af 24 ; *
elessair 0:7e2bd16f80af 25 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:7e2bd16f80af 26 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:7e2bd16f80af 27 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:7e2bd16f80af 28 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:7e2bd16f80af 29 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:7e2bd16f80af 30 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:7e2bd16f80af 31 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:7e2bd16f80af 32 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:7e2bd16f80af 33 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:7e2bd16f80af 34 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:7e2bd16f80af 35 ; POSSIBILITY OF SUCH DAMAGE.
elessair 0:7e2bd16f80af 36 ; ---------------------------------------------------------------------------*/
elessair 0:7e2bd16f80af 37
elessair 0:7e2bd16f80af 38 #ifdef __cplusplus
elessair 0:7e2bd16f80af 39 extern "C" {
elessair 0:7e2bd16f80af 40 #endif
elessair 0:7e2bd16f80af 41
elessair 0:7e2bd16f80af 42 #ifndef _MMU_FUNC_H
elessair 0:7e2bd16f80af 43 #define _MMU_FUNC_H
elessair 0:7e2bd16f80af 44
elessair 0:7e2bd16f80af 45 #define SECTION_DESCRIPTOR (0x2)
elessair 0:7e2bd16f80af 46 #define SECTION_MASK (0xFFFFFFFC)
elessair 0:7e2bd16f80af 47
elessair 0:7e2bd16f80af 48 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
elessair 0:7e2bd16f80af 49 #define SECTION_B_SHIFT (2)
elessair 0:7e2bd16f80af 50 #define SECTION_C_SHIFT (3)
elessair 0:7e2bd16f80af 51 #define SECTION_TEX0_SHIFT (12)
elessair 0:7e2bd16f80af 52 #define SECTION_TEX1_SHIFT (13)
elessair 0:7e2bd16f80af 53 #define SECTION_TEX2_SHIFT (14)
elessair 0:7e2bd16f80af 54
elessair 0:7e2bd16f80af 55 #define SECTION_XN_MASK (0xFFFFFFEF)
elessair 0:7e2bd16f80af 56 #define SECTION_XN_SHIFT (4)
elessair 0:7e2bd16f80af 57
elessair 0:7e2bd16f80af 58 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
elessair 0:7e2bd16f80af 59 #define SECTION_DOMAIN_SHIFT (5)
elessair 0:7e2bd16f80af 60
elessair 0:7e2bd16f80af 61 #define SECTION_P_MASK (0xFFFFFDFF)
elessair 0:7e2bd16f80af 62 #define SECTION_P_SHIFT (9)
elessair 0:7e2bd16f80af 63
elessair 0:7e2bd16f80af 64 #define SECTION_AP_MASK (0xFFFF73FF)
elessair 0:7e2bd16f80af 65 #define SECTION_AP_SHIFT (10)
elessair 0:7e2bd16f80af 66 #define SECTION_AP2_SHIFT (15)
elessair 0:7e2bd16f80af 67
elessair 0:7e2bd16f80af 68 #define SECTION_S_MASK (0xFFFEFFFF)
elessair 0:7e2bd16f80af 69 #define SECTION_S_SHIFT (16)
elessair 0:7e2bd16f80af 70
elessair 0:7e2bd16f80af 71 #define SECTION_NG_MASK (0xFFFDFFFF)
elessair 0:7e2bd16f80af 72 #define SECTION_NG_SHIFT (17)
elessair 0:7e2bd16f80af 73
elessair 0:7e2bd16f80af 74 #define SECTION_NS_MASK (0xFFF7FFFF)
elessair 0:7e2bd16f80af 75 #define SECTION_NS_SHIFT (19)
elessair 0:7e2bd16f80af 76
elessair 0:7e2bd16f80af 77
elessair 0:7e2bd16f80af 78 #define PAGE_L1_DESCRIPTOR (0x1)
elessair 0:7e2bd16f80af 79 #define PAGE_L1_MASK (0xFFFFFFFC)
elessair 0:7e2bd16f80af 80
elessair 0:7e2bd16f80af 81 #define PAGE_L2_4K_DESC (0x2)
elessair 0:7e2bd16f80af 82 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
elessair 0:7e2bd16f80af 83
elessair 0:7e2bd16f80af 84 #define PAGE_L2_64K_DESC (0x1)
elessair 0:7e2bd16f80af 85 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
elessair 0:7e2bd16f80af 86
elessair 0:7e2bd16f80af 87 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
elessair 0:7e2bd16f80af 88 #define PAGE_4K_B_SHIFT (2)
elessair 0:7e2bd16f80af 89 #define PAGE_4K_C_SHIFT (3)
elessair 0:7e2bd16f80af 90 #define PAGE_4K_TEX0_SHIFT (6)
elessair 0:7e2bd16f80af 91 #define PAGE_4K_TEX1_SHIFT (7)
elessair 0:7e2bd16f80af 92 #define PAGE_4K_TEX2_SHIFT (8)
elessair 0:7e2bd16f80af 93
elessair 0:7e2bd16f80af 94 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
elessair 0:7e2bd16f80af 95 #define PAGE_64K_B_SHIFT (2)
elessair 0:7e2bd16f80af 96 #define PAGE_64K_C_SHIFT (3)
elessair 0:7e2bd16f80af 97 #define PAGE_64K_TEX0_SHIFT (12)
elessair 0:7e2bd16f80af 98 #define PAGE_64K_TEX1_SHIFT (13)
elessair 0:7e2bd16f80af 99 #define PAGE_64K_TEX2_SHIFT (14)
elessair 0:7e2bd16f80af 100
elessair 0:7e2bd16f80af 101 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
elessair 0:7e2bd16f80af 102 #define PAGE_B_SHIFT (2)
elessair 0:7e2bd16f80af 103 #define PAGE_C_SHIFT (3)
elessair 0:7e2bd16f80af 104 #define PAGE_TEX_SHIFT (12)
elessair 0:7e2bd16f80af 105
elessair 0:7e2bd16f80af 106 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
elessair 0:7e2bd16f80af 107 #define PAGE_XN_4K_SHIFT (0)
elessair 0:7e2bd16f80af 108 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
elessair 0:7e2bd16f80af 109 #define PAGE_XN_64K_SHIFT (15)
elessair 0:7e2bd16f80af 110
elessair 0:7e2bd16f80af 111
elessair 0:7e2bd16f80af 112 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
elessair 0:7e2bd16f80af 113 #define PAGE_DOMAIN_SHIFT (5)
elessair 0:7e2bd16f80af 114
elessair 0:7e2bd16f80af 115 #define PAGE_P_MASK (0xFFFFFDFF)
elessair 0:7e2bd16f80af 116 #define PAGE_P_SHIFT (9)
elessair 0:7e2bd16f80af 117
elessair 0:7e2bd16f80af 118 #define PAGE_AP_MASK (0xFFFFFDCF)
elessair 0:7e2bd16f80af 119 #define PAGE_AP_SHIFT (4)
elessair 0:7e2bd16f80af 120 #define PAGE_AP2_SHIFT (9)
elessair 0:7e2bd16f80af 121
elessair 0:7e2bd16f80af 122 #define PAGE_S_MASK (0xFFFFFBFF)
elessair 0:7e2bd16f80af 123 #define PAGE_S_SHIFT (10)
elessair 0:7e2bd16f80af 124
elessair 0:7e2bd16f80af 125 #define PAGE_NG_MASK (0xFFFFF7FF)
elessair 0:7e2bd16f80af 126 #define PAGE_NG_SHIFT (11)
elessair 0:7e2bd16f80af 127
elessair 0:7e2bd16f80af 128 #define PAGE_NS_MASK (0xFFFFFFF7)
elessair 0:7e2bd16f80af 129 #define PAGE_NS_SHIFT (3)
elessair 0:7e2bd16f80af 130
elessair 0:7e2bd16f80af 131 #define OFFSET_1M (0x00100000)
elessair 0:7e2bd16f80af 132 #define OFFSET_64K (0x00010000)
elessair 0:7e2bd16f80af 133 #define OFFSET_4K (0x00001000)
elessair 0:7e2bd16f80af 134
elessair 0:7e2bd16f80af 135 #define DESCRIPTOR_FAULT (0x00000000)
elessair 0:7e2bd16f80af 136
elessair 0:7e2bd16f80af 137 /* ########################### MMU Function Access ########################### */
elessair 0:7e2bd16f80af 138 /** \ingroup MMU_FunctionInterface
elessair 0:7e2bd16f80af 139 \defgroup MMU_Functions MMU Functions Interface
elessair 0:7e2bd16f80af 140 @{
elessair 0:7e2bd16f80af 141 */
elessair 0:7e2bd16f80af 142
elessair 0:7e2bd16f80af 143 /* Attributes enumerations */
elessair 0:7e2bd16f80af 144
elessair 0:7e2bd16f80af 145 /* Region size attributes */
elessair 0:7e2bd16f80af 146 typedef enum
elessair 0:7e2bd16f80af 147 {
elessair 0:7e2bd16f80af 148 SECTION,
elessair 0:7e2bd16f80af 149 PAGE_4k,
elessair 0:7e2bd16f80af 150 PAGE_64k,
elessair 0:7e2bd16f80af 151 } mmu_region_size_Type;
elessair 0:7e2bd16f80af 152
elessair 0:7e2bd16f80af 153 /* Region type attributes */
elessair 0:7e2bd16f80af 154 typedef enum
elessair 0:7e2bd16f80af 155 {
elessair 0:7e2bd16f80af 156 NORMAL,
elessair 0:7e2bd16f80af 157 DEVICE,
elessair 0:7e2bd16f80af 158 SHARED_DEVICE,
elessair 0:7e2bd16f80af 159 NON_SHARED_DEVICE,
elessair 0:7e2bd16f80af 160 STRONGLY_ORDERED
elessair 0:7e2bd16f80af 161 } mmu_memory_Type;
elessair 0:7e2bd16f80af 162
elessair 0:7e2bd16f80af 163 /* Region cacheability attributes */
elessair 0:7e2bd16f80af 164 typedef enum
elessair 0:7e2bd16f80af 165 {
elessair 0:7e2bd16f80af 166 NON_CACHEABLE,
elessair 0:7e2bd16f80af 167 WB_WA,
elessair 0:7e2bd16f80af 168 WT,
elessair 0:7e2bd16f80af 169 WB_NO_WA,
elessair 0:7e2bd16f80af 170 } mmu_cacheability_Type;
elessair 0:7e2bd16f80af 171
elessair 0:7e2bd16f80af 172 /* Region parity check attributes */
elessair 0:7e2bd16f80af 173 typedef enum
elessair 0:7e2bd16f80af 174 {
elessair 0:7e2bd16f80af 175 ECC_DISABLED,
elessair 0:7e2bd16f80af 176 ECC_ENABLED,
elessair 0:7e2bd16f80af 177 } mmu_ecc_check_Type;
elessair 0:7e2bd16f80af 178
elessair 0:7e2bd16f80af 179 /* Region execution attributes */
elessair 0:7e2bd16f80af 180 typedef enum
elessair 0:7e2bd16f80af 181 {
elessair 0:7e2bd16f80af 182 EXECUTE,
elessair 0:7e2bd16f80af 183 NON_EXECUTE,
elessair 0:7e2bd16f80af 184 } mmu_execute_Type;
elessair 0:7e2bd16f80af 185
elessair 0:7e2bd16f80af 186 /* Region global attributes */
elessair 0:7e2bd16f80af 187 typedef enum
elessair 0:7e2bd16f80af 188 {
elessair 0:7e2bd16f80af 189 GLOBAL,
elessair 0:7e2bd16f80af 190 NON_GLOBAL,
elessair 0:7e2bd16f80af 191 } mmu_global_Type;
elessair 0:7e2bd16f80af 192
elessair 0:7e2bd16f80af 193 /* Region shareability attributes */
elessair 0:7e2bd16f80af 194 typedef enum
elessair 0:7e2bd16f80af 195 {
elessair 0:7e2bd16f80af 196 NON_SHARED,
elessair 0:7e2bd16f80af 197 SHARED,
elessair 0:7e2bd16f80af 198 } mmu_shared_Type;
elessair 0:7e2bd16f80af 199
elessair 0:7e2bd16f80af 200 /* Region security attributes */
elessair 0:7e2bd16f80af 201 typedef enum
elessair 0:7e2bd16f80af 202 {
elessair 0:7e2bd16f80af 203 SECURE,
elessair 0:7e2bd16f80af 204 NON_SECURE,
elessair 0:7e2bd16f80af 205 } mmu_secure_Type;
elessair 0:7e2bd16f80af 206
elessair 0:7e2bd16f80af 207 /* Region access attributes */
elessair 0:7e2bd16f80af 208 typedef enum
elessair 0:7e2bd16f80af 209 {
elessair 0:7e2bd16f80af 210 NO_ACCESS,
elessair 0:7e2bd16f80af 211 RW,
elessair 0:7e2bd16f80af 212 READ,
elessair 0:7e2bd16f80af 213 } mmu_access_Type;
elessair 0:7e2bd16f80af 214
elessair 0:7e2bd16f80af 215 /* Memory Region definition */
elessair 0:7e2bd16f80af 216 typedef struct RegionStruct {
elessair 0:7e2bd16f80af 217 mmu_region_size_Type rg_t;
elessair 0:7e2bd16f80af 218 mmu_memory_Type mem_t;
elessair 0:7e2bd16f80af 219 uint8_t domain;
elessair 0:7e2bd16f80af 220 mmu_cacheability_Type inner_norm_t;
elessair 0:7e2bd16f80af 221 mmu_cacheability_Type outer_norm_t;
elessair 0:7e2bd16f80af 222 mmu_ecc_check_Type e_t;
elessair 0:7e2bd16f80af 223 mmu_execute_Type xn_t;
elessair 0:7e2bd16f80af 224 mmu_global_Type g_t;
elessair 0:7e2bd16f80af 225 mmu_secure_Type sec_t;
elessair 0:7e2bd16f80af 226 mmu_access_Type priv_t;
elessair 0:7e2bd16f80af 227 mmu_access_Type user_t;
elessair 0:7e2bd16f80af 228 mmu_shared_Type sh_t;
elessair 0:7e2bd16f80af 229
elessair 0:7e2bd16f80af 230 } mmu_region_attributes_Type;
elessair 0:7e2bd16f80af 231
elessair 0:7e2bd16f80af 232 /** \brief Set section execution-never attribute
elessair 0:7e2bd16f80af 233
elessair 0:7e2bd16f80af 234 The function sets section execution-never attribute
elessair 0:7e2bd16f80af 235
elessair 0:7e2bd16f80af 236 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 237 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
elessair 0:7e2bd16f80af 238
elessair 0:7e2bd16f80af 239 \return 0
elessair 0:7e2bd16f80af 240 */
elessair 0:7e2bd16f80af 241 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
elessair 0:7e2bd16f80af 242 {
elessair 0:7e2bd16f80af 243 *descriptor_l1 &= SECTION_XN_MASK;
elessair 0:7e2bd16f80af 244 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
elessair 0:7e2bd16f80af 245 return 0;
elessair 0:7e2bd16f80af 246 }
elessair 0:7e2bd16f80af 247
elessair 0:7e2bd16f80af 248 /** \brief Set section domain
elessair 0:7e2bd16f80af 249
elessair 0:7e2bd16f80af 250 The function sets section domain
elessair 0:7e2bd16f80af 251
elessair 0:7e2bd16f80af 252 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 253 \param [in] domain Section domain
elessair 0:7e2bd16f80af 254
elessair 0:7e2bd16f80af 255 \return 0
elessair 0:7e2bd16f80af 256 */
elessair 0:7e2bd16f80af 257 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
elessair 0:7e2bd16f80af 258 {
elessair 0:7e2bd16f80af 259 *descriptor_l1 &= SECTION_DOMAIN_MASK;
elessair 0:7e2bd16f80af 260 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
elessair 0:7e2bd16f80af 261 return 0;
elessair 0:7e2bd16f80af 262 }
elessair 0:7e2bd16f80af 263
elessair 0:7e2bd16f80af 264 /** \brief Set section parity check
elessair 0:7e2bd16f80af 265
elessair 0:7e2bd16f80af 266 The function sets section parity check
elessair 0:7e2bd16f80af 267
elessair 0:7e2bd16f80af 268 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 269 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
elessair 0:7e2bd16f80af 270
elessair 0:7e2bd16f80af 271 \return 0
elessair 0:7e2bd16f80af 272 */
elessair 0:7e2bd16f80af 273 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
elessair 0:7e2bd16f80af 274 {
elessair 0:7e2bd16f80af 275 *descriptor_l1 &= SECTION_P_MASK;
elessair 0:7e2bd16f80af 276 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
elessair 0:7e2bd16f80af 277 return 0;
elessair 0:7e2bd16f80af 278 }
elessair 0:7e2bd16f80af 279
elessair 0:7e2bd16f80af 280 /** \brief Set section access privileges
elessair 0:7e2bd16f80af 281
elessair 0:7e2bd16f80af 282 The function sets section access privileges
elessair 0:7e2bd16f80af 283
elessair 0:7e2bd16f80af 284 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 285 \param [in] user User Level Access: NO_ACCESS, RW, READ
elessair 0:7e2bd16f80af 286 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
elessair 0:7e2bd16f80af 287 \param [in] afe Access flag enable
elessair 0:7e2bd16f80af 288
elessair 0:7e2bd16f80af 289 \return 0
elessair 0:7e2bd16f80af 290 */
elessair 0:7e2bd16f80af 291 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
elessair 0:7e2bd16f80af 292 {
elessair 0:7e2bd16f80af 293 uint32_t ap = 0;
elessair 0:7e2bd16f80af 294
elessair 0:7e2bd16f80af 295 if (afe == 0) { //full access
elessair 0:7e2bd16f80af 296 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
elessair 0:7e2bd16f80af 297 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:7e2bd16f80af 298 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
elessair 0:7e2bd16f80af 299 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:7e2bd16f80af 300 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:7e2bd16f80af 301 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
elessair 0:7e2bd16f80af 302 }
elessair 0:7e2bd16f80af 303
elessair 0:7e2bd16f80af 304 else { //Simplified access
elessair 0:7e2bd16f80af 305 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:7e2bd16f80af 306 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:7e2bd16f80af 307 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:7e2bd16f80af 308 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
elessair 0:7e2bd16f80af 309 }
elessair 0:7e2bd16f80af 310
elessair 0:7e2bd16f80af 311 *descriptor_l1 &= SECTION_AP_MASK;
elessair 0:7e2bd16f80af 312 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
elessair 0:7e2bd16f80af 313 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
elessair 0:7e2bd16f80af 314
elessair 0:7e2bd16f80af 315 return 0;
elessair 0:7e2bd16f80af 316 }
elessair 0:7e2bd16f80af 317
elessair 0:7e2bd16f80af 318 /** \brief Set section shareability
elessair 0:7e2bd16f80af 319
elessair 0:7e2bd16f80af 320 The function sets section shareability
elessair 0:7e2bd16f80af 321
elessair 0:7e2bd16f80af 322 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 323 \param [in] s_bit Section shareability: NON_SHARED, SHARED
elessair 0:7e2bd16f80af 324
elessair 0:7e2bd16f80af 325 \return 0
elessair 0:7e2bd16f80af 326 */
elessair 0:7e2bd16f80af 327 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
elessair 0:7e2bd16f80af 328 {
elessair 0:7e2bd16f80af 329 *descriptor_l1 &= SECTION_S_MASK;
elessair 0:7e2bd16f80af 330 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
elessair 0:7e2bd16f80af 331 return 0;
elessair 0:7e2bd16f80af 332 }
elessair 0:7e2bd16f80af 333
elessair 0:7e2bd16f80af 334 /** \brief Set section Global attribute
elessair 0:7e2bd16f80af 335
elessair 0:7e2bd16f80af 336 The function sets section Global attribute
elessair 0:7e2bd16f80af 337
elessair 0:7e2bd16f80af 338 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 339 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
elessair 0:7e2bd16f80af 340
elessair 0:7e2bd16f80af 341 \return 0
elessair 0:7e2bd16f80af 342 */
elessair 0:7e2bd16f80af 343 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
elessair 0:7e2bd16f80af 344 {
elessair 0:7e2bd16f80af 345 *descriptor_l1 &= SECTION_NG_MASK;
elessair 0:7e2bd16f80af 346 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
elessair 0:7e2bd16f80af 347 return 0;
elessair 0:7e2bd16f80af 348 }
elessair 0:7e2bd16f80af 349
elessair 0:7e2bd16f80af 350 /** \brief Set section Security attribute
elessair 0:7e2bd16f80af 351
elessair 0:7e2bd16f80af 352 The function sets section Global attribute
elessair 0:7e2bd16f80af 353
elessair 0:7e2bd16f80af 354 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 355 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
elessair 0:7e2bd16f80af 356
elessair 0:7e2bd16f80af 357 \return 0
elessair 0:7e2bd16f80af 358 */
elessair 0:7e2bd16f80af 359 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
elessair 0:7e2bd16f80af 360 {
elessair 0:7e2bd16f80af 361 *descriptor_l1 &= SECTION_NS_MASK;
elessair 0:7e2bd16f80af 362 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
elessair 0:7e2bd16f80af 363 return 0;
elessair 0:7e2bd16f80af 364 }
elessair 0:7e2bd16f80af 365
elessair 0:7e2bd16f80af 366 /* Page 4k or 64k */
elessair 0:7e2bd16f80af 367 /** \brief Set 4k/64k page execution-never attribute
elessair 0:7e2bd16f80af 368
elessair 0:7e2bd16f80af 369 The function sets 4k/64k page execution-never attribute
elessair 0:7e2bd16f80af 370
elessair 0:7e2bd16f80af 371 \param [out] descriptor_l2 L2 descriptor.
elessair 0:7e2bd16f80af 372 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
elessair 0:7e2bd16f80af 373 \param [in] page Page size: PAGE_4k, PAGE_64k,
elessair 0:7e2bd16f80af 374
elessair 0:7e2bd16f80af 375 \return 0
elessair 0:7e2bd16f80af 376 */
elessair 0:7e2bd16f80af 377 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
elessair 0:7e2bd16f80af 378 {
elessair 0:7e2bd16f80af 379 if (page == PAGE_4k)
elessair 0:7e2bd16f80af 380 {
elessair 0:7e2bd16f80af 381 *descriptor_l2 &= PAGE_XN_4K_MASK;
elessair 0:7e2bd16f80af 382 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
elessair 0:7e2bd16f80af 383 }
elessair 0:7e2bd16f80af 384 else
elessair 0:7e2bd16f80af 385 {
elessair 0:7e2bd16f80af 386 *descriptor_l2 &= PAGE_XN_64K_MASK;
elessair 0:7e2bd16f80af 387 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
elessair 0:7e2bd16f80af 388 }
elessair 0:7e2bd16f80af 389 return 0;
elessair 0:7e2bd16f80af 390 }
elessair 0:7e2bd16f80af 391
elessair 0:7e2bd16f80af 392 /** \brief Set 4k/64k page domain
elessair 0:7e2bd16f80af 393
elessair 0:7e2bd16f80af 394 The function sets 4k/64k page domain
elessair 0:7e2bd16f80af 395
elessair 0:7e2bd16f80af 396 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 397 \param [in] domain Page domain
elessair 0:7e2bd16f80af 398
elessair 0:7e2bd16f80af 399 \return 0
elessair 0:7e2bd16f80af 400 */
elessair 0:7e2bd16f80af 401 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
elessair 0:7e2bd16f80af 402 {
elessair 0:7e2bd16f80af 403 *descriptor_l1 &= PAGE_DOMAIN_MASK;
elessair 0:7e2bd16f80af 404 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
elessair 0:7e2bd16f80af 405 return 0;
elessair 0:7e2bd16f80af 406 }
elessair 0:7e2bd16f80af 407
elessair 0:7e2bd16f80af 408 /** \brief Set 4k/64k page parity check
elessair 0:7e2bd16f80af 409
elessair 0:7e2bd16f80af 410 The function sets 4k/64k page parity check
elessair 0:7e2bd16f80af 411
elessair 0:7e2bd16f80af 412 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 413 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
elessair 0:7e2bd16f80af 414
elessair 0:7e2bd16f80af 415 \return 0
elessair 0:7e2bd16f80af 416 */
elessair 0:7e2bd16f80af 417 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
elessair 0:7e2bd16f80af 418 {
elessair 0:7e2bd16f80af 419 *descriptor_l1 &= SECTION_P_MASK;
elessair 0:7e2bd16f80af 420 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
elessair 0:7e2bd16f80af 421 return 0;
elessair 0:7e2bd16f80af 422 }
elessair 0:7e2bd16f80af 423
elessair 0:7e2bd16f80af 424 /** \brief Set 4k/64k page access privileges
elessair 0:7e2bd16f80af 425
elessair 0:7e2bd16f80af 426 The function sets 4k/64k page access privileges
elessair 0:7e2bd16f80af 427
elessair 0:7e2bd16f80af 428 \param [out] descriptor_l2 L2 descriptor.
elessair 0:7e2bd16f80af 429 \param [in] user User Level Access: NO_ACCESS, RW, READ
elessair 0:7e2bd16f80af 430 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
elessair 0:7e2bd16f80af 431 \param [in] afe Access flag enable
elessair 0:7e2bd16f80af 432
elessair 0:7e2bd16f80af 433 \return 0
elessair 0:7e2bd16f80af 434 */
elessair 0:7e2bd16f80af 435 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
elessair 0:7e2bd16f80af 436 {
elessair 0:7e2bd16f80af 437 uint32_t ap = 0;
elessair 0:7e2bd16f80af 438
elessair 0:7e2bd16f80af 439 if (afe == 0) { //full access
elessair 0:7e2bd16f80af 440 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
elessair 0:7e2bd16f80af 441 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:7e2bd16f80af 442 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
elessair 0:7e2bd16f80af 443 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:7e2bd16f80af 444 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:7e2bd16f80af 445 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
elessair 0:7e2bd16f80af 446 }
elessair 0:7e2bd16f80af 447
elessair 0:7e2bd16f80af 448 else { //Simplified access
elessair 0:7e2bd16f80af 449 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
elessair 0:7e2bd16f80af 450 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
elessair 0:7e2bd16f80af 451 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
elessair 0:7e2bd16f80af 452 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
elessair 0:7e2bd16f80af 453 }
elessair 0:7e2bd16f80af 454
elessair 0:7e2bd16f80af 455 *descriptor_l2 &= PAGE_AP_MASK;
elessair 0:7e2bd16f80af 456 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
elessair 0:7e2bd16f80af 457 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
elessair 0:7e2bd16f80af 458
elessair 0:7e2bd16f80af 459 return 0;
elessair 0:7e2bd16f80af 460 }
elessair 0:7e2bd16f80af 461
elessair 0:7e2bd16f80af 462 /** \brief Set 4k/64k page shareability
elessair 0:7e2bd16f80af 463
elessair 0:7e2bd16f80af 464 The function sets 4k/64k page shareability
elessair 0:7e2bd16f80af 465
elessair 0:7e2bd16f80af 466 \param [out] descriptor_l2 L2 descriptor.
elessair 0:7e2bd16f80af 467 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
elessair 0:7e2bd16f80af 468
elessair 0:7e2bd16f80af 469 \return 0
elessair 0:7e2bd16f80af 470 */
elessair 0:7e2bd16f80af 471 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
elessair 0:7e2bd16f80af 472 {
elessair 0:7e2bd16f80af 473 *descriptor_l2 &= PAGE_S_MASK;
elessair 0:7e2bd16f80af 474 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
elessair 0:7e2bd16f80af 475 return 0;
elessair 0:7e2bd16f80af 476 }
elessair 0:7e2bd16f80af 477
elessair 0:7e2bd16f80af 478 /** \brief Set 4k/64k page Global attribute
elessair 0:7e2bd16f80af 479
elessair 0:7e2bd16f80af 480 The function sets 4k/64k page Global attribute
elessair 0:7e2bd16f80af 481
elessair 0:7e2bd16f80af 482 \param [out] descriptor_l2 L2 descriptor.
elessair 0:7e2bd16f80af 483 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
elessair 0:7e2bd16f80af 484
elessair 0:7e2bd16f80af 485 \return 0
elessair 0:7e2bd16f80af 486 */
elessair 0:7e2bd16f80af 487 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
elessair 0:7e2bd16f80af 488 {
elessair 0:7e2bd16f80af 489 *descriptor_l2 &= PAGE_NG_MASK;
elessair 0:7e2bd16f80af 490 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
elessair 0:7e2bd16f80af 491 return 0;
elessair 0:7e2bd16f80af 492 }
elessair 0:7e2bd16f80af 493
elessair 0:7e2bd16f80af 494 /** \brief Set 4k/64k page Security attribute
elessair 0:7e2bd16f80af 495
elessair 0:7e2bd16f80af 496 The function sets 4k/64k page Global attribute
elessair 0:7e2bd16f80af 497
elessair 0:7e2bd16f80af 498 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 499 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
elessair 0:7e2bd16f80af 500
elessair 0:7e2bd16f80af 501 \return 0
elessair 0:7e2bd16f80af 502 */
elessair 0:7e2bd16f80af 503 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
elessair 0:7e2bd16f80af 504 {
elessair 0:7e2bd16f80af 505 *descriptor_l1 &= PAGE_NS_MASK;
elessair 0:7e2bd16f80af 506 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
elessair 0:7e2bd16f80af 507 return 0;
elessair 0:7e2bd16f80af 508 }
elessair 0:7e2bd16f80af 509
elessair 0:7e2bd16f80af 510
elessair 0:7e2bd16f80af 511 /** \brief Set Section memory attributes
elessair 0:7e2bd16f80af 512
elessair 0:7e2bd16f80af 513 The function sets section memory attributes
elessair 0:7e2bd16f80af 514
elessair 0:7e2bd16f80af 515 \param [out] descriptor_l1 L1 descriptor.
elessair 0:7e2bd16f80af 516 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
elessair 0:7e2bd16f80af 517 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:7e2bd16f80af 518 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:7e2bd16f80af 519
elessair 0:7e2bd16f80af 520 \return 0
elessair 0:7e2bd16f80af 521 */
elessair 0:7e2bd16f80af 522 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
elessair 0:7e2bd16f80af 523 {
elessair 0:7e2bd16f80af 524 *descriptor_l1 &= SECTION_TEXCB_MASK;
elessair 0:7e2bd16f80af 525
elessair 0:7e2bd16f80af 526 if (STRONGLY_ORDERED == mem)
elessair 0:7e2bd16f80af 527 {
elessair 0:7e2bd16f80af 528 return 0;
elessair 0:7e2bd16f80af 529 }
elessair 0:7e2bd16f80af 530 else if (SHARED_DEVICE == mem)
elessair 0:7e2bd16f80af 531 {
elessair 0:7e2bd16f80af 532 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
elessair 0:7e2bd16f80af 533 }
elessair 0:7e2bd16f80af 534 else if (NON_SHARED_DEVICE == mem)
elessair 0:7e2bd16f80af 535 {
elessair 0:7e2bd16f80af 536 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
elessair 0:7e2bd16f80af 537 }
elessair 0:7e2bd16f80af 538 else if (NORMAL == mem)
elessair 0:7e2bd16f80af 539 {
elessair 0:7e2bd16f80af 540 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
elessair 0:7e2bd16f80af 541 switch(inner)
elessair 0:7e2bd16f80af 542 {
elessair 0:7e2bd16f80af 543 case NON_CACHEABLE:
elessair 0:7e2bd16f80af 544 break;
elessair 0:7e2bd16f80af 545 case WB_WA:
elessair 0:7e2bd16f80af 546 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
elessair 0:7e2bd16f80af 547 break;
elessair 0:7e2bd16f80af 548 case WT:
elessair 0:7e2bd16f80af 549 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
elessair 0:7e2bd16f80af 550 break;
elessair 0:7e2bd16f80af 551 case WB_NO_WA:
elessair 0:7e2bd16f80af 552 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
elessair 0:7e2bd16f80af 553 break;
elessair 0:7e2bd16f80af 554 }
elessair 0:7e2bd16f80af 555 switch(outer)
elessair 0:7e2bd16f80af 556 {
elessair 0:7e2bd16f80af 557 case NON_CACHEABLE:
elessair 0:7e2bd16f80af 558 break;
elessair 0:7e2bd16f80af 559 case WB_WA:
elessair 0:7e2bd16f80af 560 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
elessair 0:7e2bd16f80af 561 break;
elessair 0:7e2bd16f80af 562 case WT:
elessair 0:7e2bd16f80af 563 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
elessair 0:7e2bd16f80af 564 break;
elessair 0:7e2bd16f80af 565 case WB_NO_WA:
elessair 0:7e2bd16f80af 566 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
elessair 0:7e2bd16f80af 567 break;
elessair 0:7e2bd16f80af 568 }
elessair 0:7e2bd16f80af 569 }
elessair 0:7e2bd16f80af 570
elessair 0:7e2bd16f80af 571 return 0;
elessair 0:7e2bd16f80af 572 }
elessair 0:7e2bd16f80af 573
elessair 0:7e2bd16f80af 574 /** \brief Set 4k/64k page memory attributes
elessair 0:7e2bd16f80af 575
elessair 0:7e2bd16f80af 576 The function sets 4k/64k page memory attributes
elessair 0:7e2bd16f80af 577
elessair 0:7e2bd16f80af 578 \param [out] descriptor_l2 L2 descriptor.
elessair 0:7e2bd16f80af 579 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
elessair 0:7e2bd16f80af 580 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:7e2bd16f80af 581 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
elessair 0:7e2bd16f80af 582
elessair 0:7e2bd16f80af 583 \return 0
elessair 0:7e2bd16f80af 584 */
elessair 0:7e2bd16f80af 585 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
elessair 0:7e2bd16f80af 586 {
elessair 0:7e2bd16f80af 587 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
elessair 0:7e2bd16f80af 588
elessair 0:7e2bd16f80af 589 if (page == PAGE_64k)
elessair 0:7e2bd16f80af 590 {
elessair 0:7e2bd16f80af 591 //same as section
elessair 0:7e2bd16f80af 592 __memory_section(descriptor_l2, mem, outer, inner);
elessair 0:7e2bd16f80af 593 }
elessair 0:7e2bd16f80af 594 else
elessair 0:7e2bd16f80af 595 {
elessair 0:7e2bd16f80af 596 if (STRONGLY_ORDERED == mem)
elessair 0:7e2bd16f80af 597 {
elessair 0:7e2bd16f80af 598 return 0;
elessair 0:7e2bd16f80af 599 }
elessair 0:7e2bd16f80af 600 else if (SHARED_DEVICE == mem)
elessair 0:7e2bd16f80af 601 {
elessair 0:7e2bd16f80af 602 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
elessair 0:7e2bd16f80af 603 }
elessair 0:7e2bd16f80af 604 else if (NON_SHARED_DEVICE == mem)
elessair 0:7e2bd16f80af 605 {
elessair 0:7e2bd16f80af 606 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
elessair 0:7e2bd16f80af 607 }
elessair 0:7e2bd16f80af 608 else if (NORMAL == mem)
elessair 0:7e2bd16f80af 609 {
elessair 0:7e2bd16f80af 610 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
elessair 0:7e2bd16f80af 611 switch(inner)
elessair 0:7e2bd16f80af 612 {
elessair 0:7e2bd16f80af 613 case NON_CACHEABLE:
elessair 0:7e2bd16f80af 614 break;
elessair 0:7e2bd16f80af 615 case WB_WA:
elessair 0:7e2bd16f80af 616 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
elessair 0:7e2bd16f80af 617 break;
elessair 0:7e2bd16f80af 618 case WT:
elessair 0:7e2bd16f80af 619 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
elessair 0:7e2bd16f80af 620 break;
elessair 0:7e2bd16f80af 621 case WB_NO_WA:
elessair 0:7e2bd16f80af 622 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
elessair 0:7e2bd16f80af 623 break;
elessair 0:7e2bd16f80af 624 }
elessair 0:7e2bd16f80af 625 switch(outer)
elessair 0:7e2bd16f80af 626 {
elessair 0:7e2bd16f80af 627 case NON_CACHEABLE:
elessair 0:7e2bd16f80af 628 break;
elessair 0:7e2bd16f80af 629 case WB_WA:
elessair 0:7e2bd16f80af 630 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
elessair 0:7e2bd16f80af 631 break;
elessair 0:7e2bd16f80af 632 case WT:
elessair 0:7e2bd16f80af 633 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
elessair 0:7e2bd16f80af 634 break;
elessair 0:7e2bd16f80af 635 case WB_NO_WA:
elessair 0:7e2bd16f80af 636 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
elessair 0:7e2bd16f80af 637 break;
elessair 0:7e2bd16f80af 638 }
elessair 0:7e2bd16f80af 639 }
elessair 0:7e2bd16f80af 640 }
elessair 0:7e2bd16f80af 641
elessair 0:7e2bd16f80af 642 return 0;
elessair 0:7e2bd16f80af 643 }
elessair 0:7e2bd16f80af 644
elessair 0:7e2bd16f80af 645 /** \brief Create a L1 section descriptor
elessair 0:7e2bd16f80af 646
elessair 0:7e2bd16f80af 647 The function creates a section descriptor.
elessair 0:7e2bd16f80af 648
elessair 0:7e2bd16f80af 649 Assumptions:
elessair 0:7e2bd16f80af 650 - 16MB super sections not suported
elessair 0:7e2bd16f80af 651 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
elessair 0:7e2bd16f80af 652 - Functions always return 0
elessair 0:7e2bd16f80af 653
elessair 0:7e2bd16f80af 654 \param [out] descriptor L1 descriptor
elessair 0:7e2bd16f80af 655 \param [out] descriptor2 L2 descriptor
elessair 0:7e2bd16f80af 656 \param [in] reg Section attributes
elessair 0:7e2bd16f80af 657
elessair 0:7e2bd16f80af 658 \return 0
elessair 0:7e2bd16f80af 659 */
elessair 0:7e2bd16f80af 660 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
elessair 0:7e2bd16f80af 661 {
elessair 0:7e2bd16f80af 662 *descriptor = 0;
elessair 0:7e2bd16f80af 663
elessair 0:7e2bd16f80af 664 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
elessair 0:7e2bd16f80af 665 __xn_section(descriptor,reg.xn_t);
elessair 0:7e2bd16f80af 666 __domain_section(descriptor, reg.domain);
elessair 0:7e2bd16f80af 667 __p_section(descriptor, reg.e_t);
elessair 0:7e2bd16f80af 668 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
elessair 0:7e2bd16f80af 669 __shared_section(descriptor,reg.sh_t);
elessair 0:7e2bd16f80af 670 __global_section(descriptor,reg.g_t);
elessair 0:7e2bd16f80af 671 __secure_section(descriptor,reg.sec_t);
elessair 0:7e2bd16f80af 672 *descriptor &= SECTION_MASK;
elessair 0:7e2bd16f80af 673 *descriptor |= SECTION_DESCRIPTOR;
elessair 0:7e2bd16f80af 674
elessair 0:7e2bd16f80af 675 return 0;
elessair 0:7e2bd16f80af 676
elessair 0:7e2bd16f80af 677 }
elessair 0:7e2bd16f80af 678
elessair 0:7e2bd16f80af 679
elessair 0:7e2bd16f80af 680 /** \brief Create a L1 and L2 4k/64k page descriptor
elessair 0:7e2bd16f80af 681
elessair 0:7e2bd16f80af 682 The function creates a 4k/64k page descriptor.
elessair 0:7e2bd16f80af 683 Assumptions:
elessair 0:7e2bd16f80af 684 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
elessair 0:7e2bd16f80af 685 - Functions always return 0
elessair 0:7e2bd16f80af 686
elessair 0:7e2bd16f80af 687 \param [out] descriptor L1 descriptor
elessair 0:7e2bd16f80af 688 \param [out] descriptor2 L2 descriptor
elessair 0:7e2bd16f80af 689 \param [in] reg 4k/64k page attributes
elessair 0:7e2bd16f80af 690
elessair 0:7e2bd16f80af 691 \return 0
elessair 0:7e2bd16f80af 692 */
elessair 0:7e2bd16f80af 693 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
elessair 0:7e2bd16f80af 694 {
elessair 0:7e2bd16f80af 695 *descriptor = 0;
elessair 0:7e2bd16f80af 696 *descriptor2 = 0;
elessair 0:7e2bd16f80af 697
elessair 0:7e2bd16f80af 698 switch (reg.rg_t)
elessair 0:7e2bd16f80af 699 {
elessair 0:7e2bd16f80af 700 case PAGE_4k:
elessair 0:7e2bd16f80af 701 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
elessair 0:7e2bd16f80af 702 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
elessair 0:7e2bd16f80af 703 __domain_page(descriptor, reg.domain);
elessair 0:7e2bd16f80af 704 __p_page(descriptor, reg.e_t);
elessair 0:7e2bd16f80af 705 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
elessair 0:7e2bd16f80af 706 __shared_page(descriptor2,reg.sh_t);
elessair 0:7e2bd16f80af 707 __global_page(descriptor2,reg.g_t);
elessair 0:7e2bd16f80af 708 __secure_page(descriptor,reg.sec_t);
elessair 0:7e2bd16f80af 709 *descriptor &= PAGE_L1_MASK;
elessair 0:7e2bd16f80af 710 *descriptor |= PAGE_L1_DESCRIPTOR;
elessair 0:7e2bd16f80af 711 *descriptor2 &= PAGE_L2_4K_MASK;
elessair 0:7e2bd16f80af 712 *descriptor2 |= PAGE_L2_4K_DESC;
elessair 0:7e2bd16f80af 713 break;
elessair 0:7e2bd16f80af 714
elessair 0:7e2bd16f80af 715 case PAGE_64k:
elessair 0:7e2bd16f80af 716 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
elessair 0:7e2bd16f80af 717 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
elessair 0:7e2bd16f80af 718 __domain_page(descriptor, reg.domain);
elessair 0:7e2bd16f80af 719 __p_page(descriptor, reg.e_t);
elessair 0:7e2bd16f80af 720 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
elessair 0:7e2bd16f80af 721 __shared_page(descriptor2,reg.sh_t);
elessair 0:7e2bd16f80af 722 __global_page(descriptor2,reg.g_t);
elessair 0:7e2bd16f80af 723 __secure_page(descriptor,reg.sec_t);
elessair 0:7e2bd16f80af 724 *descriptor &= PAGE_L1_MASK;
elessair 0:7e2bd16f80af 725 *descriptor |= PAGE_L1_DESCRIPTOR;
elessair 0:7e2bd16f80af 726 *descriptor2 &= PAGE_L2_64K_MASK;
elessair 0:7e2bd16f80af 727 *descriptor2 |= PAGE_L2_64K_DESC;
elessair 0:7e2bd16f80af 728 break;
elessair 0:7e2bd16f80af 729
elessair 0:7e2bd16f80af 730 case SECTION:
elessair 0:7e2bd16f80af 731 //error
elessair 0:7e2bd16f80af 732 break;
elessair 0:7e2bd16f80af 733
elessair 0:7e2bd16f80af 734 }
elessair 0:7e2bd16f80af 735
elessair 0:7e2bd16f80af 736 return 0;
elessair 0:7e2bd16f80af 737
elessair 0:7e2bd16f80af 738 }
elessair 0:7e2bd16f80af 739
elessair 0:7e2bd16f80af 740 /** \brief Create a 1MB Section
elessair 0:7e2bd16f80af 741
elessair 0:7e2bd16f80af 742 \param [in] ttb Translation table base address
elessair 0:7e2bd16f80af 743 \param [in] base_address Section base address
elessair 0:7e2bd16f80af 744 \param [in] count Number of sections to create
elessair 0:7e2bd16f80af 745 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:7e2bd16f80af 746
elessair 0:7e2bd16f80af 747 */
elessair 0:7e2bd16f80af 748 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
elessair 0:7e2bd16f80af 749 {
elessair 0:7e2bd16f80af 750 uint32_t offset;
elessair 0:7e2bd16f80af 751 uint32_t entry;
elessair 0:7e2bd16f80af 752 uint32_t i;
elessair 0:7e2bd16f80af 753
elessair 0:7e2bd16f80af 754 offset = base_address >> 20;
elessair 0:7e2bd16f80af 755 entry = (base_address & 0xFFF00000) | descriptor_l1;
elessair 0:7e2bd16f80af 756
elessair 0:7e2bd16f80af 757 //4 bytes aligned
elessair 0:7e2bd16f80af 758 ttb = ttb + offset;
elessair 0:7e2bd16f80af 759
elessair 0:7e2bd16f80af 760 for (i = 0; i < count; i++ )
elessair 0:7e2bd16f80af 761 {
elessair 0:7e2bd16f80af 762 //4 bytes aligned
elessair 0:7e2bd16f80af 763 *ttb++ = entry;
elessair 0:7e2bd16f80af 764 entry += OFFSET_1M;
elessair 0:7e2bd16f80af 765 }
elessair 0:7e2bd16f80af 766 }
elessair 0:7e2bd16f80af 767
elessair 0:7e2bd16f80af 768 /** \brief Create a 4k page entry
elessair 0:7e2bd16f80af 769
elessair 0:7e2bd16f80af 770 \param [in] ttb L1 table base address
elessair 0:7e2bd16f80af 771 \param [in] base_address 4k base address
elessair 0:7e2bd16f80af 772 \param [in] count Number of 4k pages to create
elessair 0:7e2bd16f80af 773 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:7e2bd16f80af 774 \param [in] ttb_l2 L2 table base address
elessair 0:7e2bd16f80af 775 \param [in] descriptor_l2 L2 descriptor (region attributes)
elessair 0:7e2bd16f80af 776
elessair 0:7e2bd16f80af 777 */
elessair 0:7e2bd16f80af 778 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
elessair 0:7e2bd16f80af 779 {
elessair 0:7e2bd16f80af 780
elessair 0:7e2bd16f80af 781 uint32_t offset, offset2;
elessair 0:7e2bd16f80af 782 uint32_t entry, entry2;
elessair 0:7e2bd16f80af 783 uint32_t i;
elessair 0:7e2bd16f80af 784
elessair 0:7e2bd16f80af 785
elessair 0:7e2bd16f80af 786 offset = base_address >> 20;
elessair 0:7e2bd16f80af 787 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
elessair 0:7e2bd16f80af 788
elessair 0:7e2bd16f80af 789 //4 bytes aligned
elessair 0:7e2bd16f80af 790 ttb += offset;
elessair 0:7e2bd16f80af 791 //create l1_entry
elessair 0:7e2bd16f80af 792 *ttb = entry;
elessair 0:7e2bd16f80af 793
elessair 0:7e2bd16f80af 794 offset2 = (base_address & 0xff000) >> 12;
elessair 0:7e2bd16f80af 795 ttb_l2 += offset2;
elessair 0:7e2bd16f80af 796 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
elessair 0:7e2bd16f80af 797 for (i = 0; i < count; i++ )
elessair 0:7e2bd16f80af 798 {
elessair 0:7e2bd16f80af 799 //4 bytes aligned
elessair 0:7e2bd16f80af 800 *ttb_l2++ = entry2;
elessair 0:7e2bd16f80af 801 entry2 += OFFSET_4K;
elessair 0:7e2bd16f80af 802 }
elessair 0:7e2bd16f80af 803 }
elessair 0:7e2bd16f80af 804
elessair 0:7e2bd16f80af 805 /** \brief Create a 64k page entry
elessair 0:7e2bd16f80af 806
elessair 0:7e2bd16f80af 807 \param [in] ttb L1 table base address
elessair 0:7e2bd16f80af 808 \param [in] base_address 64k base address
elessair 0:7e2bd16f80af 809 \param [in] count Number of 64k pages to create
elessair 0:7e2bd16f80af 810 \param [in] descriptor_l1 L1 descriptor (region attributes)
elessair 0:7e2bd16f80af 811 \param [in] ttb_l2 L2 table base address
elessair 0:7e2bd16f80af 812 \param [in] descriptor_l2 L2 descriptor (region attributes)
elessair 0:7e2bd16f80af 813
elessair 0:7e2bd16f80af 814 */
elessair 0:7e2bd16f80af 815 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
elessair 0:7e2bd16f80af 816 {
elessair 0:7e2bd16f80af 817 uint32_t offset, offset2;
elessair 0:7e2bd16f80af 818 uint32_t entry, entry2;
elessair 0:7e2bd16f80af 819 uint32_t i,j;
elessair 0:7e2bd16f80af 820
elessair 0:7e2bd16f80af 821
elessair 0:7e2bd16f80af 822 offset = base_address >> 20;
elessair 0:7e2bd16f80af 823 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
elessair 0:7e2bd16f80af 824
elessair 0:7e2bd16f80af 825 //4 bytes aligned
elessair 0:7e2bd16f80af 826 ttb += offset;
elessair 0:7e2bd16f80af 827 //create l1_entry
elessair 0:7e2bd16f80af 828 *ttb = entry;
elessair 0:7e2bd16f80af 829
elessair 0:7e2bd16f80af 830 offset2 = (base_address & 0xff000) >> 12;
elessair 0:7e2bd16f80af 831 ttb_l2 += offset2;
elessair 0:7e2bd16f80af 832 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
elessair 0:7e2bd16f80af 833 for (i = 0; i < count; i++ )
elessair 0:7e2bd16f80af 834 {
elessair 0:7e2bd16f80af 835 //create 16 entries
elessair 0:7e2bd16f80af 836 for (j = 0; j < 16; j++)
elessair 0:7e2bd16f80af 837 //4 bytes aligned
elessair 0:7e2bd16f80af 838 *ttb_l2++ = entry2;
elessair 0:7e2bd16f80af 839 entry2 += OFFSET_64K;
elessair 0:7e2bd16f80af 840 }
elessair 0:7e2bd16f80af 841 }
elessair 0:7e2bd16f80af 842
elessair 0:7e2bd16f80af 843 /*@} end of MMU_Functions */
elessair 0:7e2bd16f80af 844 #endif
elessair 0:7e2bd16f80af 845
elessair 0:7e2bd16f80af 846 #ifdef __cplusplus
elessair 0:7e2bd16f80af 847 }
elessair 0:7e2bd16f80af 848 #endif