Revision 0:3927c6d8ad1f, committed 2015-09-06

Comitter:

baxterja

Date:

Sun Sep 06 04:23:51 2015 +0000

Child:

1:f0a5690db73f

Commit message:

Chemical Sensing program

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Sun Sep 06 04:23:51 2015 +0000
@@ -0,0 +1,978 @@
+
+// TODO: 
+#include "mbed.h"
+#include <string>
+
+#include <stdio.h>
+#include "PeripheralNames.h"
+#include "PeripheralPins.h"
+#include "fsl_adc_hal.h"
+#include "fsl_clock_manager.h"
+#include "fsl_dspi_hal.h"
+
+
+
+Serial pc(USBTX, USBRX);
+
+/*
+#if DEBUG
+#define DEBUG_PRINT(x) pc.printf(x)
+#else
+#define DEBUG_PRINT(x) do {} while(0)
+#endif
+*/
+DigitalOut led_red(LED_RED);
+DigitalOut led_green(LED_GREEN);
+DigitalOut led_blue(LED_BLUE);
+
+
+#define MAX_FADC 6000000
+
+#define TimerInterruptInMicroSeconds 25 // This is for 40 kHz
+
+
+#define CarrierFrequency 190
+
+#define ISR_counter_loop_reset 4 // 10 kHz sampling of the signal
+
+int ISR_counter = 1;
+
+#define MaxNumSamples 0  //set to 0 if want continuous sampling (i.e. run forever)
+#define NumSamplesAverageInADC 32 //hardware averaging default is 2. values 0..32. Higher values reduce noise and maximum sample rate
+#define NumADCbits 16
+
+int CyclesInState = 0;
+// While 32 is the minimum, it seems to take a few cycles to get things to work right. 32 + 18 + 18 + 18
+#define PreCalculateCycles 256
+#define NumCalculatedAverages 500
+
+AnalogOut WaveOut(DAC0_OUT);
+AnalogIn WaveIn1(A0);
+AnalogIn WaveIn2(A2);
+
+
+double previousTime = 0;
+
+
+volatile unsigned long counter = 0; //keep track of how many times the timer interrupt executes
+
+
+volatile int phase_counter = 0;
+float twopi = 3.14159265359 * 2;
+
+#define pre_compute_length 4000
+float i_mod_pre[pre_compute_length];
+float q_mod_pre[pre_compute_length];
+int out_val_pre[pre_compute_length]; 
+
+float current_i_mod;
+float current_q_mod;
+
+
+#define lp_fir_length 256
+#define bp_fir_length 256
+
+float x_0_i[lp_fir_length];
+float x_0_q[lp_fir_length];
+float x_1_i[lp_fir_length];
+float x_1_q[lp_fir_length];
+
+float real_ip = 0;
+float real_ip_total = 0;
+float imag_ip = 0;
+float imag_ip_total = 0;
+float y_0_squared = 0;
+float y_1_squared = 0;
+
+int max_0 = -1;
+int min_0 = 65536;
+int max_1 = -1;
+int min_1 = 65536;
+
+
+// Coefficients for FIR low-pass filter
+// Order: 127
+// Fs = 10000
+// Fpass = 5
+// Fstop = 50
+// Density Factor 20
+float lp_filter_coeff[lp_fir_length] = {
+0.0861805974737537,
+0.00194058236914933,
+0.00196838475539374,
+0.00198494885848217,
+0.00201327315570587,
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+0.00244169878557599,
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+0.00226646783939495,
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+0.00198494885848217,
+0.00196838475539374,
+0.00194058236914933,
+0.0861805974737537
+};
+
+
+// Coefficients for FIR band-pass filter (single-precision floating)
+// Order: 255
+// Fs = 10000
+// Fstop1 = 140
+// Fpass1 = 180
+// Fpass2 = 200
+// Fstop2 = 240  
+// Density Factor 20
+float bp_filter_coeff[bp_fir_length] = {
+-0.0222569832875342,
+-0.000668571820934435,
+-0.000617098880070943,
+-0.000526912832180624,
+-0.000394083108191473,
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+-1.40519139447993e-05,
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+-0.000668571820934435,
+-0.0222569832875342
+};
+
+
+int lp_fifo_num = 1;
+int bp_fifo_num = 1;
+
+float x_0[bp_fir_length];
+float x_1[bp_fir_length];
+
+int value[] = {0,0};
+
+float mag = 0;
+float calc_mag = 0;
+double mag_total = 0;
+float calc_phase = 0;
+int NumInBlock = 0;
+
+float mag_result = 0;
+float phase_result = 0;
+/*
+int diff_0[3] = {0, 0, 0};
+int diff_1[3] = {0, 0, 0};
+*/
+double final_mag = 0;
+float final_phase = 0;
+
+// Finite State Machine
+int current_state = 0;
+
+// Flag
+bool ADC_reading = false;
+bool isTransmitting = false;
+
+
+//IntervalTimer timer0;
+Ticker timer0;
+Timer t1;
+
+int adc_cal(void)
+{
+    ADC0_CFG1 |= (ADC_CFG1_MODE(3)  | // 16 bits mode
+                  ADC_CFG1_ADICLK(1)| // Input Bus Clock divided by 2 (20-25 MHz out of reset (FEI mode) / 2)
+                  ADC_CFG1_ADIV(2)) ; // Clock divide by 4 (2.5-3 MHz)
+    
+    ADC0_SC3 |= ADC_SC3_AVGE_MASK |   // Enable HW average
+                ADC_SC3_AVGS(3)   |   // Set HW average of 32 samples
+                ADC_SC3_CAL_MASK;     // Start calibration process
+    
+    while(ADC0_SC3 & ADC_SC3_CAL_MASK); // Wait for calibration to end
+    
+    if(ADC0_SC3 & ADC_SC3_CALF_MASK) return 1;  // Check for successful calibration
+    
+    uint16_t calib = 0; // calibration variable 
+    calib += ADC0->CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
+    calib /= 2;
+    calib |= 0x8000;    // Set MSB 
+    ADC0_PG = calib;
+    calib = 0;
+    calib += ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
+    calib /= 2;
+    calib |= 0x8000;    // Set MSB
+    ADC0_MG = calib;
+    
+    return 0;
+}
+
+void adc_init()
+{
+    // red, indicating not ready
+
+    
+    // Turn on the ADC0 and ADC1 clocks
+    SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
+    SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
+    
+    
+     __disable_irq();
+     adc_cal();
+    //if(adc_cal()) {red = 0; green = 0;} // if calibration fails, display yellow
+    __enable_irq();
+
+
+    
+    // Setup Configuration Register 1 
+    ADC0_CFG1 = 0; // clear register
+    ADC0_CFG1 |= ADC_CFG1_ADICLK(0);    // select bus clock
+    ADC0_CFG1 |= ADC_CFG1_MODE(3);      // select 16-bit 2's complement output  
+    ADC0_CFG1 |= ADC_CFG1_ADIV(0);      // clock divisor = 0.
+    ADC0_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time   //QUESTION
+    ADC0_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
+    ADC1_CFG1 = 0; // clear register
+    ADC1_CFG1 |= ADC_CFG1_ADICLK(0);    // select bus clock
+    ADC1_CFG1 |= ADC_CFG1_MODE(3);      // select 16-bit 2's complement output
+    ADC1_CFG1 |= ADC_CFG1_ADIV(0);      // clock divisor = 0.
+    ADC1_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
+    ADC1_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
+    
+    // Setup Configuration Register 2 
+    ADC0_CFG2 = 0; // clear register
+    //ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
+    ADC0_CFG2 |= ADC_CFG2_MUXSEL_MASK; // select a channels    //possibly change to channel b.
+    ADC1_CFG2 = 0; // clear register
+    //ADC1_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
+    ADC1_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels    
+    
+    // Setup Status and Control Register 2 
+    ADC0_SC2 = 0;                    // clear register
+    ADC0_SC2 |= ADC_SC2_REFSEL(0);   // select external voltage reference   //QUESTION
+    //ADC0_SC2 |= ADC_SC2_DMAEN_MASK;  // enable DMA
+    //ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select hardware trigger  //QESTION
+    ADC1_SC2 = 0;                    // clear register
+    ADC1_SC2 |= ADC_SC2_REFSEL(0);   // select external voltage reference
+    //ADC1_SC2 |= ADC_SC2_DMAEN_MASK;  // enable DMA
+    //ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select hardware trigger
+    
+    // Setup Status and Control Register 3 now that calibration is complete
+    ADC0_SC3 = 0; // Hardware Average set to 4 samples averaged
+                  // Hardware Average Disabled
+                  // select single conversion mode
+    ADC1_SC3 = 0; // Hardware Average set to 4 samples averaged
+                  // Hardware Average Disabled
+                  // select single conversion mode
+    //ADC1_SC3 = ADC_SC3_AVGS(0) |  ADC_SC3_AVGE_MASK;//JARED COME BACK AND LOOK AT THIS
+    
+    // Setup Status and Control Register 1A 
+    ADC0_SC1A = 0; // clear register
+    ADC0_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
+    ADC0_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
+    ADC0_SC1A |= ADC_SC1_ADCH(12);   // select channel 13
+    ADC1_SC1A = 0; // clear register
+    ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
+    ADC1_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
+    ADC1_SC1A |= ADC_SC1_ADCH(14);   // select channel 14
+    
+    
+    // Check if ADC is finished initializing  TODO:  This part doesn't seem right, but I did it according to 871
+    while( (ADC0_SC1B&ADC_SC1_COCO_MASK)) {}
+    int gain = ADC0_RA; // read the register to clear SC1A[COCO]  //possibly a
+    while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
+    gain = ADC1_RA; // read the register to clear SC1A[COCO]
+    
+    
+//QUESTION
+    ADC0_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
+    ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
+    ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
+    ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
+    ADC0_SC1A |= ADC_SC1_ADCH(12);   // write to SC1B causing a trigger
+    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
+}
+
+
+
+void pre_compute_tables() {
+  // This function will precompute the cos and sin tables used in the rest of the program
+  for(int precompute_counter = 0; precompute_counter < pre_compute_length; precompute_counter++){
+    out_val_pre[precompute_counter] = (int) (cos(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter) * 32500.0 + 33000.0);
+    i_mod_pre[precompute_counter] = (cos(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter));
+    q_mod_pre[precompute_counter] = (-sin(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter));
+
+  }
+} //pre_compute_tables
+
+
+
+
+void ISR_repeat() {//40 KHz
+  // Calculation of loop for generating signal to output on DAC
+  
+  WaveOut.write_u16(out_val_pre[phase_counter]);  //creates a wave that bounces between 0 & 3.3 V
+
+  // ISR counter reset and increment
+  if (ISR_counter >= ISR_counter_loop_reset)//10KHz
+  {
+    ISR_counter = 1;
+  //JARED ADD THESE 2 LINES BACK IN
+    ADC0_SC1A |= ADC_SC1_ADCH(12);   // start ADC process Possibly change to B.
+    ADC1_SC1A |= ADC_SC1_ADCH(14);   // start ADC process
+    
+    ADC_reading = true;
+    current_i_mod = i_mod_pre[phase_counter];
+    current_q_mod = q_mod_pre[phase_counter];
+  }
+  else {
+    ISR_counter++;
+  }
+  
+  phase_counter++;
+  if (phase_counter >= pre_compute_length) phase_counter = 0;
+  
+} //ISR_repeat
+
+
+void execute_DSP() {
+bp_fifo_num++;  
+  if (bp_fifo_num >= bp_fir_length) bp_fifo_num = 0;
+
+   x_0[bp_fifo_num] = (float) (value[1] - value[0]);
+   x_1[bp_fifo_num] = (float) (value[0] - 32768);
+
+   // Band pass filter of incoming data
+  float y_0 = x_0[bp_fifo_num] * bp_filter_coeff[0];
+  float y_1 = x_1[bp_fifo_num] * bp_filter_coeff[0];
+  
+  for(int fir_counter = 1; fir_counter < bp_fir_length; fir_counter++){
+    int fir_index = bp_fifo_num + fir_counter;
+    if (fir_index >= bp_fir_length) {
+      fir_index -= bp_fir_length;
+    }
+    y_0 += x_0[fir_index] * bp_filter_coeff[fir_counter];
+    y_1 += x_1[fir_index] * bp_filter_coeff[fir_counter];
+  }
+
+  current_i_mod = i_mod_pre[phase_counter];
+  current_q_mod = q_mod_pre[phase_counter];
+
+  // Demodulation of the signal
+  x_0_i[lp_fifo_num] = (y_0 * current_i_mod);
+  x_0_q[lp_fifo_num] = (y_0 * current_q_mod);
+  x_1_i[lp_fifo_num] = (y_1 * current_i_mod);
+  x_1_q[lp_fifo_num] = (y_1 * current_q_mod); 
+
+  lp_fifo_num++;  
+  if (lp_fifo_num >= lp_fir_length) lp_fifo_num = 0;
+
+  // Low pass filter of demodulated signal
+  float y_0_i = x_0_i[lp_fifo_num] * lp_filter_coeff[0];
+  float y_0_q = x_0_q[lp_fifo_num] * lp_filter_coeff[0];
+  float y_1_i = x_1_i[lp_fifo_num] * lp_filter_coeff[0];
+  float y_1_q = x_1_q[lp_fifo_num] * lp_filter_coeff[0];
+
+  for(int fir_counter = 1; fir_counter < lp_fir_length; fir_counter++){
+    int fir_index = lp_fifo_num + fir_counter;
+    if (fir_index >= lp_fir_length) {
+      fir_index -= lp_fir_length;
+    }
+    y_0_i += x_0_i[fir_index] * lp_filter_coeff[fir_counter];
+    y_0_q += x_0_q[fir_index] * lp_filter_coeff[fir_counter];
+    y_1_i += x_1_i[fir_index] * lp_filter_coeff[fir_counter];
+    y_1_q += x_1_q[fir_index] * lp_filter_coeff[fir_counter];
+  }  
+   
+  real_ip = y_0_i * y_1_i + y_0_q * y_1_q;
+  imag_ip = y_0_q * y_1_i - y_0_i * y_1_q;
+  y_0_squared = y_0_i * y_0_i + y_0_q * y_0_q; 
+  y_1_squared = y_1_i * y_1_i + y_1_q * y_1_q;
+
+//  float mag = sqrt((real_ip * real_ip + imag_ip * imag_ip) / y_0_squared;
+  mag = sqrt(((float) real_ip * (float) real_ip + (float) imag_ip * (float) imag_ip)) / ((float) y_0_squared);
+  mag_total += mag;
+  calc_mag = mag_total / NumInBlock;
+
+  real_ip_total += real_ip;
+  imag_ip_total += imag_ip;
+  calc_phase = -atan2(imag_ip_total, real_ip_total);
+}
+
+
+
+void setup() { 
+  adc_init();
+  pre_compute_tables();
+  wait(1); 
+} //setup
+
+using namespace std;
+ 
+int main() {
+    led_blue = 1;
+    led_green = 1;
+    led_red = 0;
+    
+    setup();
+    int count = 0;
+    t1.start();
+    
+    pc.baud(115200);
+    
+    for(int i = 0; i < 86; i++) 
+    {
+        if(NVIC_GetPriority((IRQn_Type) i) == 0) NVIC_SetPriority((IRQn_Type) i, 2);
+    }
+    
+    // Give hardware associated with 
+    // sampling the highest priority
+    NVIC_SetPriority(ADC1_IRQn,0);
+    NVIC_SetPriority(ADC0_IRQn,0);
+    NVIC_SetPriority(PDB0_IRQn,0);
+    NVIC_SetPriority(DMA0_IRQn,0);
+    NVIC_SetPriority(DMA1_IRQn,0);
+    NVIC_SetPriority(DMA2_IRQn,0);
+    
+    NVIC_SetPriority(ENET_1588_Timer_IRQn,1);
+    NVIC_SetPriority(ENET_Transmit_IRQn,1);
+    NVIC_SetPriority(ENET_Receive_IRQn,1);
+    NVIC_SetPriority(ENET_Error_IRQn,1);
+
+    led_green = 1;
+    led_red = 1;
+    led_blue = 1;
+
+    timer0.attach_us(&ISR_repeat, TimerInterruptInMicroSeconds);
+    while(true) {
+                
+                count++;
+                //printf("Loop");
+                
+                while (!ADC_reading)  
+                {
+                    
+                led_blue = 0;
+                }
+
+            
+              counter++;
+              
+              CyclesInState++;
+              
+              
+              execute_DSP();
+              
+              if (CyclesInState <= PreCalculateCycles) {
+                NumInBlock = 0;
+                mag_total = 0;
+                real_ip_total = 0;
+                imag_ip_total = 0;
+        
+                max_0 = -1;
+                max_1 = -1;
+                min_0 = 65536;
+                min_1 = 65536;
+              }
+              else {
+                NumInBlock++;
+                if (NumInBlock >= NumCalculatedAverages) {
+                  mag_result = calc_mag;
+                  phase_result = calc_phase;
+                  final_mag = mag_result;
+                  final_phase = phase_result;
+                  NumInBlock = 0;
+                  mag_total = 0;
+                  real_ip_total = 0;
+                  imag_ip_total = 0;
+                  printf("Coeficient%f Phase%f\n\r", final_mag, final_phase);
+                }
+              }
+              
+                      
+          value[0] = ADC0_RA;//Read adc
+          value[1] = ADC1_RA;//Read adc
+          //printf("%f %f\n\r", value[0], value[1]);
+          ADC_reading = false;//lower flag
+
+    }// end while(true) 
+}// end main

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Sun Sep 06 04:23:51 2015 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/ba1f97679dad
\ No newline at end of file