Diff: Sample/dma.cpp

Revision:

4:9fd291254686

Parent:

3:a85b742be262

Child:

7:af255a90505e

--- a/Sample/dma.cpp	Sat Oct 31 20:06:37 2015 +0000
+++ b/Sample/dma.cpp	Fri Nov 06 03:33:09 2015 +0000
@@ -13,25 +13,39 @@
 int len = TOTAL_SAMPLES;
 uint16_t sample_array0[TOTAL_SAMPLES];
 uint16_t sample_array1[TOTAL_SAMPLES];
-uint16_t angle_array[TOTAL_SAMPLES+FILENAME_SIZE];//Change this to DAC Values
+//uint16_t out_val_pre[TOTAL_SAMPLES];//Change this to DAC Values
 bool dma_done = false;
 bool dma_half_done = false;
 
-
+#define pre_compute_length 2000
+#define DMA_PERIOD .00001
+#define DMA_FREQUENCY 100000
+#define CARRIERFREQUENCY 10000
+#define twopi 3.14159265359 * 2
 
 /*  DMA0 and DMA1 are triggered by ADC0 and ADC1 (which are triggered
  *  by the PDB).  However, DMA2 is triggered directly by the PDB.  This
  *  is becuase DMA2 is reading FTM2, which cannot trigger the DMA.   */
 void dma_init()
 {
+//    for(int precompute_counter = 0; precompute_counter < TOTAL_SAMPLES; precompute_counter++){
+//        out_val_pre[precompute_counter] = (int) (cos(twopi * CARRIERFREQUENCY * DMA_PERIOD * precompute_counter) * 4965.0 + 49650.0);   
+//  }
+    
     toggle_dma0 = 1;
     toggle_dma1 = 1;
     toggle_dma2 = 1;
     // Enable clock for DMAMUX and DMA
+    //SIM_SCGC2 |= SIM_SCGC2_DAC0_MASK;
+    //SIM_SCGC6 |= SIM_SCGC6_DAC0_MASK;
+    
+    
     SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
     SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;  
     SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // make sure clock is enabled for FTM2  
-            
+
+    
+    
     // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
     DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
     DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
@@ -54,8 +68,8 @@
     DMA_TCD0_DADDR = (uint32_t) sample_array0;
     DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
     DMA_TCD1_DADDR = (uint32_t) sample_array1;
-    DMA_TCD2_SADDR = (uint32_t) &FTM2_CNT;
-    DMA_TCD2_DADDR = (uint32_t) angle_array;
+    //DMA_TCD2_SADDR = (uint32_t) &out_val_pre[0];//&FTM2_CNT;
+    //DMA_TCD2_DADDR = (uint32_t) &DAC0_DAT0L;
     
     // Set an offset for source and destination address
     DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
@@ -64,26 +78,26 @@
     DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
     
     //DAC DMA Chang soff to 2, and DOFF to 0
-    DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
-    DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
+    //DMA_TCD2_SOFF = 0x02; // Source address offset of 2 bits per transaction
+    //DMA_TCD2_DOFF = 0x00; // Destination address offset of 1 bit per transaction
         
     // Set source and destination data transfer size
     DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
     DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
-    DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
+    //DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
         
     // Number of bytes to be transfered in each service request of the channel
     DMA_TCD0_NBYTES_MLNO = 0x02;
     DMA_TCD1_NBYTES_MLNO = 0x02;
-    DMA_TCD2_NBYTES_MLNO = 0x02;
+    //DMA_TCD2_NBYTES_MLNO = 0x02;
         
     // Current major iteration count
     DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
     DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
     DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
     DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
-    DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
-    DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+   // DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    //DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
     
     // Adjustment value used to restore the source and destiny address to the initial value
     // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
@@ -94,13 +108,13 @@
     DMA_TCD1_DLASTSGA = -len*2;  // Destination address adjustment
     
     //Change source and destination
-    DMA_TCD2_SLAST = 0;      // Source address adjustment
-    DMA_TCD2_DLASTSGA = -len*2;  // Destination address adjustment
+    //DMA_TCD2_SLAST = -len*2;      // Source address adjustment
+    //DMA_TCD2_DLASTSGA = 0;  // Destination address adjustment
     
     // Setup control and status register
     DMA_TCD0_CSR = 0;
     DMA_TCD1_CSR = 0;
-    DMA_TCD2_CSR = 0;
+   // DMA_TCD2_CSR = 0;
     
     // enable interrupt call at end of major loop
     DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK | DMA_CSR_INTHALF_MASK;