DCS_TEAM / Mbed 2 deprecated Chemical_Sensor_DMA

Jared's DAC Code

Dependencies:   mbed

Dependents:   DCS_FINAL_CODE

Fork of Chemical_Sensor_DMA by Jared Baxter

Sample/dma.cpp@7:af255a90505e, 2015-12-19 (annotated)

Committer:
DeWayneDennis
Date:
Sat Dec 19 21:47:52 2015 +0000
Revision:
7:af255a90505e
Parent:
4:9fd291254686 
Final Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
baxterja 2:3771b3195c7b 1 /**
baxterja 2:3771b3195c7b 2 * Setup triggering for DMA2 and PortC
baxterja 2:3771b3195c7b 3 */
baxterja 2:3771b3195c7b 4 #include "dma.h"
baxterja 2:3771b3195c7b 5
baxterja 2:3771b3195c7b 6 DigitalOut toggle_dma0(LED_RED);
baxterja 2:3771b3195c7b 7 DigitalOut toggle_dma1(LED_BLUE);
baxterja 2:3771b3195c7b 8 DigitalOut toggle_dma2(LED_GREEN);
baxterja 2:3771b3195c7b 9 Serial debug3(USBTX,USBRX);
baxterja 2:3771b3195c7b 10
baxterja 2:3771b3195c7b 11 //#define TOTAL_SAMPLES 30000
baxterja 2:3771b3195c7b 12 //#define FILENAME_SIZE 26 // this matches what is defined in DistanceFirmware's main.cpp
baxterja 2:3771b3195c7b 13 int len = TOTAL_SAMPLES;
baxterja 2:3771b3195c7b 14 uint16_t sample_array0[TOTAL_SAMPLES];
baxterja 2:3771b3195c7b 15 uint16_t sample_array1[TOTAL_SAMPLES];
DeWayneDennis 7:af255a90505e 16 uint16_t out_val_pre[TOTAL_SAMPLES];//Change this to DAC Values
baxterja 2:3771b3195c7b 17 bool dma_done = false;
baxterja 2:3771b3195c7b 18 bool dma_half_done = false;
baxterja 2:3771b3195c7b 19
baxterja 4:9fd291254686 20 #define pre_compute_length 2000
baxterja 4:9fd291254686 21 #define DMA_PERIOD .00001
baxterja 4:9fd291254686 22 #define DMA_FREQUENCY 100000
DeWayneDennis 7:af255a90505e 23 #define CARRIERFREQUENCY 1000
baxterja 4:9fd291254686 24 #define twopi 3.14159265359 * 2
baxterja 2:3771b3195c7b 25
baxterja 2:3771b3195c7b 26 /* DMA0 and DMA1 are triggered by ADC0 and ADC1 (which are triggered
baxterja 2:3771b3195c7b 27 * by the PDB). However, DMA2 is triggered directly by the PDB. This
baxterja 2:3771b3195c7b 28 * is becuase DMA2 is reading FTM2, which cannot trigger the DMA. */
baxterja 2:3771b3195c7b 29 void dma_init()
baxterja 2:3771b3195c7b 30 {
DeWayneDennis 7:af255a90505e 31 for(int precompute_counter = 0; precompute_counter < TOTAL_SAMPLES; precompute_counter++){
DeWayneDennis 7:af255a90505e 32 out_val_pre[precompute_counter] = (int) (cos(twopi * CARRIERFREQUENCY * DMA_PERIOD * precompute_counter) * 150.0 + 2755.0);
DeWayneDennis 7:af255a90505e 33 }
baxterja 4:9fd291254686 34
baxterja 2:3771b3195c7b 35 toggle_dma0 = 1;
baxterja 2:3771b3195c7b 36 toggle_dma1 = 1;
baxterja 2:3771b3195c7b 37 toggle_dma2 = 1;
baxterja 2:3771b3195c7b 38 // Enable clock for DMAMUX and DMA
baxterja 4:9fd291254686 39 //SIM_SCGC2 |= SIM_SCGC2_DAC0_MASK;
baxterja 4:9fd291254686 40 //SIM_SCGC6 |= SIM_SCGC6_DAC0_MASK;
baxterja 4:9fd291254686 41
baxterja 4:9fd291254686 42
baxterja 2:3771b3195c7b 43 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
baxterja 2:3771b3195c7b 44 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
baxterja 2:3771b3195c7b 45 SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // make sure clock is enabled for FTM2
baxterja 4:9fd291254686 46
baxterja 4:9fd291254686 47
baxterja 4:9fd291254686 48
baxterja 2:3771b3195c7b 49 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
baxterja 2:3771b3195c7b 50 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
baxterja 2:3771b3195c7b 51 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
baxterja 2:3771b3195c7b 52 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // Set trigger source to PDB (Don't set DMA Trig Enable because that is for the PIT)
baxterja 2:3771b3195c7b 53 /* Source number Source module
baxterja 2:3771b3195c7b 54 40 ADC0
baxterja 2:3771b3195c7b 55 41 ADC1
baxterja 2:3771b3195c7b 56 48 PDB
baxterja 2:3771b3195c7b 57 */
baxterja 2:3771b3195c7b 58
baxterja 2:3771b3195c7b 59
baxterja 2:3771b3195c7b 60 // Enable request signal for channel 0
baxterja 2:3771b3195c7b 61 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
baxterja 2:3771b3195c7b 62
baxterja 2:3771b3195c7b 63 // select round-robin arbitration priority
baxterja 2:3771b3195c7b 64 DMA_CR |= DMA_CR_ERCA_MASK;
baxterja 2:3771b3195c7b 65
baxterja 2:3771b3195c7b 66 // Set memory address for source and destination for DMA0, DMA1, and DMA2
baxterja 2:3771b3195c7b 67 DMA_TCD0_SADDR = (uint32_t) &ADC0_RB;
baxterja 2:3771b3195c7b 68 DMA_TCD0_DADDR = (uint32_t) sample_array0;
baxterja 2:3771b3195c7b 69 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
baxterja 2:3771b3195c7b 70 DMA_TCD1_DADDR = (uint32_t) sample_array1;
DeWayneDennis 7:af255a90505e 71 DMA_TCD2_SADDR = (uint32_t) &out_val_pre[0];//&FTM2_CNT;
DeWayneDennis 7:af255a90505e 72 DMA_TCD2_DADDR = (uint32_t) &DAC0_DAT0L;
baxterja 2:3771b3195c7b 73
baxterja 2:3771b3195c7b 74 // Set an offset for source and destination address
baxterja 2:3771b3195c7b 75 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
baxterja 2:3771b3195c7b 76 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
baxterja 2:3771b3195c7b 77 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
baxterja 2:3771b3195c7b 78 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
baxterja 3:a85b742be262 79
baxterja 3:a85b742be262 80 //DAC DMA Chang soff to 2, and DOFF to 0
DeWayneDennis 7:af255a90505e 81 DMA_TCD2_SOFF = 0x02; // Source address offset of 2 bits per transaction
DeWayneDennis 7:af255a90505e 82 DMA_TCD2_DOFF = 0x00; // Destination address offset of 1 bit per transaction
baxterja 2:3771b3195c7b 83
baxterja 2:3771b3195c7b 84 // Set source and destination data transfer size
baxterja 2:3771b3195c7b 85 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 2:3771b3195c7b 86 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
DeWayneDennis 7:af255a90505e 87 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 2:3771b3195c7b 88
baxterja 2:3771b3195c7b 89 // Number of bytes to be transfered in each service request of the channel
baxterja 2:3771b3195c7b 90 DMA_TCD0_NBYTES_MLNO = 0x02;
baxterja 2:3771b3195c7b 91 DMA_TCD1_NBYTES_MLNO = 0x02;
DeWayneDennis 7:af255a90505e 92 DMA_TCD2_NBYTES_MLNO = 0x02;
baxterja 2:3771b3195c7b 93
baxterja 2:3771b3195c7b 94 // Current major iteration count
baxterja 2:3771b3195c7b 95 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
baxterja 2:3771b3195c7b 96 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
baxterja 2:3771b3195c7b 97 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
baxterja 2:3771b3195c7b 98 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
DeWayneDennis 7:af255a90505e 99 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
DeWayneDennis 7:af255a90505e 100 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
baxterja 2:3771b3195c7b 101
baxterja 2:3771b3195c7b 102 // Adjustment value used to restore the source and destiny address to the initial value
baxterja 2:3771b3195c7b 103 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
baxterja 2:3771b3195c7b 104
baxterja 2:3771b3195c7b 105 DMA_TCD0_SLAST = 0; // Source address adjustment
baxterja 2:3771b3195c7b 106 DMA_TCD0_DLASTSGA = -len*2; // Destination address adjustment
baxterja 2:3771b3195c7b 107 DMA_TCD1_SLAST = 0; // Source address adjustment
baxterja 2:3771b3195c7b 108 DMA_TCD1_DLASTSGA = -len*2; // Destination address adjustment
baxterja 3:a85b742be262 109
baxterja 3:a85b742be262 110 //Change source and destination
DeWayneDennis 7:af255a90505e 111 DMA_TCD2_SLAST = -len*2; // Source address adjustment
DeWayneDennis 7:af255a90505e 112 DMA_TCD2_DLASTSGA = 0; // Destination address adjustment
baxterja 2:3771b3195c7b 113
baxterja 2:3771b3195c7b 114 // Setup control and status register
baxterja 2:3771b3195c7b 115 DMA_TCD0_CSR = 0;
baxterja 2:3771b3195c7b 116 DMA_TCD1_CSR = 0;
baxterja 4:9fd291254686 117 // DMA_TCD2_CSR = 0;
baxterja 2:3771b3195c7b 118
baxterja 2:3771b3195c7b 119 // enable interrupt call at end of major loop
baxterja 2:3771b3195c7b 120 DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK | DMA_CSR_INTHALF_MASK;
baxterja 2:3771b3195c7b 121
baxterja 2:3771b3195c7b 122 // add interrupt handlers to interrupt vector table
baxterja 2:3771b3195c7b 123 NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA_IRQHandler);
baxterja 2:3771b3195c7b 124
baxterja 2:3771b3195c7b 125 //enable interrupts
baxterja 2:3771b3195c7b 126 NVIC_EnableIRQ(DMA0_IRQn);
baxterja 2:3771b3195c7b 127
baxterja 2:3771b3195c7b 128 // dma_init takes 4.09us to run.
baxterja 2:3771b3195c7b 129 }
baxterja 2:3771b3195c7b 130
baxterja 2:3771b3195c7b 131 void dma_reset() {
baxterja 2:3771b3195c7b 132 dma_done = false;
baxterja 2:3771b3195c7b 133 dma_half_done = false;
baxterja 2:3771b3195c7b 134
baxterja 2:3771b3195c7b 135 // clear all DMA interrupts
baxterja 2:3771b3195c7b 136 DMA_CINT = DMA_CINT_CAIR_MASK;
baxterja 2:3771b3195c7b 137
baxterja 2:3771b3195c7b 138 //enable interrupts
baxterja 2:3771b3195c7b 139 NVIC_EnableIRQ(DMA0_IRQn);
baxterja 2:3771b3195c7b 140 }
baxterja 2:3771b3195c7b 141
baxterja 2:3771b3195c7b 142 /* The only DMA interrupt is from DMA0. The interrupts from DMA1 and DMA2
baxterja 2:3771b3195c7b 143 * are turned off because they all trigger at the same time. Actually
baxterja 2:3771b3195c7b 144 * DMA2 triggers just before DMA0 and DMA1, but it's a negligible amount
baxterja 2:3771b3195c7b 145 * of time. By the time the PDB is turned off, the ADCs will have already
baxterja 2:3771b3195c7b 146 * been triggered. */
baxterja 2:3771b3195c7b 147 void DMA_IRQHandler() {
baxterja 2:3771b3195c7b 148
baxterja 2:3771b3195c7b 149 DMA_CINT |= DMA_CINT_CINT(0); // clear interrupt flag
baxterja 2:3771b3195c7b 150 //toggle_dma0 = 0;
baxterja 2:3771b3195c7b 151 //debug3.printf("DMA ");
baxterja 2:3771b3195c7b 152 if(!dma_half_done) {
baxterja 2:3771b3195c7b 153 dma_half_done = true;
baxterja 2:3771b3195c7b 154 //debug3.printf("half done\r\n");
baxterja 2:3771b3195c7b 155 return;
baxterja 2:3771b3195c7b 156 }
baxterja 2:3771b3195c7b 157 //PDB0_SC &= ~PDB_SC_PDBEN_MASK; // disable PDB
baxterja 2:3771b3195c7b 158 //NVIC_DisableIRQ(DMA0_IRQn); // disable interrupt
baxterja 2:3771b3195c7b 159 dma_done = true;
baxterja 2:3771b3195c7b 160 //debug3.printf("done\r\n");
baxterja 2:3771b3195c7b 161 }
baxterja 2:3771b3195c7b 162
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baxterja 2:3771b3195c7b 174
baxterja 2:3771b3195c7b 175
baxterja 2:3771b3195c7b 176 /* * * * * * * * * * * * * * For Debugging Purposes * * * * * * * * * * * * * * * * * * * * */
baxterja 2:3771b3195c7b 177
baxterja 2:3771b3195c7b 178
baxterja 2:3771b3195c7b 179 void dma_print_registers() {
baxterja 2:3771b3195c7b 180
baxterja 2:3771b3195c7b 181 debug3.printf("SADDR0: 0x%08x\r\n",DMA_TCD0_SADDR);
baxterja 2:3771b3195c7b 182 debug3.printf("DADDR0: 0x%08x\r\n",DMA_TCD0_DADDR);
baxterja 2:3771b3195c7b 183 debug3.printf("SADDR1: 0x%08x\r\n",DMA_TCD1_SADDR);
baxterja 2:3771b3195c7b 184 debug3.printf("DADDR1: 0x%08x\r\n",DMA_TCD1_DADDR);
baxterja 2:3771b3195c7b 185 debug3.printf("SADDR2: 0x%08x\r\n",DMA_TCD2_SADDR);
baxterja 2:3771b3195c7b 186 debug3.printf("DADDR2: 0x%08x\r\n",DMA_TCD2_DADDR);
baxterja 2:3771b3195c7b 187
baxterja 2:3771b3195c7b 188 debug3.printf("CITER0: 0x%08x\r\n",DMA_TCD0_CITER_ELINKNO);
baxterja 2:3771b3195c7b 189 debug3.printf("BITER0: 0x%08x\r\n",DMA_TCD0_BITER_ELINKNO);
baxterja 2:3771b3195c7b 190 debug3.printf("CITER1: 0x%08x\r\n",DMA_TCD1_CITER_ELINKNO);
baxterja 2:3771b3195c7b 191 debug3.printf("BITER1: 0x%08x\r\n",DMA_TCD1_BITER_ELINKNO);
baxterja 2:3771b3195c7b 192 debug3.printf("CITER2: 0x%08x\r\n",DMA_TCD2_CITER_ELINKNO);
baxterja 2:3771b3195c7b 193 debug3.printf("BITER2: 0x%08x\r\n",DMA_TCD2_BITER_ELINKNO);
baxterja 2:3771b3195c7b 194
baxterja 2:3771b3195c7b 195
baxterja 2:3771b3195c7b 196 debug3.printf("DMA_CR: %08x\r\n", DMA_CR);
baxterja 2:3771b3195c7b 197 debug3.printf("DMA_ES: %08x\r\n", DMA_ES);
baxterja 2:3771b3195c7b 198 debug3.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
baxterja 2:3771b3195c7b 199 debug3.printf("DMA_EEI: %08x\r\n", DMA_EEI);
baxterja 2:3771b3195c7b 200 debug3.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
baxterja 2:3771b3195c7b 201 debug3.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
baxterja 2:3771b3195c7b 202 debug3.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
baxterja 2:3771b3195c7b 203 debug3.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
baxterja 2:3771b3195c7b 204 debug3.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
baxterja 2:3771b3195c7b 205 debug3.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
baxterja 2:3771b3195c7b 206 debug3.printf("DMA_CERR: %02x\r\n", DMA_CERR);
baxterja 2:3771b3195c7b 207 debug3.printf("DMA_CINT: %02x\r\n", DMA_CINT);
baxterja 2:3771b3195c7b 208 debug3.printf("DMA_INT: %08x\r\n", DMA_INT);
baxterja 2:3771b3195c7b 209 debug3.printf("DMA_ERR: %08x\r\n", DMA_ERR);
baxterja 2:3771b3195c7b 210 debug3.printf("DMA_HRS: %08x\r\n", DMA_HRS);
baxterja 2:3771b3195c7b 211
baxterja 2:3771b3195c7b 212 }