CaryCoders / SX1276Lib

local copy of sx1276 library

Dependents:   SX1276_GPS demo_SX1276_standalone

Fork of SX1276Lib by Gregory Cristian

sx1276/sx1276-hal.cpp@17:20ce6dab2237, 2015-09-03 (annotated)

Committer:
ftagius
Date:
Thu Sep 03 14:33:00 2015 +0000
Revision:
17:20ce6dab2237
Parent:
16:29f09ac61412 
add debug messages;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
ftagius 16:29f09ac61412 16 #include "main.h"
GregCr 0:e6ceb13d2d05 17
GregCr 0:e6ceb13d2d05 18 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] =
GregCr 0:e6ceb13d2d05 19 {
GregCr 0:e6ceb13d2d05 20 { MODEM_FSK , REG_LNA , 0x23 },
GregCr 0:e6ceb13d2d05 21 { MODEM_FSK , REG_RXCONFIG , 0x1E },
GregCr 0:e6ceb13d2d05 22 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
GregCr 0:e6ceb13d2d05 23 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
GregCr 0:e6ceb13d2d05 24 { MODEM_FSK , REG_OSC , 0x07 },
GregCr 0:e6ceb13d2d05 25 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
GregCr 0:e6ceb13d2d05 26 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
GregCr 0:e6ceb13d2d05 27 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
GregCr 0:e6ceb13d2d05 28 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
GregCr 5:11ec8a6ba4f0 29 { MODEM_FSK , REG_PACKETCONFIG1 , 0x98 },
GregCr 0:e6ceb13d2d05 30 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
GregCr 0:e6ceb13d2d05 31 { MODEM_FSK , REG_IMAGECAL , 0x02 },
GregCr 0:e6ceb13d2d05 32 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
GregCr 0:e6ceb13d2d05 33 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
GregCr 0:e6ceb13d2d05 34 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
ftagius 16:29f09ac61412 35 { MODEM_LORA, REG_SEQCONFIG1 , 0x02 }, // per errata to optimitze sensitivity
ftagius 16:29f09ac61412 36 };
GregCr 0:e6ceb13d2d05 37
GregCr 7:2b555111463f 38 SX1276MB1xAS::SX1276MB1xAS( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
GregCr 12:aa5b3bf7fdf4 39 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool ChannelActivityDetected ),
GregCr 0:e6ceb13d2d05 40 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 41 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 42 PinName antSwitch )
GregCr 7:2b555111463f 43 : SX1276( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5),
GregCr 0:e6ceb13d2d05 44 antSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 45 #if( defined ( TARGET_NUCLEO_L152RE ) )
GregCr 12:aa5b3bf7fdf4 46 fake( D8 )
GregCr 12:aa5b3bf7fdf4 47 #else
GregCr 0:e6ceb13d2d05 48 fake( A3 )
GregCr 0:e6ceb13d2d05 49 #endif
GregCr 0:e6ceb13d2d05 50 {
GregCr 0:e6ceb13d2d05 51 Reset( );
GregCr 0:e6ceb13d2d05 52
GregCr 0:e6ceb13d2d05 53 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 54
GregCr 0:e6ceb13d2d05 55 IoInit( );
GregCr 0:e6ceb13d2d05 56
GregCr 0:e6ceb13d2d05 57 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 58
GregCr 0:e6ceb13d2d05 59 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 60
GregCr 0:e6ceb13d2d05 61 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 62
GregCr 0:e6ceb13d2d05 63 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 64
GregCr 0:e6ceb13d2d05 65 this->settings.State = IDLE ;
GregCr 0:e6ceb13d2d05 66 }
GregCr 0:e6ceb13d2d05 67
GregCr 7:2b555111463f 68 SX1276MB1xAS::SX1276MB1xAS( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
GregCr 12:aa5b3bf7fdf4 69 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool ChannelActivityDetected ) )
GregCr 12:aa5b3bf7fdf4 70 #if defined ( TARGET_NUCLEO_L152RE )
GregCr 7:2b555111463f 71 : SX1276( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 72 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 73 fake( D8 )
GregCr 0:e6ceb13d2d05 74 #else
GregCr 12:aa5b3bf7fdf4 75 : SX1276( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
GregCr 12:aa5b3bf7fdf4 76 antSwitch( A4 ),
GregCr 12:aa5b3bf7fdf4 77 fake( A3 )
GregCr 0:e6ceb13d2d05 78 #endif
GregCr 0:e6ceb13d2d05 79 {
GregCr 0:e6ceb13d2d05 80 Reset( );
GregCr 0:e6ceb13d2d05 81
GregCr 5:11ec8a6ba4f0 82 boardConnected = UNKNOWN;
GregCr 5:11ec8a6ba4f0 83
GregCr 1:f979673946c0 84 DetectBoardType( );
GregCr 1:f979673946c0 85
GregCr 0:e6ceb13d2d05 86 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 IoInit( );
GregCr 0:e6ceb13d2d05 89
GregCr 0:e6ceb13d2d05 90 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 91 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 92
GregCr 0:e6ceb13d2d05 93 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 94
GregCr 0:e6ceb13d2d05 95 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 this->settings.State = IDLE ;
GregCr 0:e6ceb13d2d05 98 }
GregCr 0:e6ceb13d2d05 99
GregCr 0:e6ceb13d2d05 100 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 101 // Board relative functions
GregCr 0:e6ceb13d2d05 102 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 103 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 104 {
GregCr 5:11ec8a6ba4f0 105 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 106 {
GregCr 5:11ec8a6ba4f0 107 antSwitch.input( );
GregCr 5:11ec8a6ba4f0 108 wait_ms( 1 );
GregCr 5:11ec8a6ba4f0 109 if( antSwitch == 1 )
GregCr 5:11ec8a6ba4f0 110 {
GregCr 5:11ec8a6ba4f0 111 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 112 }
GregCr 5:11ec8a6ba4f0 113 else
GregCr 5:11ec8a6ba4f0 114 {
GregCr 5:11ec8a6ba4f0 115 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 116 }
GregCr 5:11ec8a6ba4f0 117 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 118 wait_ms( 1 );
GregCr 1:f979673946c0 119 }
GregCr 2:5eb3066446dd 120 return ( boardConnected );
GregCr 1:f979673946c0 121 }
GregCr 0:e6ceb13d2d05 122
GregCr 0:e6ceb13d2d05 123 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 124 {
GregCr 0:e6ceb13d2d05 125 AntSwInit( );
GregCr 0:e6ceb13d2d05 126 SpiInit( );
GregCr 0:e6ceb13d2d05 127 }
GregCr 0:e6ceb13d2d05 128
GregCr 0:e6ceb13d2d05 129 void SX1276MB1xAS::RadioRegistersInit( ){
GregCr 0:e6ceb13d2d05 130 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 131 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 132 {
GregCr 0:e6ceb13d2d05 133 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 134 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 135 }
ftagius 16:29f09ac61412 136 if( Frequency > RF_MID_BAND_THRESH )
ftagius 16:29f09ac61412 137 {
ftagius 16:29f09ac61412 138 SetModem(MODEM_LORA);
ftagius 16:29f09ac61412 139 Write(REG_TIMER2COEF, 0x64 ); // per errata to optimize sensitivity
ftagius 16:29f09ac61412 140
ftagius 16:29f09ac61412 141 }
ftagius 16:29f09ac61412 142 else
ftagius 16:29f09ac61412 143 {
ftagius 16:29f09ac61412 144 SetModem(MODEM_LORA);
ftagius 16:29f09ac61412 145 Write(REG_TIMER2COEF, 0x7f ); // per errata to optimize sensitivity
ftagius 16:29f09ac61412 146 }
GregCr 0:e6ceb13d2d05 147 }
GregCr 0:e6ceb13d2d05 148
GregCr 0:e6ceb13d2d05 149 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 150 {
GregCr 0:e6ceb13d2d05 151 nss = 1;
GregCr 0:e6ceb13d2d05 152 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 153 uint32_t frequencyToSet = 8000000;
GregCr 0:e6ceb13d2d05 154 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 155 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 156 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 157 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 158 #else
GregCr 0:e6ceb13d2d05 159 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 160 #endif
GregCr 0:e6ceb13d2d05 161 wait(0.1);
GregCr 0:e6ceb13d2d05 162 }
GregCr 0:e6ceb13d2d05 163
GregCr 0:e6ceb13d2d05 164 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 165 {
GregCr 0:e6ceb13d2d05 166 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 167 dio0.mode(PullDown);
GregCr 0:e6ceb13d2d05 168 dio1.mode(PullDown);
GregCr 0:e6ceb13d2d05 169 dio2.mode(PullDown);
GregCr 0:e6ceb13d2d05 170 dio3.mode(PullDown);
GregCr 0:e6ceb13d2d05 171 dio4.mode(PullDown);
GregCr 0:e6ceb13d2d05 172 #endif
GregCr 0:e6ceb13d2d05 173 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
GregCr 0:e6ceb13d2d05 174 dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
GregCr 0:e6ceb13d2d05 175 dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
GregCr 0:e6ceb13d2d05 176 dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
GregCr 0:e6ceb13d2d05 177 dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
GregCr 0:e6ceb13d2d05 178 }
GregCr 0:e6ceb13d2d05 179
GregCr 0:e6ceb13d2d05 180 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 181 {
GregCr 0:e6ceb13d2d05 182 //nothing
GregCr 0:e6ceb13d2d05 183 }
GregCr 0:e6ceb13d2d05 184
GregCr 0:e6ceb13d2d05 185 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 186 {
ftagius 16:29f09ac61412 187
GregCr 0:e6ceb13d2d05 188 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 189 {
GregCr 3:ca84be1f3fac 190 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 191 {
ftagius 16:29f09ac61412 192
GregCr 1:f979673946c0 193 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 194 }
GregCr 1:f979673946c0 195 else
GregCr 1:f979673946c0 196 {
ftagius 16:29f09ac61412 197
GregCr 1:f979673946c0 198 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 199 }
GregCr 0:e6ceb13d2d05 200 }
GregCr 0:e6ceb13d2d05 201 else
ftagius 16:29f09ac61412 202 {
GregCr 0:e6ceb13d2d05 203 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 204 }
GregCr 0:e6ceb13d2d05 205 }
GregCr 0:e6ceb13d2d05 206
GregCr 0:e6ceb13d2d05 207 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 208 {
GregCr 0:e6ceb13d2d05 209 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 210 {
GregCr 0:e6ceb13d2d05 211 isRadioActive = status;
GregCr 0:e6ceb13d2d05 212
GregCr 0:e6ceb13d2d05 213 if( status == false )
GregCr 0:e6ceb13d2d05 214 {
GregCr 0:e6ceb13d2d05 215 AntSwInit( );
GregCr 0:e6ceb13d2d05 216 }
GregCr 0:e6ceb13d2d05 217 else
GregCr 0:e6ceb13d2d05 218 {
GregCr 0:e6ceb13d2d05 219 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 220 }
GregCr 0:e6ceb13d2d05 221 }
GregCr 0:e6ceb13d2d05 222 }
GregCr 0:e6ceb13d2d05 223
GregCr 0:e6ceb13d2d05 224 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 antSwitch = 0;
GregCr 0:e6ceb13d2d05 227 }
GregCr 0:e6ceb13d2d05 228
GregCr 0:e6ceb13d2d05 229 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 antSwitch = 0;
GregCr 0:e6ceb13d2d05 232 }
GregCr 0:e6ceb13d2d05 233
GregCr 0:e6ceb13d2d05 234 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 235 {
GregCr 0:e6ceb13d2d05 236 if( this->rxTx == rxTx )
GregCr 0:e6ceb13d2d05 237 {
GregCr 0:e6ceb13d2d05 238 //no need to go further
GregCr 0:e6ceb13d2d05 239 return;
GregCr 0:e6ceb13d2d05 240 }
GregCr 0:e6ceb13d2d05 241
GregCr 0:e6ceb13d2d05 242 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 243
GregCr 0:e6ceb13d2d05 244 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 245 {
GregCr 0:e6ceb13d2d05 246 antSwitch = 1;
GregCr 0:e6ceb13d2d05 247 }
GregCr 0:e6ceb13d2d05 248 else
GregCr 0:e6ceb13d2d05 249 {
GregCr 0:e6ceb13d2d05 250 antSwitch = 0;
GregCr 0:e6ceb13d2d05 251 }
GregCr 0:e6ceb13d2d05 252 }
GregCr 0:e6ceb13d2d05 253
GregCr 0:e6ceb13d2d05 254 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 255 {
GregCr 0:e6ceb13d2d05 256 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 257 return true;
GregCr 0:e6ceb13d2d05 258 }
GregCr 0:e6ceb13d2d05 259
GregCr 0:e6ceb13d2d05 260
GregCr 0:e6ceb13d2d05 261 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 262 {
GregCr 4:f0ce52e94d3f 263 reset.output();
GregCr 0:e6ceb13d2d05 264 reset = 0;
GregCr 0:e6ceb13d2d05 265 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 266 reset.input();
GregCr 0:e6ceb13d2d05 267 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 268 }
GregCr 0:e6ceb13d2d05 269
GregCr 0:e6ceb13d2d05 270 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 271 {
GregCr 0:e6ceb13d2d05 272 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 273 }
GregCr 0:e6ceb13d2d05 274
GregCr 0:e6ceb13d2d05 275 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 276 {
GregCr 0:e6ceb13d2d05 277 uint8_t data;
GregCr 0:e6ceb13d2d05 278 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 279 return data;
GregCr 0:e6ceb13d2d05 280 }
GregCr 0:e6ceb13d2d05 281
GregCr 0:e6ceb13d2d05 282 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 283 {
GregCr 0:e6ceb13d2d05 284 uint8_t i;
GregCr 0:e6ceb13d2d05 285
GregCr 0:e6ceb13d2d05 286 nss = 0;
GregCr 0:e6ceb13d2d05 287 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 288 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 nss = 1;
GregCr 0:e6ceb13d2d05 293 }
GregCr 0:e6ceb13d2d05 294
GregCr 0:e6ceb13d2d05 295 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 296 {
GregCr 0:e6ceb13d2d05 297 uint8_t i;
GregCr 0:e6ceb13d2d05 298
GregCr 0:e6ceb13d2d05 299 nss = 0;
GregCr 0:e6ceb13d2d05 300 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 301 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 302 {
GregCr 0:e6ceb13d2d05 303 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 304 }
GregCr 0:e6ceb13d2d05 305 nss = 1;
GregCr 0:e6ceb13d2d05 306 }
GregCr 0:e6ceb13d2d05 307
GregCr 0:e6ceb13d2d05 308 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 309 {
GregCr 0:e6ceb13d2d05 310 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 311 }
GregCr 0:e6ceb13d2d05 312
GregCr 0:e6ceb13d2d05 313 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 314 {
GregCr 0:e6ceb13d2d05 315 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 316 }