CRAC Team / command_AX12_petit_robot_V4tempo

code ax12 petit robot 12/05/2017

Fork of command_AX12_petit_robot_V3 by CRAC Team

mbed/LPC1768/core_cm3.h@7:ad4a19e26b84, 2017-05-12 (annotated)

Committer:
ClementBreteau
Date:
Fri May 12 14:35:09 2017 +0000
Revision:
7:ad4a19e26b84
Parent:
2:99b1cb0d9f5e 
position ax12

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UserRevisionLine numberNew contents of line
SquirrelGod 2:99b1cb0d9f5e 1 /**************************************************************************//**
SquirrelGod 2:99b1cb0d9f5e 2 * @file core_cm3.h
SquirrelGod 2:99b1cb0d9f5e 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
SquirrelGod 2:99b1cb0d9f5e 4 * @version V3.01
SquirrelGod 2:99b1cb0d9f5e 5 * @date 06. March 2012
SquirrelGod 2:99b1cb0d9f5e 6 *
SquirrelGod 2:99b1cb0d9f5e 7 * @note
SquirrelGod 2:99b1cb0d9f5e 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
SquirrelGod 2:99b1cb0d9f5e 9 *
SquirrelGod 2:99b1cb0d9f5e 10 * @par
SquirrelGod 2:99b1cb0d9f5e 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
SquirrelGod 2:99b1cb0d9f5e 12 * processor based microcontrollers. This file can be freely distributed
SquirrelGod 2:99b1cb0d9f5e 13 * within development tools that are supporting such ARM based processors.
SquirrelGod 2:99b1cb0d9f5e 14 *
SquirrelGod 2:99b1cb0d9f5e 15 * @par
SquirrelGod 2:99b1cb0d9f5e 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
SquirrelGod 2:99b1cb0d9f5e 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
SquirrelGod 2:99b1cb0d9f5e 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
SquirrelGod 2:99b1cb0d9f5e 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
SquirrelGod 2:99b1cb0d9f5e 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
SquirrelGod 2:99b1cb0d9f5e 21 *
SquirrelGod 2:99b1cb0d9f5e 22 ******************************************************************************/
SquirrelGod 2:99b1cb0d9f5e 23 #if defined ( __ICCARM__ )
SquirrelGod 2:99b1cb0d9f5e 24 #pragma system_include /* treat file as system include file for MISRA check */
SquirrelGod 2:99b1cb0d9f5e 25 #endif
SquirrelGod 2:99b1cb0d9f5e 26
SquirrelGod 2:99b1cb0d9f5e 27 #ifdef __cplusplus
SquirrelGod 2:99b1cb0d9f5e 28 extern "C" {
SquirrelGod 2:99b1cb0d9f5e 29 #endif
SquirrelGod 2:99b1cb0d9f5e 30
SquirrelGod 2:99b1cb0d9f5e 31 #ifndef __CORE_CM3_H_GENERIC
SquirrelGod 2:99b1cb0d9f5e 32 #define __CORE_CM3_H_GENERIC
SquirrelGod 2:99b1cb0d9f5e 33
SquirrelGod 2:99b1cb0d9f5e 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
SquirrelGod 2:99b1cb0d9f5e 35 CMSIS violates the following MISRA-C:2004 rules:
SquirrelGod 2:99b1cb0d9f5e 36
SquirrelGod 2:99b1cb0d9f5e 37 \li Required Rule 8.5, object/function definition in header file.<br>
SquirrelGod 2:99b1cb0d9f5e 38 Function definitions in header files are used to allow 'inlining'.
SquirrelGod 2:99b1cb0d9f5e 39
SquirrelGod 2:99b1cb0d9f5e 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
SquirrelGod 2:99b1cb0d9f5e 41 Unions are used for effective representation of core registers.
SquirrelGod 2:99b1cb0d9f5e 42
SquirrelGod 2:99b1cb0d9f5e 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
SquirrelGod 2:99b1cb0d9f5e 44 Function-like macros are used to allow more efficient code.
SquirrelGod 2:99b1cb0d9f5e 45 */
SquirrelGod 2:99b1cb0d9f5e 46
SquirrelGod 2:99b1cb0d9f5e 47
SquirrelGod 2:99b1cb0d9f5e 48 /*******************************************************************************
SquirrelGod 2:99b1cb0d9f5e 49 * CMSIS definitions
SquirrelGod 2:99b1cb0d9f5e 50 ******************************************************************************/
SquirrelGod 2:99b1cb0d9f5e 51 /** \ingroup Cortex_M3
SquirrelGod 2:99b1cb0d9f5e 52 @{
SquirrelGod 2:99b1cb0d9f5e 53 */
SquirrelGod 2:99b1cb0d9f5e 54
SquirrelGod 2:99b1cb0d9f5e 55 /* CMSIS CM3 definitions */
SquirrelGod 2:99b1cb0d9f5e 56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
SquirrelGod 2:99b1cb0d9f5e 57 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
SquirrelGod 2:99b1cb0d9f5e 58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
SquirrelGod 2:99b1cb0d9f5e 59 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
SquirrelGod 2:99b1cb0d9f5e 60
SquirrelGod 2:99b1cb0d9f5e 61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
SquirrelGod 2:99b1cb0d9f5e 62
SquirrelGod 2:99b1cb0d9f5e 63
SquirrelGod 2:99b1cb0d9f5e 64 #if defined ( __CC_ARM )
SquirrelGod 2:99b1cb0d9f5e 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
SquirrelGod 2:99b1cb0d9f5e 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
SquirrelGod 2:99b1cb0d9f5e 67 #define __STATIC_INLINE static __inline
SquirrelGod 2:99b1cb0d9f5e 68
SquirrelGod 2:99b1cb0d9f5e 69 #elif defined ( __ICCARM__ )
SquirrelGod 2:99b1cb0d9f5e 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
SquirrelGod 2:99b1cb0d9f5e 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
SquirrelGod 2:99b1cb0d9f5e 72 #define __STATIC_INLINE static inline
SquirrelGod 2:99b1cb0d9f5e 73
SquirrelGod 2:99b1cb0d9f5e 74 #elif defined ( __TMS470__ )
SquirrelGod 2:99b1cb0d9f5e 75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
SquirrelGod 2:99b1cb0d9f5e 76 #define __STATIC_INLINE static inline
SquirrelGod 2:99b1cb0d9f5e 77
SquirrelGod 2:99b1cb0d9f5e 78 #elif defined ( __GNUC__ )
SquirrelGod 2:99b1cb0d9f5e 79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
SquirrelGod 2:99b1cb0d9f5e 80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
SquirrelGod 2:99b1cb0d9f5e 81 #define __STATIC_INLINE static inline
SquirrelGod 2:99b1cb0d9f5e 82
SquirrelGod 2:99b1cb0d9f5e 83 #elif defined ( __TASKING__ )
SquirrelGod 2:99b1cb0d9f5e 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
SquirrelGod 2:99b1cb0d9f5e 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
SquirrelGod 2:99b1cb0d9f5e 86 #define __STATIC_INLINE static inline
SquirrelGod 2:99b1cb0d9f5e 87
SquirrelGod 2:99b1cb0d9f5e 88 #endif
SquirrelGod 2:99b1cb0d9f5e 89
SquirrelGod 2:99b1cb0d9f5e 90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
SquirrelGod 2:99b1cb0d9f5e 91 */
SquirrelGod 2:99b1cb0d9f5e 92 #define __FPU_USED 0
SquirrelGod 2:99b1cb0d9f5e 93
SquirrelGod 2:99b1cb0d9f5e 94 #if defined ( __CC_ARM )
SquirrelGod 2:99b1cb0d9f5e 95 #if defined __TARGET_FPU_VFP
SquirrelGod 2:99b1cb0d9f5e 96 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
SquirrelGod 2:99b1cb0d9f5e 97 #endif
SquirrelGod 2:99b1cb0d9f5e 98
SquirrelGod 2:99b1cb0d9f5e 99 #elif defined ( __ICCARM__ )
SquirrelGod 2:99b1cb0d9f5e 100 #if defined __ARMVFP__
SquirrelGod 2:99b1cb0d9f5e 101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
SquirrelGod 2:99b1cb0d9f5e 102 #endif
SquirrelGod 2:99b1cb0d9f5e 103
SquirrelGod 2:99b1cb0d9f5e 104 #elif defined ( __TMS470__ )
SquirrelGod 2:99b1cb0d9f5e 105 #if defined __TI__VFP_SUPPORT____
SquirrelGod 2:99b1cb0d9f5e 106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
SquirrelGod 2:99b1cb0d9f5e 107 #endif
SquirrelGod 2:99b1cb0d9f5e 108
SquirrelGod 2:99b1cb0d9f5e 109 #elif defined ( __GNUC__ )
SquirrelGod 2:99b1cb0d9f5e 110 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
SquirrelGod 2:99b1cb0d9f5e 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
SquirrelGod 2:99b1cb0d9f5e 112 #endif
SquirrelGod 2:99b1cb0d9f5e 113
SquirrelGod 2:99b1cb0d9f5e 114 #elif defined ( __TASKING__ )
SquirrelGod 2:99b1cb0d9f5e 115 /* add preprocessor checks */
SquirrelGod 2:99b1cb0d9f5e 116 #endif
SquirrelGod 2:99b1cb0d9f5e 117
SquirrelGod 2:99b1cb0d9f5e 118 #include <stdint.h> /* standard types definitions */
SquirrelGod 2:99b1cb0d9f5e 119 #include <core_cmInstr.h> /* Core Instruction Access */
SquirrelGod 2:99b1cb0d9f5e 120 #include <core_cmFunc.h> /* Core Function Access */
SquirrelGod 2:99b1cb0d9f5e 121
SquirrelGod 2:99b1cb0d9f5e 122 #endif /* __CORE_CM3_H_GENERIC */
SquirrelGod 2:99b1cb0d9f5e 123
SquirrelGod 2:99b1cb0d9f5e 124 #ifndef __CMSIS_GENERIC
SquirrelGod 2:99b1cb0d9f5e 125
SquirrelGod 2:99b1cb0d9f5e 126 #ifndef __CORE_CM3_H_DEPENDANT
SquirrelGod 2:99b1cb0d9f5e 127 #define __CORE_CM3_H_DEPENDANT
SquirrelGod 2:99b1cb0d9f5e 128
SquirrelGod 2:99b1cb0d9f5e 129 /* check device defines and use defaults */
SquirrelGod 2:99b1cb0d9f5e 130 #if defined __CHECK_DEVICE_DEFINES
SquirrelGod 2:99b1cb0d9f5e 131 #ifndef __CM3_REV
SquirrelGod 2:99b1cb0d9f5e 132 #define __CM3_REV 0x0200
SquirrelGod 2:99b1cb0d9f5e 133 #warning "__CM3_REV not defined in device header file; using default!"
SquirrelGod 2:99b1cb0d9f5e 134 #endif
SquirrelGod 2:99b1cb0d9f5e 135
SquirrelGod 2:99b1cb0d9f5e 136 #ifndef __MPU_PRESENT
SquirrelGod 2:99b1cb0d9f5e 137 #define __MPU_PRESENT 0
SquirrelGod 2:99b1cb0d9f5e 138 #warning "__MPU_PRESENT not defined in device header file; using default!"
SquirrelGod 2:99b1cb0d9f5e 139 #endif
SquirrelGod 2:99b1cb0d9f5e 140
SquirrelGod 2:99b1cb0d9f5e 141 #ifndef __NVIC_PRIO_BITS
SquirrelGod 2:99b1cb0d9f5e 142 #define __NVIC_PRIO_BITS 4
SquirrelGod 2:99b1cb0d9f5e 143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
SquirrelGod 2:99b1cb0d9f5e 144 #endif
SquirrelGod 2:99b1cb0d9f5e 145
SquirrelGod 2:99b1cb0d9f5e 146 #ifndef __Vendor_SysTickConfig
SquirrelGod 2:99b1cb0d9f5e 147 #define __Vendor_SysTickConfig 0
SquirrelGod 2:99b1cb0d9f5e 148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
SquirrelGod 2:99b1cb0d9f5e 149 #endif
SquirrelGod 2:99b1cb0d9f5e 150 #endif
SquirrelGod 2:99b1cb0d9f5e 151
SquirrelGod 2:99b1cb0d9f5e 152 /* IO definitions (access restrictions to peripheral registers) */
SquirrelGod 2:99b1cb0d9f5e 153 /**
SquirrelGod 2:99b1cb0d9f5e 154 \defgroup CMSIS_glob_defs CMSIS Global Defines
SquirrelGod 2:99b1cb0d9f5e 155
SquirrelGod 2:99b1cb0d9f5e 156 <strong>IO Type Qualifiers</strong> are used
SquirrelGod 2:99b1cb0d9f5e 157 \li to specify the access to peripheral variables.
SquirrelGod 2:99b1cb0d9f5e 158 \li for automatic generation of peripheral register debug information.
SquirrelGod 2:99b1cb0d9f5e 159 */
SquirrelGod 2:99b1cb0d9f5e 160 #ifdef __cplusplus
SquirrelGod 2:99b1cb0d9f5e 161 #define __I volatile /*!< Defines 'read only' permissions */
SquirrelGod 2:99b1cb0d9f5e 162 #else
SquirrelGod 2:99b1cb0d9f5e 163 #define __I volatile const /*!< Defines 'read only' permissions */
SquirrelGod 2:99b1cb0d9f5e 164 #endif
SquirrelGod 2:99b1cb0d9f5e 165 #define __O volatile /*!< Defines 'write only' permissions */
SquirrelGod 2:99b1cb0d9f5e 166 #define __IO volatile /*!< Defines 'read / write' permissions */
SquirrelGod 2:99b1cb0d9f5e 167
SquirrelGod 2:99b1cb0d9f5e 168 /*@} end of group Cortex_M3 */
SquirrelGod 2:99b1cb0d9f5e 169
SquirrelGod 2:99b1cb0d9f5e 170
SquirrelGod 2:99b1cb0d9f5e 171
SquirrelGod 2:99b1cb0d9f5e 172 /*******************************************************************************
SquirrelGod 2:99b1cb0d9f5e 173 * Register Abstraction
SquirrelGod 2:99b1cb0d9f5e 174 Core Register contain:
SquirrelGod 2:99b1cb0d9f5e 175 - Core Register
SquirrelGod 2:99b1cb0d9f5e 176 - Core NVIC Register
SquirrelGod 2:99b1cb0d9f5e 177 - Core SCB Register
SquirrelGod 2:99b1cb0d9f5e 178 - Core SysTick Register
SquirrelGod 2:99b1cb0d9f5e 179 - Core Debug Register
SquirrelGod 2:99b1cb0d9f5e 180 - Core MPU Register
SquirrelGod 2:99b1cb0d9f5e 181 ******************************************************************************/
SquirrelGod 2:99b1cb0d9f5e 182 /** \defgroup CMSIS_core_register Defines and Type Definitions
SquirrelGod 2:99b1cb0d9f5e 183 \brief Type definitions and defines for Cortex-M processor based devices.
SquirrelGod 2:99b1cb0d9f5e 184 */
SquirrelGod 2:99b1cb0d9f5e 185
SquirrelGod 2:99b1cb0d9f5e 186 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 187 \defgroup CMSIS_CORE Status and Control Registers
SquirrelGod 2:99b1cb0d9f5e 188 \brief Core Register type definitions.
SquirrelGod 2:99b1cb0d9f5e 189 @{
SquirrelGod 2:99b1cb0d9f5e 190 */
SquirrelGod 2:99b1cb0d9f5e 191
SquirrelGod 2:99b1cb0d9f5e 192 /** \brief Union type to access the Application Program Status Register (APSR).
SquirrelGod 2:99b1cb0d9f5e 193 */
SquirrelGod 2:99b1cb0d9f5e 194 typedef union
SquirrelGod 2:99b1cb0d9f5e 195 {
SquirrelGod 2:99b1cb0d9f5e 196 struct
SquirrelGod 2:99b1cb0d9f5e 197 {
SquirrelGod 2:99b1cb0d9f5e 198 #if (__CORTEX_M != 0x04)
SquirrelGod 2:99b1cb0d9f5e 199 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
SquirrelGod 2:99b1cb0d9f5e 200 #else
SquirrelGod 2:99b1cb0d9f5e 201 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
SquirrelGod 2:99b1cb0d9f5e 202 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
SquirrelGod 2:99b1cb0d9f5e 203 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
SquirrelGod 2:99b1cb0d9f5e 204 #endif
SquirrelGod 2:99b1cb0d9f5e 205 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
SquirrelGod 2:99b1cb0d9f5e 206 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
SquirrelGod 2:99b1cb0d9f5e 207 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
SquirrelGod 2:99b1cb0d9f5e 208 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
SquirrelGod 2:99b1cb0d9f5e 209 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
SquirrelGod 2:99b1cb0d9f5e 210 } b; /*!< Structure used for bit access */
SquirrelGod 2:99b1cb0d9f5e 211 uint32_t w; /*!< Type used for word access */
SquirrelGod 2:99b1cb0d9f5e 212 } APSR_Type;
SquirrelGod 2:99b1cb0d9f5e 213
SquirrelGod 2:99b1cb0d9f5e 214
SquirrelGod 2:99b1cb0d9f5e 215 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
SquirrelGod 2:99b1cb0d9f5e 216 */
SquirrelGod 2:99b1cb0d9f5e 217 typedef union
SquirrelGod 2:99b1cb0d9f5e 218 {
SquirrelGod 2:99b1cb0d9f5e 219 struct
SquirrelGod 2:99b1cb0d9f5e 220 {
SquirrelGod 2:99b1cb0d9f5e 221 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
SquirrelGod 2:99b1cb0d9f5e 222 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
SquirrelGod 2:99b1cb0d9f5e 223 } b; /*!< Structure used for bit access */
SquirrelGod 2:99b1cb0d9f5e 224 uint32_t w; /*!< Type used for word access */
SquirrelGod 2:99b1cb0d9f5e 225 } IPSR_Type;
SquirrelGod 2:99b1cb0d9f5e 226
SquirrelGod 2:99b1cb0d9f5e 227
SquirrelGod 2:99b1cb0d9f5e 228 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
SquirrelGod 2:99b1cb0d9f5e 229 */
SquirrelGod 2:99b1cb0d9f5e 230 typedef union
SquirrelGod 2:99b1cb0d9f5e 231 {
SquirrelGod 2:99b1cb0d9f5e 232 struct
SquirrelGod 2:99b1cb0d9f5e 233 {
SquirrelGod 2:99b1cb0d9f5e 234 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
SquirrelGod 2:99b1cb0d9f5e 235 #if (__CORTEX_M != 0x04)
SquirrelGod 2:99b1cb0d9f5e 236 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
SquirrelGod 2:99b1cb0d9f5e 237 #else
SquirrelGod 2:99b1cb0d9f5e 238 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
SquirrelGod 2:99b1cb0d9f5e 239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
SquirrelGod 2:99b1cb0d9f5e 240 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
SquirrelGod 2:99b1cb0d9f5e 241 #endif
SquirrelGod 2:99b1cb0d9f5e 242 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
SquirrelGod 2:99b1cb0d9f5e 243 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
SquirrelGod 2:99b1cb0d9f5e 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
SquirrelGod 2:99b1cb0d9f5e 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
SquirrelGod 2:99b1cb0d9f5e 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
SquirrelGod 2:99b1cb0d9f5e 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
SquirrelGod 2:99b1cb0d9f5e 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
SquirrelGod 2:99b1cb0d9f5e 249 } b; /*!< Structure used for bit access */
SquirrelGod 2:99b1cb0d9f5e 250 uint32_t w; /*!< Type used for word access */
SquirrelGod 2:99b1cb0d9f5e 251 } xPSR_Type;
SquirrelGod 2:99b1cb0d9f5e 252
SquirrelGod 2:99b1cb0d9f5e 253
SquirrelGod 2:99b1cb0d9f5e 254 /** \brief Union type to access the Control Registers (CONTROL).
SquirrelGod 2:99b1cb0d9f5e 255 */
SquirrelGod 2:99b1cb0d9f5e 256 typedef union
SquirrelGod 2:99b1cb0d9f5e 257 {
SquirrelGod 2:99b1cb0d9f5e 258 struct
SquirrelGod 2:99b1cb0d9f5e 259 {
SquirrelGod 2:99b1cb0d9f5e 260 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
SquirrelGod 2:99b1cb0d9f5e 261 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
SquirrelGod 2:99b1cb0d9f5e 262 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
SquirrelGod 2:99b1cb0d9f5e 263 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
SquirrelGod 2:99b1cb0d9f5e 264 } b; /*!< Structure used for bit access */
SquirrelGod 2:99b1cb0d9f5e 265 uint32_t w; /*!< Type used for word access */
SquirrelGod 2:99b1cb0d9f5e 266 } CONTROL_Type;
SquirrelGod 2:99b1cb0d9f5e 267
SquirrelGod 2:99b1cb0d9f5e 268 /*@} end of group CMSIS_CORE */
SquirrelGod 2:99b1cb0d9f5e 269
SquirrelGod 2:99b1cb0d9f5e 270
SquirrelGod 2:99b1cb0d9f5e 271 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 272 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
SquirrelGod 2:99b1cb0d9f5e 273 \brief Type definitions for the NVIC Registers
SquirrelGod 2:99b1cb0d9f5e 274 @{
SquirrelGod 2:99b1cb0d9f5e 275 */
SquirrelGod 2:99b1cb0d9f5e 276
SquirrelGod 2:99b1cb0d9f5e 277 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
SquirrelGod 2:99b1cb0d9f5e 278 */
SquirrelGod 2:99b1cb0d9f5e 279 typedef struct
SquirrelGod 2:99b1cb0d9f5e 280 {
SquirrelGod 2:99b1cb0d9f5e 281 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
SquirrelGod 2:99b1cb0d9f5e 282 uint32_t RESERVED0[24];
SquirrelGod 2:99b1cb0d9f5e 283 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
SquirrelGod 2:99b1cb0d9f5e 284 uint32_t RSERVED1[24];
SquirrelGod 2:99b1cb0d9f5e 285 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
SquirrelGod 2:99b1cb0d9f5e 286 uint32_t RESERVED2[24];
SquirrelGod 2:99b1cb0d9f5e 287 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
SquirrelGod 2:99b1cb0d9f5e 288 uint32_t RESERVED3[24];
SquirrelGod 2:99b1cb0d9f5e 289 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
SquirrelGod 2:99b1cb0d9f5e 290 uint32_t RESERVED4[56];
SquirrelGod 2:99b1cb0d9f5e 291 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
SquirrelGod 2:99b1cb0d9f5e 292 uint32_t RESERVED5[644];
SquirrelGod 2:99b1cb0d9f5e 293 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
SquirrelGod 2:99b1cb0d9f5e 294 } NVIC_Type;
SquirrelGod 2:99b1cb0d9f5e 295
SquirrelGod 2:99b1cb0d9f5e 296 /* Software Triggered Interrupt Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 297 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
SquirrelGod 2:99b1cb0d9f5e 298 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
SquirrelGod 2:99b1cb0d9f5e 299
SquirrelGod 2:99b1cb0d9f5e 300 /*@} end of group CMSIS_NVIC */
SquirrelGod 2:99b1cb0d9f5e 301
SquirrelGod 2:99b1cb0d9f5e 302
SquirrelGod 2:99b1cb0d9f5e 303 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 304 \defgroup CMSIS_SCB System Control Block (SCB)
SquirrelGod 2:99b1cb0d9f5e 305 \brief Type definitions for the System Control Block Registers
SquirrelGod 2:99b1cb0d9f5e 306 @{
SquirrelGod 2:99b1cb0d9f5e 307 */
SquirrelGod 2:99b1cb0d9f5e 308
SquirrelGod 2:99b1cb0d9f5e 309 /** \brief Structure type to access the System Control Block (SCB).
SquirrelGod 2:99b1cb0d9f5e 310 */
SquirrelGod 2:99b1cb0d9f5e 311 typedef struct
SquirrelGod 2:99b1cb0d9f5e 312 {
SquirrelGod 2:99b1cb0d9f5e 313 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
SquirrelGod 2:99b1cb0d9f5e 314 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
SquirrelGod 2:99b1cb0d9f5e 315 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
SquirrelGod 2:99b1cb0d9f5e 316 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
SquirrelGod 2:99b1cb0d9f5e 317 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
SquirrelGod 2:99b1cb0d9f5e 318 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
SquirrelGod 2:99b1cb0d9f5e 319 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
SquirrelGod 2:99b1cb0d9f5e 320 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
SquirrelGod 2:99b1cb0d9f5e 321 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
SquirrelGod 2:99b1cb0d9f5e 322 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
SquirrelGod 2:99b1cb0d9f5e 323 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
SquirrelGod 2:99b1cb0d9f5e 324 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
SquirrelGod 2:99b1cb0d9f5e 325 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
SquirrelGod 2:99b1cb0d9f5e 326 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
SquirrelGod 2:99b1cb0d9f5e 327 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
SquirrelGod 2:99b1cb0d9f5e 328 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
SquirrelGod 2:99b1cb0d9f5e 329 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
SquirrelGod 2:99b1cb0d9f5e 330 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
SquirrelGod 2:99b1cb0d9f5e 331 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
SquirrelGod 2:99b1cb0d9f5e 332 uint32_t RESERVED0[5];
SquirrelGod 2:99b1cb0d9f5e 333 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
SquirrelGod 2:99b1cb0d9f5e 334 } SCB_Type;
SquirrelGod 2:99b1cb0d9f5e 335
SquirrelGod 2:99b1cb0d9f5e 336 /* SCB CPUID Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 337 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
SquirrelGod 2:99b1cb0d9f5e 338 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
SquirrelGod 2:99b1cb0d9f5e 339
SquirrelGod 2:99b1cb0d9f5e 340 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
SquirrelGod 2:99b1cb0d9f5e 341 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
SquirrelGod 2:99b1cb0d9f5e 342
SquirrelGod 2:99b1cb0d9f5e 343 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
SquirrelGod 2:99b1cb0d9f5e 344 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
SquirrelGod 2:99b1cb0d9f5e 345
SquirrelGod 2:99b1cb0d9f5e 346 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
SquirrelGod 2:99b1cb0d9f5e 347 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
SquirrelGod 2:99b1cb0d9f5e 348
SquirrelGod 2:99b1cb0d9f5e 349 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
SquirrelGod 2:99b1cb0d9f5e 350 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
SquirrelGod 2:99b1cb0d9f5e 351
SquirrelGod 2:99b1cb0d9f5e 352 /* SCB Interrupt Control State Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 353 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
SquirrelGod 2:99b1cb0d9f5e 354 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
SquirrelGod 2:99b1cb0d9f5e 355
SquirrelGod 2:99b1cb0d9f5e 356 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
SquirrelGod 2:99b1cb0d9f5e 357 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
SquirrelGod 2:99b1cb0d9f5e 358
SquirrelGod 2:99b1cb0d9f5e 359 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
SquirrelGod 2:99b1cb0d9f5e 360 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
SquirrelGod 2:99b1cb0d9f5e 361
SquirrelGod 2:99b1cb0d9f5e 362 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
SquirrelGod 2:99b1cb0d9f5e 363 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
SquirrelGod 2:99b1cb0d9f5e 364
SquirrelGod 2:99b1cb0d9f5e 365 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
SquirrelGod 2:99b1cb0d9f5e 366 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
SquirrelGod 2:99b1cb0d9f5e 367
SquirrelGod 2:99b1cb0d9f5e 368 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
SquirrelGod 2:99b1cb0d9f5e 369 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
SquirrelGod 2:99b1cb0d9f5e 370
SquirrelGod 2:99b1cb0d9f5e 371 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
SquirrelGod 2:99b1cb0d9f5e 372 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
SquirrelGod 2:99b1cb0d9f5e 373
SquirrelGod 2:99b1cb0d9f5e 374 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
SquirrelGod 2:99b1cb0d9f5e 375 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
SquirrelGod 2:99b1cb0d9f5e 376
SquirrelGod 2:99b1cb0d9f5e 377 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
SquirrelGod 2:99b1cb0d9f5e 378 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
SquirrelGod 2:99b1cb0d9f5e 379
SquirrelGod 2:99b1cb0d9f5e 380 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
SquirrelGod 2:99b1cb0d9f5e 381 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
SquirrelGod 2:99b1cb0d9f5e 382
SquirrelGod 2:99b1cb0d9f5e 383 /* SCB Vector Table Offset Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 384 #if (__CM3_REV < 0x0201) /* core r2p1 */
SquirrelGod 2:99b1cb0d9f5e 385 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
SquirrelGod 2:99b1cb0d9f5e 386 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
SquirrelGod 2:99b1cb0d9f5e 387
SquirrelGod 2:99b1cb0d9f5e 388 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
SquirrelGod 2:99b1cb0d9f5e 389 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
SquirrelGod 2:99b1cb0d9f5e 390 #else
SquirrelGod 2:99b1cb0d9f5e 391 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
SquirrelGod 2:99b1cb0d9f5e 392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
SquirrelGod 2:99b1cb0d9f5e 393 #endif
SquirrelGod 2:99b1cb0d9f5e 394
SquirrelGod 2:99b1cb0d9f5e 395 /* SCB Application Interrupt and Reset Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 396 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
SquirrelGod 2:99b1cb0d9f5e 397 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
SquirrelGod 2:99b1cb0d9f5e 398
SquirrelGod 2:99b1cb0d9f5e 399 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
SquirrelGod 2:99b1cb0d9f5e 400 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
SquirrelGod 2:99b1cb0d9f5e 401
SquirrelGod 2:99b1cb0d9f5e 402 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
SquirrelGod 2:99b1cb0d9f5e 403 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
SquirrelGod 2:99b1cb0d9f5e 404
SquirrelGod 2:99b1cb0d9f5e 405 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
SquirrelGod 2:99b1cb0d9f5e 406 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
SquirrelGod 2:99b1cb0d9f5e 407
SquirrelGod 2:99b1cb0d9f5e 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
SquirrelGod 2:99b1cb0d9f5e 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
SquirrelGod 2:99b1cb0d9f5e 410
SquirrelGod 2:99b1cb0d9f5e 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
SquirrelGod 2:99b1cb0d9f5e 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
SquirrelGod 2:99b1cb0d9f5e 413
SquirrelGod 2:99b1cb0d9f5e 414 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
SquirrelGod 2:99b1cb0d9f5e 415 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
SquirrelGod 2:99b1cb0d9f5e 416
SquirrelGod 2:99b1cb0d9f5e 417 /* SCB System Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 418 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
SquirrelGod 2:99b1cb0d9f5e 419 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
SquirrelGod 2:99b1cb0d9f5e 420
SquirrelGod 2:99b1cb0d9f5e 421 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
SquirrelGod 2:99b1cb0d9f5e 422 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
SquirrelGod 2:99b1cb0d9f5e 423
SquirrelGod 2:99b1cb0d9f5e 424 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
SquirrelGod 2:99b1cb0d9f5e 425 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
SquirrelGod 2:99b1cb0d9f5e 426
SquirrelGod 2:99b1cb0d9f5e 427 /* SCB Configuration Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 428 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
SquirrelGod 2:99b1cb0d9f5e 429 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
SquirrelGod 2:99b1cb0d9f5e 430
SquirrelGod 2:99b1cb0d9f5e 431 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
SquirrelGod 2:99b1cb0d9f5e 432 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
SquirrelGod 2:99b1cb0d9f5e 433
SquirrelGod 2:99b1cb0d9f5e 434 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
SquirrelGod 2:99b1cb0d9f5e 435 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
SquirrelGod 2:99b1cb0d9f5e 436
SquirrelGod 2:99b1cb0d9f5e 437 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
SquirrelGod 2:99b1cb0d9f5e 438 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
SquirrelGod 2:99b1cb0d9f5e 439
SquirrelGod 2:99b1cb0d9f5e 440 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
SquirrelGod 2:99b1cb0d9f5e 441 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
SquirrelGod 2:99b1cb0d9f5e 442
SquirrelGod 2:99b1cb0d9f5e 443 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
SquirrelGod 2:99b1cb0d9f5e 444 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
SquirrelGod 2:99b1cb0d9f5e 445
SquirrelGod 2:99b1cb0d9f5e 446 /* SCB System Handler Control and State Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 447 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
SquirrelGod 2:99b1cb0d9f5e 448 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 449
SquirrelGod 2:99b1cb0d9f5e 450 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
SquirrelGod 2:99b1cb0d9f5e 451 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 452
SquirrelGod 2:99b1cb0d9f5e 453 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
SquirrelGod 2:99b1cb0d9f5e 454 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 455
SquirrelGod 2:99b1cb0d9f5e 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
SquirrelGod 2:99b1cb0d9f5e 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
SquirrelGod 2:99b1cb0d9f5e 458
SquirrelGod 2:99b1cb0d9f5e 459 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
SquirrelGod 2:99b1cb0d9f5e 460 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
SquirrelGod 2:99b1cb0d9f5e 461
SquirrelGod 2:99b1cb0d9f5e 462 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
SquirrelGod 2:99b1cb0d9f5e 463 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
SquirrelGod 2:99b1cb0d9f5e 464
SquirrelGod 2:99b1cb0d9f5e 465 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
SquirrelGod 2:99b1cb0d9f5e 466 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
SquirrelGod 2:99b1cb0d9f5e 467
SquirrelGod 2:99b1cb0d9f5e 468 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
SquirrelGod 2:99b1cb0d9f5e 469 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
SquirrelGod 2:99b1cb0d9f5e 470
SquirrelGod 2:99b1cb0d9f5e 471 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
SquirrelGod 2:99b1cb0d9f5e 472 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
SquirrelGod 2:99b1cb0d9f5e 473
SquirrelGod 2:99b1cb0d9f5e 474 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
SquirrelGod 2:99b1cb0d9f5e 475 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
SquirrelGod 2:99b1cb0d9f5e 476
SquirrelGod 2:99b1cb0d9f5e 477 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
SquirrelGod 2:99b1cb0d9f5e 478 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
SquirrelGod 2:99b1cb0d9f5e 479
SquirrelGod 2:99b1cb0d9f5e 480 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
SquirrelGod 2:99b1cb0d9f5e 481 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
SquirrelGod 2:99b1cb0d9f5e 482
SquirrelGod 2:99b1cb0d9f5e 483 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
SquirrelGod 2:99b1cb0d9f5e 484 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
SquirrelGod 2:99b1cb0d9f5e 485
SquirrelGod 2:99b1cb0d9f5e 486 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
SquirrelGod 2:99b1cb0d9f5e 487 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
SquirrelGod 2:99b1cb0d9f5e 488
SquirrelGod 2:99b1cb0d9f5e 489 /* SCB Configurable Fault Status Registers Definitions */
SquirrelGod 2:99b1cb0d9f5e 490 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
SquirrelGod 2:99b1cb0d9f5e 491 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
SquirrelGod 2:99b1cb0d9f5e 492
SquirrelGod 2:99b1cb0d9f5e 493 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
SquirrelGod 2:99b1cb0d9f5e 494 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
SquirrelGod 2:99b1cb0d9f5e 495
SquirrelGod 2:99b1cb0d9f5e 496 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
SquirrelGod 2:99b1cb0d9f5e 497 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
SquirrelGod 2:99b1cb0d9f5e 498
SquirrelGod 2:99b1cb0d9f5e 499 /* SCB Hard Fault Status Registers Definitions */
SquirrelGod 2:99b1cb0d9f5e 500 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
SquirrelGod 2:99b1cb0d9f5e 501 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
SquirrelGod 2:99b1cb0d9f5e 502
SquirrelGod 2:99b1cb0d9f5e 503 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
SquirrelGod 2:99b1cb0d9f5e 504 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
SquirrelGod 2:99b1cb0d9f5e 505
SquirrelGod 2:99b1cb0d9f5e 506 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
SquirrelGod 2:99b1cb0d9f5e 507 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
SquirrelGod 2:99b1cb0d9f5e 508
SquirrelGod 2:99b1cb0d9f5e 509 /* SCB Debug Fault Status Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 510 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
SquirrelGod 2:99b1cb0d9f5e 511 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
SquirrelGod 2:99b1cb0d9f5e 512
SquirrelGod 2:99b1cb0d9f5e 513 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
SquirrelGod 2:99b1cb0d9f5e 514 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
SquirrelGod 2:99b1cb0d9f5e 515
SquirrelGod 2:99b1cb0d9f5e 516 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
SquirrelGod 2:99b1cb0d9f5e 517 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
SquirrelGod 2:99b1cb0d9f5e 518
SquirrelGod 2:99b1cb0d9f5e 519 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
SquirrelGod 2:99b1cb0d9f5e 520 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
SquirrelGod 2:99b1cb0d9f5e 521
SquirrelGod 2:99b1cb0d9f5e 522 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
SquirrelGod 2:99b1cb0d9f5e 523 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
SquirrelGod 2:99b1cb0d9f5e 524
SquirrelGod 2:99b1cb0d9f5e 525 /*@} end of group CMSIS_SCB */
SquirrelGod 2:99b1cb0d9f5e 526
SquirrelGod 2:99b1cb0d9f5e 527
SquirrelGod 2:99b1cb0d9f5e 528 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 529 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
SquirrelGod 2:99b1cb0d9f5e 530 \brief Type definitions for the System Control and ID Register not in the SCB
SquirrelGod 2:99b1cb0d9f5e 531 @{
SquirrelGod 2:99b1cb0d9f5e 532 */
SquirrelGod 2:99b1cb0d9f5e 533
SquirrelGod 2:99b1cb0d9f5e 534 /** \brief Structure type to access the System Control and ID Register not in the SCB.
SquirrelGod 2:99b1cb0d9f5e 535 */
SquirrelGod 2:99b1cb0d9f5e 536 typedef struct
SquirrelGod 2:99b1cb0d9f5e 537 {
SquirrelGod 2:99b1cb0d9f5e 538 uint32_t RESERVED0[1];
SquirrelGod 2:99b1cb0d9f5e 539 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
SquirrelGod 2:99b1cb0d9f5e 540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
SquirrelGod 2:99b1cb0d9f5e 541 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
SquirrelGod 2:99b1cb0d9f5e 542 #else
SquirrelGod 2:99b1cb0d9f5e 543 uint32_t RESERVED1[1];
SquirrelGod 2:99b1cb0d9f5e 544 #endif
SquirrelGod 2:99b1cb0d9f5e 545 } SCnSCB_Type;
SquirrelGod 2:99b1cb0d9f5e 546
SquirrelGod 2:99b1cb0d9f5e 547 /* Interrupt Controller Type Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 548 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
SquirrelGod 2:99b1cb0d9f5e 549 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
SquirrelGod 2:99b1cb0d9f5e 550
SquirrelGod 2:99b1cb0d9f5e 551 /* Auxiliary Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 552
SquirrelGod 2:99b1cb0d9f5e 553 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
SquirrelGod 2:99b1cb0d9f5e 554 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
SquirrelGod 2:99b1cb0d9f5e 555
SquirrelGod 2:99b1cb0d9f5e 556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
SquirrelGod 2:99b1cb0d9f5e 557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
SquirrelGod 2:99b1cb0d9f5e 558
SquirrelGod 2:99b1cb0d9f5e 559 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
SquirrelGod 2:99b1cb0d9f5e 560 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
SquirrelGod 2:99b1cb0d9f5e 561
SquirrelGod 2:99b1cb0d9f5e 562 /*@} end of group CMSIS_SCnotSCB */
SquirrelGod 2:99b1cb0d9f5e 563
SquirrelGod 2:99b1cb0d9f5e 564
SquirrelGod 2:99b1cb0d9f5e 565 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 566 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
SquirrelGod 2:99b1cb0d9f5e 567 \brief Type definitions for the System Timer Registers.
SquirrelGod 2:99b1cb0d9f5e 568 @{
SquirrelGod 2:99b1cb0d9f5e 569 */
SquirrelGod 2:99b1cb0d9f5e 570
SquirrelGod 2:99b1cb0d9f5e 571 /** \brief Structure type to access the System Timer (SysTick).
SquirrelGod 2:99b1cb0d9f5e 572 */
SquirrelGod 2:99b1cb0d9f5e 573 typedef struct
SquirrelGod 2:99b1cb0d9f5e 574 {
SquirrelGod 2:99b1cb0d9f5e 575 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
SquirrelGod 2:99b1cb0d9f5e 576 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
SquirrelGod 2:99b1cb0d9f5e 577 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
SquirrelGod 2:99b1cb0d9f5e 578 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
SquirrelGod 2:99b1cb0d9f5e 579 } SysTick_Type;
SquirrelGod 2:99b1cb0d9f5e 580
SquirrelGod 2:99b1cb0d9f5e 581 /* SysTick Control / Status Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 582 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
SquirrelGod 2:99b1cb0d9f5e 583 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
SquirrelGod 2:99b1cb0d9f5e 584
SquirrelGod 2:99b1cb0d9f5e 585 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
SquirrelGod 2:99b1cb0d9f5e 586 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
SquirrelGod 2:99b1cb0d9f5e 587
SquirrelGod 2:99b1cb0d9f5e 588 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
SquirrelGod 2:99b1cb0d9f5e 589 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
SquirrelGod 2:99b1cb0d9f5e 590
SquirrelGod 2:99b1cb0d9f5e 591 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
SquirrelGod 2:99b1cb0d9f5e 592 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
SquirrelGod 2:99b1cb0d9f5e 593
SquirrelGod 2:99b1cb0d9f5e 594 /* SysTick Reload Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 595 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
SquirrelGod 2:99b1cb0d9f5e 596 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
SquirrelGod 2:99b1cb0d9f5e 597
SquirrelGod 2:99b1cb0d9f5e 598 /* SysTick Current Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 599 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
SquirrelGod 2:99b1cb0d9f5e 600 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
SquirrelGod 2:99b1cb0d9f5e 601
SquirrelGod 2:99b1cb0d9f5e 602 /* SysTick Calibration Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 603 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
SquirrelGod 2:99b1cb0d9f5e 604 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
SquirrelGod 2:99b1cb0d9f5e 605
SquirrelGod 2:99b1cb0d9f5e 606 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
SquirrelGod 2:99b1cb0d9f5e 607 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
SquirrelGod 2:99b1cb0d9f5e 608
SquirrelGod 2:99b1cb0d9f5e 609 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
SquirrelGod 2:99b1cb0d9f5e 610 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
SquirrelGod 2:99b1cb0d9f5e 611
SquirrelGod 2:99b1cb0d9f5e 612 /*@} end of group CMSIS_SysTick */
SquirrelGod 2:99b1cb0d9f5e 613
SquirrelGod 2:99b1cb0d9f5e 614
SquirrelGod 2:99b1cb0d9f5e 615 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 616 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
SquirrelGod 2:99b1cb0d9f5e 617 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
SquirrelGod 2:99b1cb0d9f5e 618 @{
SquirrelGod 2:99b1cb0d9f5e 619 */
SquirrelGod 2:99b1cb0d9f5e 620
SquirrelGod 2:99b1cb0d9f5e 621 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
SquirrelGod 2:99b1cb0d9f5e 622 */
SquirrelGod 2:99b1cb0d9f5e 623 typedef struct
SquirrelGod 2:99b1cb0d9f5e 624 {
SquirrelGod 2:99b1cb0d9f5e 625 __O union
SquirrelGod 2:99b1cb0d9f5e 626 {
SquirrelGod 2:99b1cb0d9f5e 627 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
SquirrelGod 2:99b1cb0d9f5e 628 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
SquirrelGod 2:99b1cb0d9f5e 629 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
SquirrelGod 2:99b1cb0d9f5e 630 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
SquirrelGod 2:99b1cb0d9f5e 631 uint32_t RESERVED0[864];
SquirrelGod 2:99b1cb0d9f5e 632 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
SquirrelGod 2:99b1cb0d9f5e 633 uint32_t RESERVED1[15];
SquirrelGod 2:99b1cb0d9f5e 634 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
SquirrelGod 2:99b1cb0d9f5e 635 uint32_t RESERVED2[15];
SquirrelGod 2:99b1cb0d9f5e 636 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
SquirrelGod 2:99b1cb0d9f5e 637 } ITM_Type;
SquirrelGod 2:99b1cb0d9f5e 638
SquirrelGod 2:99b1cb0d9f5e 639 /* ITM Trace Privilege Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 640 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
SquirrelGod 2:99b1cb0d9f5e 641 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
SquirrelGod 2:99b1cb0d9f5e 642
SquirrelGod 2:99b1cb0d9f5e 643 /* ITM Trace Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 644 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
SquirrelGod 2:99b1cb0d9f5e 645 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
SquirrelGod 2:99b1cb0d9f5e 646
SquirrelGod 2:99b1cb0d9f5e 647 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
SquirrelGod 2:99b1cb0d9f5e 648 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
SquirrelGod 2:99b1cb0d9f5e 649
SquirrelGod 2:99b1cb0d9f5e 650 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
SquirrelGod 2:99b1cb0d9f5e 651 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
SquirrelGod 2:99b1cb0d9f5e 652
SquirrelGod 2:99b1cb0d9f5e 653 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
SquirrelGod 2:99b1cb0d9f5e 654 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
SquirrelGod 2:99b1cb0d9f5e 655
SquirrelGod 2:99b1cb0d9f5e 656 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
SquirrelGod 2:99b1cb0d9f5e 657 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
SquirrelGod 2:99b1cb0d9f5e 658
SquirrelGod 2:99b1cb0d9f5e 659 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
SquirrelGod 2:99b1cb0d9f5e 660 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
SquirrelGod 2:99b1cb0d9f5e 661
SquirrelGod 2:99b1cb0d9f5e 662 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
SquirrelGod 2:99b1cb0d9f5e 663 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
SquirrelGod 2:99b1cb0d9f5e 664
SquirrelGod 2:99b1cb0d9f5e 665 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
SquirrelGod 2:99b1cb0d9f5e 666 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
SquirrelGod 2:99b1cb0d9f5e 667
SquirrelGod 2:99b1cb0d9f5e 668 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
SquirrelGod 2:99b1cb0d9f5e 669 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
SquirrelGod 2:99b1cb0d9f5e 670
SquirrelGod 2:99b1cb0d9f5e 671 /*@}*/ /* end of group CMSIS_ITM */
SquirrelGod 2:99b1cb0d9f5e 672
SquirrelGod 2:99b1cb0d9f5e 673
SquirrelGod 2:99b1cb0d9f5e 674 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 675 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
SquirrelGod 2:99b1cb0d9f5e 676 \brief Type definitions for the Data Watchpoint and Trace (DWT)
SquirrelGod 2:99b1cb0d9f5e 677 @{
SquirrelGod 2:99b1cb0d9f5e 678 */
SquirrelGod 2:99b1cb0d9f5e 679
SquirrelGod 2:99b1cb0d9f5e 680 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
SquirrelGod 2:99b1cb0d9f5e 681 */
SquirrelGod 2:99b1cb0d9f5e 682 typedef struct
SquirrelGod 2:99b1cb0d9f5e 683 {
SquirrelGod 2:99b1cb0d9f5e 684 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
SquirrelGod 2:99b1cb0d9f5e 685 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
SquirrelGod 2:99b1cb0d9f5e 686 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
SquirrelGod 2:99b1cb0d9f5e 687 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
SquirrelGod 2:99b1cb0d9f5e 688 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
SquirrelGod 2:99b1cb0d9f5e 689 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
SquirrelGod 2:99b1cb0d9f5e 690 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
SquirrelGod 2:99b1cb0d9f5e 691 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
SquirrelGod 2:99b1cb0d9f5e 692 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
SquirrelGod 2:99b1cb0d9f5e 693 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
SquirrelGod 2:99b1cb0d9f5e 694 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
SquirrelGod 2:99b1cb0d9f5e 695 uint32_t RESERVED0[1];
SquirrelGod 2:99b1cb0d9f5e 696 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
SquirrelGod 2:99b1cb0d9f5e 697 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
SquirrelGod 2:99b1cb0d9f5e 698 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
SquirrelGod 2:99b1cb0d9f5e 699 uint32_t RESERVED1[1];
SquirrelGod 2:99b1cb0d9f5e 700 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
SquirrelGod 2:99b1cb0d9f5e 701 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
SquirrelGod 2:99b1cb0d9f5e 702 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
SquirrelGod 2:99b1cb0d9f5e 703 uint32_t RESERVED2[1];
SquirrelGod 2:99b1cb0d9f5e 704 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
SquirrelGod 2:99b1cb0d9f5e 705 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
SquirrelGod 2:99b1cb0d9f5e 706 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
SquirrelGod 2:99b1cb0d9f5e 707 } DWT_Type;
SquirrelGod 2:99b1cb0d9f5e 708
SquirrelGod 2:99b1cb0d9f5e 709 /* DWT Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 710 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
SquirrelGod 2:99b1cb0d9f5e 711 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
SquirrelGod 2:99b1cb0d9f5e 712
SquirrelGod 2:99b1cb0d9f5e 713 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
SquirrelGod 2:99b1cb0d9f5e 714 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
SquirrelGod 2:99b1cb0d9f5e 715
SquirrelGod 2:99b1cb0d9f5e 716 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
SquirrelGod 2:99b1cb0d9f5e 717 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
SquirrelGod 2:99b1cb0d9f5e 718
SquirrelGod 2:99b1cb0d9f5e 719 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
SquirrelGod 2:99b1cb0d9f5e 720 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 721
SquirrelGod 2:99b1cb0d9f5e 722 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
SquirrelGod 2:99b1cb0d9f5e 723 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 724
SquirrelGod 2:99b1cb0d9f5e 725 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 726 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 727
SquirrelGod 2:99b1cb0d9f5e 728 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 729 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 730
SquirrelGod 2:99b1cb0d9f5e 731 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 732 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 733
SquirrelGod 2:99b1cb0d9f5e 734 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 735 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 736
SquirrelGod 2:99b1cb0d9f5e 737 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 738 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 739
SquirrelGod 2:99b1cb0d9f5e 740 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
SquirrelGod 2:99b1cb0d9f5e 741 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 742
SquirrelGod 2:99b1cb0d9f5e 743 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
SquirrelGod 2:99b1cb0d9f5e 744 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
SquirrelGod 2:99b1cb0d9f5e 745
SquirrelGod 2:99b1cb0d9f5e 746 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
SquirrelGod 2:99b1cb0d9f5e 747 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
SquirrelGod 2:99b1cb0d9f5e 748
SquirrelGod 2:99b1cb0d9f5e 749 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
SquirrelGod 2:99b1cb0d9f5e 750 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
SquirrelGod 2:99b1cb0d9f5e 751
SquirrelGod 2:99b1cb0d9f5e 752 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
SquirrelGod 2:99b1cb0d9f5e 753 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
SquirrelGod 2:99b1cb0d9f5e 754
SquirrelGod 2:99b1cb0d9f5e 755 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
SquirrelGod 2:99b1cb0d9f5e 756 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
SquirrelGod 2:99b1cb0d9f5e 757
SquirrelGod 2:99b1cb0d9f5e 758 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
SquirrelGod 2:99b1cb0d9f5e 759 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
SquirrelGod 2:99b1cb0d9f5e 760
SquirrelGod 2:99b1cb0d9f5e 761 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
SquirrelGod 2:99b1cb0d9f5e 762 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
SquirrelGod 2:99b1cb0d9f5e 763
SquirrelGod 2:99b1cb0d9f5e 764 /* DWT CPI Count Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 765 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
SquirrelGod 2:99b1cb0d9f5e 766 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
SquirrelGod 2:99b1cb0d9f5e 767
SquirrelGod 2:99b1cb0d9f5e 768 /* DWT Exception Overhead Count Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 769 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
SquirrelGod 2:99b1cb0d9f5e 770 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 771
SquirrelGod 2:99b1cb0d9f5e 772 /* DWT Sleep Count Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 773 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
SquirrelGod 2:99b1cb0d9f5e 774 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 775
SquirrelGod 2:99b1cb0d9f5e 776 /* DWT LSU Count Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 777 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
SquirrelGod 2:99b1cb0d9f5e 778 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 779
SquirrelGod 2:99b1cb0d9f5e 780 /* DWT Folded-instruction Count Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 781 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
SquirrelGod 2:99b1cb0d9f5e 782 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
SquirrelGod 2:99b1cb0d9f5e 783
SquirrelGod 2:99b1cb0d9f5e 784 /* DWT Comparator Mask Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 785 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
SquirrelGod 2:99b1cb0d9f5e 786 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
SquirrelGod 2:99b1cb0d9f5e 787
SquirrelGod 2:99b1cb0d9f5e 788 /* DWT Comparator Function Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 789 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
SquirrelGod 2:99b1cb0d9f5e 790 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
SquirrelGod 2:99b1cb0d9f5e 791
SquirrelGod 2:99b1cb0d9f5e 792 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
SquirrelGod 2:99b1cb0d9f5e 793 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
SquirrelGod 2:99b1cb0d9f5e 794
SquirrelGod 2:99b1cb0d9f5e 795 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
SquirrelGod 2:99b1cb0d9f5e 796 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
SquirrelGod 2:99b1cb0d9f5e 797
SquirrelGod 2:99b1cb0d9f5e 798 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
SquirrelGod 2:99b1cb0d9f5e 799 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
SquirrelGod 2:99b1cb0d9f5e 800
SquirrelGod 2:99b1cb0d9f5e 801 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
SquirrelGod 2:99b1cb0d9f5e 802 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
SquirrelGod 2:99b1cb0d9f5e 803
SquirrelGod 2:99b1cb0d9f5e 804 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
SquirrelGod 2:99b1cb0d9f5e 805 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
SquirrelGod 2:99b1cb0d9f5e 806
SquirrelGod 2:99b1cb0d9f5e 807 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
SquirrelGod 2:99b1cb0d9f5e 808 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
SquirrelGod 2:99b1cb0d9f5e 809
SquirrelGod 2:99b1cb0d9f5e 810 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
SquirrelGod 2:99b1cb0d9f5e 811 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
SquirrelGod 2:99b1cb0d9f5e 812
SquirrelGod 2:99b1cb0d9f5e 813 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
SquirrelGod 2:99b1cb0d9f5e 814 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
SquirrelGod 2:99b1cb0d9f5e 815
SquirrelGod 2:99b1cb0d9f5e 816 /*@}*/ /* end of group CMSIS_DWT */
SquirrelGod 2:99b1cb0d9f5e 817
SquirrelGod 2:99b1cb0d9f5e 818
SquirrelGod 2:99b1cb0d9f5e 819 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 820 \defgroup CMSIS_TPI Trace Port Interface (TPI)
SquirrelGod 2:99b1cb0d9f5e 821 \brief Type definitions for the Trace Port Interface (TPI)
SquirrelGod 2:99b1cb0d9f5e 822 @{
SquirrelGod 2:99b1cb0d9f5e 823 */
SquirrelGod 2:99b1cb0d9f5e 824
SquirrelGod 2:99b1cb0d9f5e 825 /** \brief Structure type to access the Trace Port Interface Register (TPI).
SquirrelGod 2:99b1cb0d9f5e 826 */
SquirrelGod 2:99b1cb0d9f5e 827 typedef struct
SquirrelGod 2:99b1cb0d9f5e 828 {
SquirrelGod 2:99b1cb0d9f5e 829 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
SquirrelGod 2:99b1cb0d9f5e 830 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
SquirrelGod 2:99b1cb0d9f5e 831 uint32_t RESERVED0[2];
SquirrelGod 2:99b1cb0d9f5e 832 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
SquirrelGod 2:99b1cb0d9f5e 833 uint32_t RESERVED1[55];
SquirrelGod 2:99b1cb0d9f5e 834 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
SquirrelGod 2:99b1cb0d9f5e 835 uint32_t RESERVED2[131];
SquirrelGod 2:99b1cb0d9f5e 836 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
SquirrelGod 2:99b1cb0d9f5e 837 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
SquirrelGod 2:99b1cb0d9f5e 838 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
SquirrelGod 2:99b1cb0d9f5e 839 uint32_t RESERVED3[759];
SquirrelGod 2:99b1cb0d9f5e 840 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
SquirrelGod 2:99b1cb0d9f5e 841 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
SquirrelGod 2:99b1cb0d9f5e 842 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
SquirrelGod 2:99b1cb0d9f5e 843 uint32_t RESERVED4[1];
SquirrelGod 2:99b1cb0d9f5e 844 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
SquirrelGod 2:99b1cb0d9f5e 845 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
SquirrelGod 2:99b1cb0d9f5e 846 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
SquirrelGod 2:99b1cb0d9f5e 847 uint32_t RESERVED5[39];
SquirrelGod 2:99b1cb0d9f5e 848 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
SquirrelGod 2:99b1cb0d9f5e 849 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
SquirrelGod 2:99b1cb0d9f5e 850 uint32_t RESERVED7[8];
SquirrelGod 2:99b1cb0d9f5e 851 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
SquirrelGod 2:99b1cb0d9f5e 852 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
SquirrelGod 2:99b1cb0d9f5e 853 } TPI_Type;
SquirrelGod 2:99b1cb0d9f5e 854
SquirrelGod 2:99b1cb0d9f5e 855 /* TPI Asynchronous Clock Prescaler Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 856 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
SquirrelGod 2:99b1cb0d9f5e 857 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
SquirrelGod 2:99b1cb0d9f5e 858
SquirrelGod 2:99b1cb0d9f5e 859 /* TPI Selected Pin Protocol Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 860 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
SquirrelGod 2:99b1cb0d9f5e 861 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
SquirrelGod 2:99b1cb0d9f5e 862
SquirrelGod 2:99b1cb0d9f5e 863 /* TPI Formatter and Flush Status Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 864 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
SquirrelGod 2:99b1cb0d9f5e 865 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
SquirrelGod 2:99b1cb0d9f5e 866
SquirrelGod 2:99b1cb0d9f5e 867 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
SquirrelGod 2:99b1cb0d9f5e 868 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
SquirrelGod 2:99b1cb0d9f5e 869
SquirrelGod 2:99b1cb0d9f5e 870 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
SquirrelGod 2:99b1cb0d9f5e 871 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
SquirrelGod 2:99b1cb0d9f5e 872
SquirrelGod 2:99b1cb0d9f5e 873 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
SquirrelGod 2:99b1cb0d9f5e 874 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
SquirrelGod 2:99b1cb0d9f5e 875
SquirrelGod 2:99b1cb0d9f5e 876 /* TPI Formatter and Flush Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 877 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
SquirrelGod 2:99b1cb0d9f5e 878 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
SquirrelGod 2:99b1cb0d9f5e 879
SquirrelGod 2:99b1cb0d9f5e 880 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
SquirrelGod 2:99b1cb0d9f5e 881 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
SquirrelGod 2:99b1cb0d9f5e 882
SquirrelGod 2:99b1cb0d9f5e 883 /* TPI TRIGGER Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 884 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
SquirrelGod 2:99b1cb0d9f5e 885 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
SquirrelGod 2:99b1cb0d9f5e 886
SquirrelGod 2:99b1cb0d9f5e 887 /* TPI Integration ETM Data Register Definitions (FIFO0) */
SquirrelGod 2:99b1cb0d9f5e 888 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
SquirrelGod 2:99b1cb0d9f5e 889 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 890
SquirrelGod 2:99b1cb0d9f5e 891 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
SquirrelGod 2:99b1cb0d9f5e 892 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
SquirrelGod 2:99b1cb0d9f5e 893
SquirrelGod 2:99b1cb0d9f5e 894 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
SquirrelGod 2:99b1cb0d9f5e 895 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 896
SquirrelGod 2:99b1cb0d9f5e 897 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
SquirrelGod 2:99b1cb0d9f5e 898 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
SquirrelGod 2:99b1cb0d9f5e 899
SquirrelGod 2:99b1cb0d9f5e 900 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
SquirrelGod 2:99b1cb0d9f5e 901 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
SquirrelGod 2:99b1cb0d9f5e 902
SquirrelGod 2:99b1cb0d9f5e 903 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
SquirrelGod 2:99b1cb0d9f5e 904 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
SquirrelGod 2:99b1cb0d9f5e 905
SquirrelGod 2:99b1cb0d9f5e 906 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
SquirrelGod 2:99b1cb0d9f5e 907 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
SquirrelGod 2:99b1cb0d9f5e 908
SquirrelGod 2:99b1cb0d9f5e 909 /* TPI ITATBCTR2 Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 910 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
SquirrelGod 2:99b1cb0d9f5e 911 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
SquirrelGod 2:99b1cb0d9f5e 912
SquirrelGod 2:99b1cb0d9f5e 913 /* TPI Integration ITM Data Register Definitions (FIFO1) */
SquirrelGod 2:99b1cb0d9f5e 914 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
SquirrelGod 2:99b1cb0d9f5e 915 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 916
SquirrelGod 2:99b1cb0d9f5e 917 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
SquirrelGod 2:99b1cb0d9f5e 918 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
SquirrelGod 2:99b1cb0d9f5e 919
SquirrelGod 2:99b1cb0d9f5e 920 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
SquirrelGod 2:99b1cb0d9f5e 921 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 922
SquirrelGod 2:99b1cb0d9f5e 923 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
SquirrelGod 2:99b1cb0d9f5e 924 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
SquirrelGod 2:99b1cb0d9f5e 925
SquirrelGod 2:99b1cb0d9f5e 926 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
SquirrelGod 2:99b1cb0d9f5e 927 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
SquirrelGod 2:99b1cb0d9f5e 928
SquirrelGod 2:99b1cb0d9f5e 929 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
SquirrelGod 2:99b1cb0d9f5e 930 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
SquirrelGod 2:99b1cb0d9f5e 931
SquirrelGod 2:99b1cb0d9f5e 932 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
SquirrelGod 2:99b1cb0d9f5e 933 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
SquirrelGod 2:99b1cb0d9f5e 934
SquirrelGod 2:99b1cb0d9f5e 935 /* TPI ITATBCTR0 Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 936 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
SquirrelGod 2:99b1cb0d9f5e 937 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
SquirrelGod 2:99b1cb0d9f5e 938
SquirrelGod 2:99b1cb0d9f5e 939 /* TPI Integration Mode Control Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 940 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
SquirrelGod 2:99b1cb0d9f5e 941 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
SquirrelGod 2:99b1cb0d9f5e 942
SquirrelGod 2:99b1cb0d9f5e 943 /* TPI DEVID Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 944 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
SquirrelGod 2:99b1cb0d9f5e 945 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 946
SquirrelGod 2:99b1cb0d9f5e 947 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
SquirrelGod 2:99b1cb0d9f5e 948 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 949
SquirrelGod 2:99b1cb0d9f5e 950 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
SquirrelGod 2:99b1cb0d9f5e 951 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
SquirrelGod 2:99b1cb0d9f5e 952
SquirrelGod 2:99b1cb0d9f5e 953 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
SquirrelGod 2:99b1cb0d9f5e 954 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
SquirrelGod 2:99b1cb0d9f5e 955
SquirrelGod 2:99b1cb0d9f5e 956 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
SquirrelGod 2:99b1cb0d9f5e 957 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
SquirrelGod 2:99b1cb0d9f5e 958
SquirrelGod 2:99b1cb0d9f5e 959 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
SquirrelGod 2:99b1cb0d9f5e 960 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
SquirrelGod 2:99b1cb0d9f5e 961
SquirrelGod 2:99b1cb0d9f5e 962 /* TPI DEVTYPE Register Definitions */
SquirrelGod 2:99b1cb0d9f5e 963 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
SquirrelGod 2:99b1cb0d9f5e 964 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
SquirrelGod 2:99b1cb0d9f5e 965
SquirrelGod 2:99b1cb0d9f5e 966 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
SquirrelGod 2:99b1cb0d9f5e 967 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
SquirrelGod 2:99b1cb0d9f5e 968
SquirrelGod 2:99b1cb0d9f5e 969 /*@}*/ /* end of group CMSIS_TPI */
SquirrelGod 2:99b1cb0d9f5e 970
SquirrelGod 2:99b1cb0d9f5e 971
SquirrelGod 2:99b1cb0d9f5e 972 #if (__MPU_PRESENT == 1)
SquirrelGod 2:99b1cb0d9f5e 973 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 974 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
SquirrelGod 2:99b1cb0d9f5e 975 \brief Type definitions for the Memory Protection Unit (MPU)
SquirrelGod 2:99b1cb0d9f5e 976 @{
SquirrelGod 2:99b1cb0d9f5e 977 */
SquirrelGod 2:99b1cb0d9f5e 978
SquirrelGod 2:99b1cb0d9f5e 979 /** \brief Structure type to access the Memory Protection Unit (MPU).
SquirrelGod 2:99b1cb0d9f5e 980 */
SquirrelGod 2:99b1cb0d9f5e 981 typedef struct
SquirrelGod 2:99b1cb0d9f5e 982 {
SquirrelGod 2:99b1cb0d9f5e 983 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
SquirrelGod 2:99b1cb0d9f5e 984 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
SquirrelGod 2:99b1cb0d9f5e 985 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
SquirrelGod 2:99b1cb0d9f5e 986 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
SquirrelGod 2:99b1cb0d9f5e 987 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
SquirrelGod 2:99b1cb0d9f5e 988 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
SquirrelGod 2:99b1cb0d9f5e 989 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
SquirrelGod 2:99b1cb0d9f5e 990 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
SquirrelGod 2:99b1cb0d9f5e 991 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
SquirrelGod 2:99b1cb0d9f5e 992 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
SquirrelGod 2:99b1cb0d9f5e 993 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
SquirrelGod 2:99b1cb0d9f5e 994 } MPU_Type;
SquirrelGod 2:99b1cb0d9f5e 995
SquirrelGod 2:99b1cb0d9f5e 996 /* MPU Type Register */
SquirrelGod 2:99b1cb0d9f5e 997 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
SquirrelGod 2:99b1cb0d9f5e 998 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
SquirrelGod 2:99b1cb0d9f5e 999
SquirrelGod 2:99b1cb0d9f5e 1000 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
SquirrelGod 2:99b1cb0d9f5e 1001 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
SquirrelGod 2:99b1cb0d9f5e 1002
SquirrelGod 2:99b1cb0d9f5e 1003 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
SquirrelGod 2:99b1cb0d9f5e 1004 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
SquirrelGod 2:99b1cb0d9f5e 1005
SquirrelGod 2:99b1cb0d9f5e 1006 /* MPU Control Register */
SquirrelGod 2:99b1cb0d9f5e 1007 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
SquirrelGod 2:99b1cb0d9f5e 1008 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
SquirrelGod 2:99b1cb0d9f5e 1009
SquirrelGod 2:99b1cb0d9f5e 1010 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
SquirrelGod 2:99b1cb0d9f5e 1011 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
SquirrelGod 2:99b1cb0d9f5e 1012
SquirrelGod 2:99b1cb0d9f5e 1013 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
SquirrelGod 2:99b1cb0d9f5e 1014 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
SquirrelGod 2:99b1cb0d9f5e 1015
SquirrelGod 2:99b1cb0d9f5e 1016 /* MPU Region Number Register */
SquirrelGod 2:99b1cb0d9f5e 1017 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
SquirrelGod 2:99b1cb0d9f5e 1018 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
SquirrelGod 2:99b1cb0d9f5e 1019
SquirrelGod 2:99b1cb0d9f5e 1020 /* MPU Region Base Address Register */
SquirrelGod 2:99b1cb0d9f5e 1021 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
SquirrelGod 2:99b1cb0d9f5e 1022 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
SquirrelGod 2:99b1cb0d9f5e 1023
SquirrelGod 2:99b1cb0d9f5e 1024 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
SquirrelGod 2:99b1cb0d9f5e 1025 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
SquirrelGod 2:99b1cb0d9f5e 1026
SquirrelGod 2:99b1cb0d9f5e 1027 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
SquirrelGod 2:99b1cb0d9f5e 1028 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
SquirrelGod 2:99b1cb0d9f5e 1029
SquirrelGod 2:99b1cb0d9f5e 1030 /* MPU Region Attribute and Size Register */
SquirrelGod 2:99b1cb0d9f5e 1031 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
SquirrelGod 2:99b1cb0d9f5e 1032 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
SquirrelGod 2:99b1cb0d9f5e 1033
SquirrelGod 2:99b1cb0d9f5e 1034 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
SquirrelGod 2:99b1cb0d9f5e 1035 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
SquirrelGod 2:99b1cb0d9f5e 1036
SquirrelGod 2:99b1cb0d9f5e 1037 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
SquirrelGod 2:99b1cb0d9f5e 1038 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
SquirrelGod 2:99b1cb0d9f5e 1039
SquirrelGod 2:99b1cb0d9f5e 1040 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
SquirrelGod 2:99b1cb0d9f5e 1041 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
SquirrelGod 2:99b1cb0d9f5e 1042
SquirrelGod 2:99b1cb0d9f5e 1043 /*@} end of group CMSIS_MPU */
SquirrelGod 2:99b1cb0d9f5e 1044 #endif
SquirrelGod 2:99b1cb0d9f5e 1045
SquirrelGod 2:99b1cb0d9f5e 1046
SquirrelGod 2:99b1cb0d9f5e 1047 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 1048 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
SquirrelGod 2:99b1cb0d9f5e 1049 \brief Type definitions for the Core Debug Registers
SquirrelGod 2:99b1cb0d9f5e 1050 @{
SquirrelGod 2:99b1cb0d9f5e 1051 */
SquirrelGod 2:99b1cb0d9f5e 1052
SquirrelGod 2:99b1cb0d9f5e 1053 /** \brief Structure type to access the Core Debug Register (CoreDebug).
SquirrelGod 2:99b1cb0d9f5e 1054 */
SquirrelGod 2:99b1cb0d9f5e 1055 typedef struct
SquirrelGod 2:99b1cb0d9f5e 1056 {
SquirrelGod 2:99b1cb0d9f5e 1057 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
SquirrelGod 2:99b1cb0d9f5e 1058 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
SquirrelGod 2:99b1cb0d9f5e 1059 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
SquirrelGod 2:99b1cb0d9f5e 1060 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
SquirrelGod 2:99b1cb0d9f5e 1061 } CoreDebug_Type;
SquirrelGod 2:99b1cb0d9f5e 1062
SquirrelGod 2:99b1cb0d9f5e 1063 /* Debug Halting Control and Status Register */
SquirrelGod 2:99b1cb0d9f5e 1064 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
SquirrelGod 2:99b1cb0d9f5e 1065 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
SquirrelGod 2:99b1cb0d9f5e 1066
SquirrelGod 2:99b1cb0d9f5e 1067 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
SquirrelGod 2:99b1cb0d9f5e 1068 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
SquirrelGod 2:99b1cb0d9f5e 1069
SquirrelGod 2:99b1cb0d9f5e 1070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
SquirrelGod 2:99b1cb0d9f5e 1071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
SquirrelGod 2:99b1cb0d9f5e 1072
SquirrelGod 2:99b1cb0d9f5e 1073 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
SquirrelGod 2:99b1cb0d9f5e 1074 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
SquirrelGod 2:99b1cb0d9f5e 1075
SquirrelGod 2:99b1cb0d9f5e 1076 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
SquirrelGod 2:99b1cb0d9f5e 1077 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
SquirrelGod 2:99b1cb0d9f5e 1078
SquirrelGod 2:99b1cb0d9f5e 1079 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
SquirrelGod 2:99b1cb0d9f5e 1080 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
SquirrelGod 2:99b1cb0d9f5e 1081
SquirrelGod 2:99b1cb0d9f5e 1082 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
SquirrelGod 2:99b1cb0d9f5e 1083 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
SquirrelGod 2:99b1cb0d9f5e 1084
SquirrelGod 2:99b1cb0d9f5e 1085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
SquirrelGod 2:99b1cb0d9f5e 1086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
SquirrelGod 2:99b1cb0d9f5e 1087
SquirrelGod 2:99b1cb0d9f5e 1088 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
SquirrelGod 2:99b1cb0d9f5e 1089 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
SquirrelGod 2:99b1cb0d9f5e 1090
SquirrelGod 2:99b1cb0d9f5e 1091 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
SquirrelGod 2:99b1cb0d9f5e 1092 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
SquirrelGod 2:99b1cb0d9f5e 1093
SquirrelGod 2:99b1cb0d9f5e 1094 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
SquirrelGod 2:99b1cb0d9f5e 1095 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
SquirrelGod 2:99b1cb0d9f5e 1096
SquirrelGod 2:99b1cb0d9f5e 1097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
SquirrelGod 2:99b1cb0d9f5e 1098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
SquirrelGod 2:99b1cb0d9f5e 1099
SquirrelGod 2:99b1cb0d9f5e 1100 /* Debug Core Register Selector Register */
SquirrelGod 2:99b1cb0d9f5e 1101 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
SquirrelGod 2:99b1cb0d9f5e 1102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
SquirrelGod 2:99b1cb0d9f5e 1103
SquirrelGod 2:99b1cb0d9f5e 1104 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
SquirrelGod 2:99b1cb0d9f5e 1105 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
SquirrelGod 2:99b1cb0d9f5e 1106
SquirrelGod 2:99b1cb0d9f5e 1107 /* Debug Exception and Monitor Control Register */
SquirrelGod 2:99b1cb0d9f5e 1108 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
SquirrelGod 2:99b1cb0d9f5e 1109 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
SquirrelGod 2:99b1cb0d9f5e 1110
SquirrelGod 2:99b1cb0d9f5e 1111 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
SquirrelGod 2:99b1cb0d9f5e 1112 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
SquirrelGod 2:99b1cb0d9f5e 1113
SquirrelGod 2:99b1cb0d9f5e 1114 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
SquirrelGod 2:99b1cb0d9f5e 1115 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
SquirrelGod 2:99b1cb0d9f5e 1116
SquirrelGod 2:99b1cb0d9f5e 1117 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
SquirrelGod 2:99b1cb0d9f5e 1118 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
SquirrelGod 2:99b1cb0d9f5e 1119
SquirrelGod 2:99b1cb0d9f5e 1120 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
SquirrelGod 2:99b1cb0d9f5e 1121 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
SquirrelGod 2:99b1cb0d9f5e 1122
SquirrelGod 2:99b1cb0d9f5e 1123 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
SquirrelGod 2:99b1cb0d9f5e 1124 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1125
SquirrelGod 2:99b1cb0d9f5e 1126 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
SquirrelGod 2:99b1cb0d9f5e 1127 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1128
SquirrelGod 2:99b1cb0d9f5e 1129 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
SquirrelGod 2:99b1cb0d9f5e 1130 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1131
SquirrelGod 2:99b1cb0d9f5e 1132 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
SquirrelGod 2:99b1cb0d9f5e 1133 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1134
SquirrelGod 2:99b1cb0d9f5e 1135 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
SquirrelGod 2:99b1cb0d9f5e 1136 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1137
SquirrelGod 2:99b1cb0d9f5e 1138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
SquirrelGod 2:99b1cb0d9f5e 1139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1140
SquirrelGod 2:99b1cb0d9f5e 1141 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
SquirrelGod 2:99b1cb0d9f5e 1142 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
SquirrelGod 2:99b1cb0d9f5e 1143
SquirrelGod 2:99b1cb0d9f5e 1144 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
SquirrelGod 2:99b1cb0d9f5e 1145 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
SquirrelGod 2:99b1cb0d9f5e 1146
SquirrelGod 2:99b1cb0d9f5e 1147 /*@} end of group CMSIS_CoreDebug */
SquirrelGod 2:99b1cb0d9f5e 1148
SquirrelGod 2:99b1cb0d9f5e 1149
SquirrelGod 2:99b1cb0d9f5e 1150 /** \ingroup CMSIS_core_register
SquirrelGod 2:99b1cb0d9f5e 1151 \defgroup CMSIS_core_base Core Definitions
SquirrelGod 2:99b1cb0d9f5e 1152 \brief Definitions for base addresses, unions, and structures.
SquirrelGod 2:99b1cb0d9f5e 1153 @{
SquirrelGod 2:99b1cb0d9f5e 1154 */
SquirrelGod 2:99b1cb0d9f5e 1155
SquirrelGod 2:99b1cb0d9f5e 1156 /* Memory mapping of Cortex-M3 Hardware */
SquirrelGod 2:99b1cb0d9f5e 1157 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
SquirrelGod 2:99b1cb0d9f5e 1158 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
SquirrelGod 2:99b1cb0d9f5e 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
SquirrelGod 2:99b1cb0d9f5e 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
SquirrelGod 2:99b1cb0d9f5e 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
SquirrelGod 2:99b1cb0d9f5e 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
SquirrelGod 2:99b1cb0d9f5e 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
SquirrelGod 2:99b1cb0d9f5e 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
SquirrelGod 2:99b1cb0d9f5e 1165
SquirrelGod 2:99b1cb0d9f5e 1166 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
SquirrelGod 2:99b1cb0d9f5e 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1170 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1171 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1172 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1173 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
SquirrelGod 2:99b1cb0d9f5e 1174
SquirrelGod 2:99b1cb0d9f5e 1175 #if (__MPU_PRESENT == 1)
SquirrelGod 2:99b1cb0d9f5e 1176 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
SquirrelGod 2:99b1cb0d9f5e 1177 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
SquirrelGod 2:99b1cb0d9f5e 1178 #endif
SquirrelGod 2:99b1cb0d9f5e 1179
SquirrelGod 2:99b1cb0d9f5e 1180 /*@} */
SquirrelGod 2:99b1cb0d9f5e 1181
SquirrelGod 2:99b1cb0d9f5e 1182
SquirrelGod 2:99b1cb0d9f5e 1183
SquirrelGod 2:99b1cb0d9f5e 1184 /*******************************************************************************
SquirrelGod 2:99b1cb0d9f5e 1185 * Hardware Abstraction Layer
SquirrelGod 2:99b1cb0d9f5e 1186 Core Function Interface contains:
SquirrelGod 2:99b1cb0d9f5e 1187 - Core NVIC Functions
SquirrelGod 2:99b1cb0d9f5e 1188 - Core SysTick Functions
SquirrelGod 2:99b1cb0d9f5e 1189 - Core Debug Functions
SquirrelGod 2:99b1cb0d9f5e 1190 - Core Register Access Functions
SquirrelGod 2:99b1cb0d9f5e 1191 ******************************************************************************/
SquirrelGod 2:99b1cb0d9f5e 1192 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
SquirrelGod 2:99b1cb0d9f5e 1193 */
SquirrelGod 2:99b1cb0d9f5e 1194
SquirrelGod 2:99b1cb0d9f5e 1195
SquirrelGod 2:99b1cb0d9f5e 1196
SquirrelGod 2:99b1cb0d9f5e 1197 /* ########################## NVIC functions #################################### */
SquirrelGod 2:99b1cb0d9f5e 1198 /** \ingroup CMSIS_Core_FunctionInterface
SquirrelGod 2:99b1cb0d9f5e 1199 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
SquirrelGod 2:99b1cb0d9f5e 1200 \brief Functions that manage interrupts and exceptions via the NVIC.
SquirrelGod 2:99b1cb0d9f5e 1201 @{
SquirrelGod 2:99b1cb0d9f5e 1202 */
SquirrelGod 2:99b1cb0d9f5e 1203
SquirrelGod 2:99b1cb0d9f5e 1204 /** \brief Set Priority Grouping
SquirrelGod 2:99b1cb0d9f5e 1205
SquirrelGod 2:99b1cb0d9f5e 1206 The function sets the priority grouping field using the required unlock sequence.
SquirrelGod 2:99b1cb0d9f5e 1207 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
SquirrelGod 2:99b1cb0d9f5e 1208 Only values from 0..7 are used.
SquirrelGod 2:99b1cb0d9f5e 1209 In case of a conflict between priority grouping and available
SquirrelGod 2:99b1cb0d9f5e 1210 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
SquirrelGod 2:99b1cb0d9f5e 1211
SquirrelGod 2:99b1cb0d9f5e 1212 \param [in] PriorityGroup Priority grouping field.
SquirrelGod 2:99b1cb0d9f5e 1213 */
SquirrelGod 2:99b1cb0d9f5e 1214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
SquirrelGod 2:99b1cb0d9f5e 1215 {
SquirrelGod 2:99b1cb0d9f5e 1216 uint32_t reg_value;
SquirrelGod 2:99b1cb0d9f5e 1217 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
SquirrelGod 2:99b1cb0d9f5e 1218
SquirrelGod 2:99b1cb0d9f5e 1219 reg_value = SCB->AIRCR; /* read old register configuration */
SquirrelGod 2:99b1cb0d9f5e 1220 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
SquirrelGod 2:99b1cb0d9f5e 1221 reg_value = (reg_value |
SquirrelGod 2:99b1cb0d9f5e 1222 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SquirrelGod 2:99b1cb0d9f5e 1223 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SquirrelGod 2:99b1cb0d9f5e 1224 SCB->AIRCR = reg_value;
SquirrelGod 2:99b1cb0d9f5e 1225 }
SquirrelGod 2:99b1cb0d9f5e 1226
SquirrelGod 2:99b1cb0d9f5e 1227
SquirrelGod 2:99b1cb0d9f5e 1228 /** \brief Get Priority Grouping
SquirrelGod 2:99b1cb0d9f5e 1229
SquirrelGod 2:99b1cb0d9f5e 1230 The function reads the priority grouping field from the NVIC Interrupt Controller.
SquirrelGod 2:99b1cb0d9f5e 1231
SquirrelGod 2:99b1cb0d9f5e 1232 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
SquirrelGod 2:99b1cb0d9f5e 1233 */
SquirrelGod 2:99b1cb0d9f5e 1234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
SquirrelGod 2:99b1cb0d9f5e 1235 {
SquirrelGod 2:99b1cb0d9f5e 1236 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
SquirrelGod 2:99b1cb0d9f5e 1237 }
SquirrelGod 2:99b1cb0d9f5e 1238
SquirrelGod 2:99b1cb0d9f5e 1239
SquirrelGod 2:99b1cb0d9f5e 1240 /** \brief Enable External Interrupt
SquirrelGod 2:99b1cb0d9f5e 1241
SquirrelGod 2:99b1cb0d9f5e 1242 The function enables a device-specific interrupt in the NVIC interrupt controller.
SquirrelGod 2:99b1cb0d9f5e 1243
SquirrelGod 2:99b1cb0d9f5e 1244 \param [in] IRQn External interrupt number. Value cannot be negative.
SquirrelGod 2:99b1cb0d9f5e 1245 */
SquirrelGod 2:99b1cb0d9f5e 1246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1247 {
SquirrelGod 2:99b1cb0d9f5e 1248 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
SquirrelGod 2:99b1cb0d9f5e 1249 }
SquirrelGod 2:99b1cb0d9f5e 1250
SquirrelGod 2:99b1cb0d9f5e 1251
SquirrelGod 2:99b1cb0d9f5e 1252 /** \brief Disable External Interrupt
SquirrelGod 2:99b1cb0d9f5e 1253
SquirrelGod 2:99b1cb0d9f5e 1254 The function disables a device-specific interrupt in the NVIC interrupt controller.
SquirrelGod 2:99b1cb0d9f5e 1255
SquirrelGod 2:99b1cb0d9f5e 1256 \param [in] IRQn External interrupt number. Value cannot be negative.
SquirrelGod 2:99b1cb0d9f5e 1257 */
SquirrelGod 2:99b1cb0d9f5e 1258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1259 {
SquirrelGod 2:99b1cb0d9f5e 1260 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
SquirrelGod 2:99b1cb0d9f5e 1261 }
SquirrelGod 2:99b1cb0d9f5e 1262
SquirrelGod 2:99b1cb0d9f5e 1263
SquirrelGod 2:99b1cb0d9f5e 1264 /** \brief Get Pending Interrupt
SquirrelGod 2:99b1cb0d9f5e 1265
SquirrelGod 2:99b1cb0d9f5e 1266 The function reads the pending register in the NVIC and returns the pending bit
SquirrelGod 2:99b1cb0d9f5e 1267 for the specified interrupt.
SquirrelGod 2:99b1cb0d9f5e 1268
SquirrelGod 2:99b1cb0d9f5e 1269 \param [in] IRQn Interrupt number.
SquirrelGod 2:99b1cb0d9f5e 1270
SquirrelGod 2:99b1cb0d9f5e 1271 \return 0 Interrupt status is not pending.
SquirrelGod 2:99b1cb0d9f5e 1272 \return 1 Interrupt status is pending.
SquirrelGod 2:99b1cb0d9f5e 1273 */
SquirrelGod 2:99b1cb0d9f5e 1274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1275 {
SquirrelGod 2:99b1cb0d9f5e 1276 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
SquirrelGod 2:99b1cb0d9f5e 1277 }
SquirrelGod 2:99b1cb0d9f5e 1278
SquirrelGod 2:99b1cb0d9f5e 1279
SquirrelGod 2:99b1cb0d9f5e 1280 /** \brief Set Pending Interrupt
SquirrelGod 2:99b1cb0d9f5e 1281
SquirrelGod 2:99b1cb0d9f5e 1282 The function sets the pending bit of an external interrupt.
SquirrelGod 2:99b1cb0d9f5e 1283
SquirrelGod 2:99b1cb0d9f5e 1284 \param [in] IRQn Interrupt number. Value cannot be negative.
SquirrelGod 2:99b1cb0d9f5e 1285 */
SquirrelGod 2:99b1cb0d9f5e 1286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1287 {
SquirrelGod 2:99b1cb0d9f5e 1288 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
SquirrelGod 2:99b1cb0d9f5e 1289 }
SquirrelGod 2:99b1cb0d9f5e 1290
SquirrelGod 2:99b1cb0d9f5e 1291
SquirrelGod 2:99b1cb0d9f5e 1292 /** \brief Clear Pending Interrupt
SquirrelGod 2:99b1cb0d9f5e 1293
SquirrelGod 2:99b1cb0d9f5e 1294 The function clears the pending bit of an external interrupt.
SquirrelGod 2:99b1cb0d9f5e 1295
SquirrelGod 2:99b1cb0d9f5e 1296 \param [in] IRQn External interrupt number. Value cannot be negative.
SquirrelGod 2:99b1cb0d9f5e 1297 */
SquirrelGod 2:99b1cb0d9f5e 1298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1299 {
SquirrelGod 2:99b1cb0d9f5e 1300 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
SquirrelGod 2:99b1cb0d9f5e 1301 }
SquirrelGod 2:99b1cb0d9f5e 1302
SquirrelGod 2:99b1cb0d9f5e 1303
SquirrelGod 2:99b1cb0d9f5e 1304 /** \brief Get Active Interrupt
SquirrelGod 2:99b1cb0d9f5e 1305
SquirrelGod 2:99b1cb0d9f5e 1306 The function reads the active register in NVIC and returns the active bit.
SquirrelGod 2:99b1cb0d9f5e 1307
SquirrelGod 2:99b1cb0d9f5e 1308 \param [in] IRQn Interrupt number.
SquirrelGod 2:99b1cb0d9f5e 1309
SquirrelGod 2:99b1cb0d9f5e 1310 \return 0 Interrupt status is not active.
SquirrelGod 2:99b1cb0d9f5e 1311 \return 1 Interrupt status is active.
SquirrelGod 2:99b1cb0d9f5e 1312 */
SquirrelGod 2:99b1cb0d9f5e 1313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1314 {
SquirrelGod 2:99b1cb0d9f5e 1315 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
SquirrelGod 2:99b1cb0d9f5e 1316 }
SquirrelGod 2:99b1cb0d9f5e 1317
SquirrelGod 2:99b1cb0d9f5e 1318
SquirrelGod 2:99b1cb0d9f5e 1319 /** \brief Set Interrupt Priority
SquirrelGod 2:99b1cb0d9f5e 1320
SquirrelGod 2:99b1cb0d9f5e 1321 The function sets the priority of an interrupt.
SquirrelGod 2:99b1cb0d9f5e 1322
SquirrelGod 2:99b1cb0d9f5e 1323 \note The priority cannot be set for every core interrupt.
SquirrelGod 2:99b1cb0d9f5e 1324
SquirrelGod 2:99b1cb0d9f5e 1325 \param [in] IRQn Interrupt number.
SquirrelGod 2:99b1cb0d9f5e 1326 \param [in] priority Priority to set.
SquirrelGod 2:99b1cb0d9f5e 1327 */
SquirrelGod 2:99b1cb0d9f5e 1328 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
SquirrelGod 2:99b1cb0d9f5e 1329 {
SquirrelGod 2:99b1cb0d9f5e 1330 if(IRQn < 0) {
SquirrelGod 2:99b1cb0d9f5e 1331 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
SquirrelGod 2:99b1cb0d9f5e 1332 else {
SquirrelGod 2:99b1cb0d9f5e 1333 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
SquirrelGod 2:99b1cb0d9f5e 1334 }
SquirrelGod 2:99b1cb0d9f5e 1335
SquirrelGod 2:99b1cb0d9f5e 1336
SquirrelGod 2:99b1cb0d9f5e 1337 /** \brief Get Interrupt Priority
SquirrelGod 2:99b1cb0d9f5e 1338
SquirrelGod 2:99b1cb0d9f5e 1339 The function reads the priority of an interrupt. The interrupt
SquirrelGod 2:99b1cb0d9f5e 1340 number can be positive to specify an external (device specific)
SquirrelGod 2:99b1cb0d9f5e 1341 interrupt, or negative to specify an internal (core) interrupt.
SquirrelGod 2:99b1cb0d9f5e 1342
SquirrelGod 2:99b1cb0d9f5e 1343
SquirrelGod 2:99b1cb0d9f5e 1344 \param [in] IRQn Interrupt number.
SquirrelGod 2:99b1cb0d9f5e 1345 \return Interrupt Priority. Value is aligned automatically to the implemented
SquirrelGod 2:99b1cb0d9f5e 1346 priority bits of the microcontroller.
SquirrelGod 2:99b1cb0d9f5e 1347 */
SquirrelGod 2:99b1cb0d9f5e 1348 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
SquirrelGod 2:99b1cb0d9f5e 1349 {
SquirrelGod 2:99b1cb0d9f5e 1350
SquirrelGod 2:99b1cb0d9f5e 1351 if(IRQn < 0) {
SquirrelGod 2:99b1cb0d9f5e 1352 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
SquirrelGod 2:99b1cb0d9f5e 1353 else {
SquirrelGod 2:99b1cb0d9f5e 1354 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
SquirrelGod 2:99b1cb0d9f5e 1355 }
SquirrelGod 2:99b1cb0d9f5e 1356
SquirrelGod 2:99b1cb0d9f5e 1357
SquirrelGod 2:99b1cb0d9f5e 1358 /** \brief Encode Priority
SquirrelGod 2:99b1cb0d9f5e 1359
SquirrelGod 2:99b1cb0d9f5e 1360 The function encodes the priority for an interrupt with the given priority group,
SquirrelGod 2:99b1cb0d9f5e 1361 preemptive priority value, and subpriority value.
SquirrelGod 2:99b1cb0d9f5e 1362 In case of a conflict between priority grouping and available
SquirrelGod 2:99b1cb0d9f5e 1363 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
SquirrelGod 2:99b1cb0d9f5e 1364
SquirrelGod 2:99b1cb0d9f5e 1365 \param [in] PriorityGroup Used priority group.
SquirrelGod 2:99b1cb0d9f5e 1366 \param [in] PreemptPriority Preemptive priority value (starting from 0).
SquirrelGod 2:99b1cb0d9f5e 1367 \param [in] SubPriority Subpriority value (starting from 0).
SquirrelGod 2:99b1cb0d9f5e 1368 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
SquirrelGod 2:99b1cb0d9f5e 1369 */
SquirrelGod 2:99b1cb0d9f5e 1370 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
SquirrelGod 2:99b1cb0d9f5e 1371 {
SquirrelGod 2:99b1cb0d9f5e 1372 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
SquirrelGod 2:99b1cb0d9f5e 1373 uint32_t PreemptPriorityBits;
SquirrelGod 2:99b1cb0d9f5e 1374 uint32_t SubPriorityBits;
SquirrelGod 2:99b1cb0d9f5e 1375
SquirrelGod 2:99b1cb0d9f5e 1376 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SquirrelGod 2:99b1cb0d9f5e 1377 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
SquirrelGod 2:99b1cb0d9f5e 1378
SquirrelGod 2:99b1cb0d9f5e 1379 return (
SquirrelGod 2:99b1cb0d9f5e 1380 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
SquirrelGod 2:99b1cb0d9f5e 1381 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
SquirrelGod 2:99b1cb0d9f5e 1382 );
SquirrelGod 2:99b1cb0d9f5e 1383 }
SquirrelGod 2:99b1cb0d9f5e 1384
SquirrelGod 2:99b1cb0d9f5e 1385
SquirrelGod 2:99b1cb0d9f5e 1386 /** \brief Decode Priority
SquirrelGod 2:99b1cb0d9f5e 1387
SquirrelGod 2:99b1cb0d9f5e 1388 The function decodes an interrupt priority value with a given priority group to
SquirrelGod 2:99b1cb0d9f5e 1389 preemptive priority value and subpriority value.
SquirrelGod 2:99b1cb0d9f5e 1390 In case of a conflict between priority grouping and available
SquirrelGod 2:99b1cb0d9f5e 1391 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
SquirrelGod 2:99b1cb0d9f5e 1392
SquirrelGod 2:99b1cb0d9f5e 1393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
SquirrelGod 2:99b1cb0d9f5e 1394 \param [in] PriorityGroup Used priority group.
SquirrelGod 2:99b1cb0d9f5e 1395 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
SquirrelGod 2:99b1cb0d9f5e 1396 \param [out] pSubPriority Subpriority value (starting from 0).
SquirrelGod 2:99b1cb0d9f5e 1397 */
SquirrelGod 2:99b1cb0d9f5e 1398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
SquirrelGod 2:99b1cb0d9f5e 1399 {
SquirrelGod 2:99b1cb0d9f5e 1400 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
SquirrelGod 2:99b1cb0d9f5e 1401 uint32_t PreemptPriorityBits;
SquirrelGod 2:99b1cb0d9f5e 1402 uint32_t SubPriorityBits;
SquirrelGod 2:99b1cb0d9f5e 1403
SquirrelGod 2:99b1cb0d9f5e 1404 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SquirrelGod 2:99b1cb0d9f5e 1405 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
SquirrelGod 2:99b1cb0d9f5e 1406
SquirrelGod 2:99b1cb0d9f5e 1407 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
SquirrelGod 2:99b1cb0d9f5e 1408 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
SquirrelGod 2:99b1cb0d9f5e 1409 }
SquirrelGod 2:99b1cb0d9f5e 1410
SquirrelGod 2:99b1cb0d9f5e 1411
SquirrelGod 2:99b1cb0d9f5e 1412 /** \brief System Reset
SquirrelGod 2:99b1cb0d9f5e 1413
SquirrelGod 2:99b1cb0d9f5e 1414 The function initiates a system reset request to reset the MCU.
SquirrelGod 2:99b1cb0d9f5e 1415 */
SquirrelGod 2:99b1cb0d9f5e 1416 __STATIC_INLINE void NVIC_SystemReset(void)
SquirrelGod 2:99b1cb0d9f5e 1417 {
SquirrelGod 2:99b1cb0d9f5e 1418 __DSB(); /* Ensure all outstanding memory accesses included
SquirrelGod 2:99b1cb0d9f5e 1419 buffered write are completed before reset */
SquirrelGod 2:99b1cb0d9f5e 1420 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SquirrelGod 2:99b1cb0d9f5e 1421 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SquirrelGod 2:99b1cb0d9f5e 1422 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
SquirrelGod 2:99b1cb0d9f5e 1423 __DSB(); /* Ensure completion of memory access */
SquirrelGod 2:99b1cb0d9f5e 1424 while(1); /* wait until reset */
SquirrelGod 2:99b1cb0d9f5e 1425 }
SquirrelGod 2:99b1cb0d9f5e 1426
SquirrelGod 2:99b1cb0d9f5e 1427 /*@} end of CMSIS_Core_NVICFunctions */
SquirrelGod 2:99b1cb0d9f5e 1428
SquirrelGod 2:99b1cb0d9f5e 1429
SquirrelGod 2:99b1cb0d9f5e 1430
SquirrelGod 2:99b1cb0d9f5e 1431 /* ################################## SysTick function ############################################ */
SquirrelGod 2:99b1cb0d9f5e 1432 /** \ingroup CMSIS_Core_FunctionInterface
SquirrelGod 2:99b1cb0d9f5e 1433 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
SquirrelGod 2:99b1cb0d9f5e 1434 \brief Functions that configure the System.
SquirrelGod 2:99b1cb0d9f5e 1435 @{
SquirrelGod 2:99b1cb0d9f5e 1436 */
SquirrelGod 2:99b1cb0d9f5e 1437
SquirrelGod 2:99b1cb0d9f5e 1438 #if (__Vendor_SysTickConfig == 0)
SquirrelGod 2:99b1cb0d9f5e 1439
SquirrelGod 2:99b1cb0d9f5e 1440 /** \brief System Tick Configuration
SquirrelGod 2:99b1cb0d9f5e 1441
SquirrelGod 2:99b1cb0d9f5e 1442 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
SquirrelGod 2:99b1cb0d9f5e 1443 Counter is in free running mode to generate periodic interrupts.
SquirrelGod 2:99b1cb0d9f5e 1444
SquirrelGod 2:99b1cb0d9f5e 1445 \param [in] ticks Number of ticks between two interrupts.
SquirrelGod 2:99b1cb0d9f5e 1446
SquirrelGod 2:99b1cb0d9f5e 1447 \return 0 Function succeeded.
SquirrelGod 2:99b1cb0d9f5e 1448 \return 1 Function failed.
SquirrelGod 2:99b1cb0d9f5e 1449
SquirrelGod 2:99b1cb0d9f5e 1450 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
SquirrelGod 2:99b1cb0d9f5e 1451 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
SquirrelGod 2:99b1cb0d9f5e 1452 must contain a vendor-specific implementation of this function.
SquirrelGod 2:99b1cb0d9f5e 1453
SquirrelGod 2:99b1cb0d9f5e 1454 */
SquirrelGod 2:99b1cb0d9f5e 1455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
SquirrelGod 2:99b1cb0d9f5e 1456 {
SquirrelGod 2:99b1cb0d9f5e 1457 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SquirrelGod 2:99b1cb0d9f5e 1458
SquirrelGod 2:99b1cb0d9f5e 1459 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SquirrelGod 2:99b1cb0d9f5e 1460 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SquirrelGod 2:99b1cb0d9f5e 1461 SysTick->VAL = 0; /* Load the SysTick Counter Value */
SquirrelGod 2:99b1cb0d9f5e 1462 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SquirrelGod 2:99b1cb0d9f5e 1463 SysTick_CTRL_TICKINT_Msk |
SquirrelGod 2:99b1cb0d9f5e 1464 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SquirrelGod 2:99b1cb0d9f5e 1465 return (0); /* Function successful */
SquirrelGod 2:99b1cb0d9f5e 1466 }
SquirrelGod 2:99b1cb0d9f5e 1467
SquirrelGod 2:99b1cb0d9f5e 1468 #endif
SquirrelGod 2:99b1cb0d9f5e 1469
SquirrelGod 2:99b1cb0d9f5e 1470 /*@} end of CMSIS_Core_SysTickFunctions */
SquirrelGod 2:99b1cb0d9f5e 1471
SquirrelGod 2:99b1cb0d9f5e 1472
SquirrelGod 2:99b1cb0d9f5e 1473
SquirrelGod 2:99b1cb0d9f5e 1474 /* ##################################### Debug In/Output function ########################################### */
SquirrelGod 2:99b1cb0d9f5e 1475 /** \ingroup CMSIS_Core_FunctionInterface
SquirrelGod 2:99b1cb0d9f5e 1476 \defgroup CMSIS_core_DebugFunctions ITM Functions
SquirrelGod 2:99b1cb0d9f5e 1477 \brief Functions that access the ITM debug interface.
SquirrelGod 2:99b1cb0d9f5e 1478 @{
SquirrelGod 2:99b1cb0d9f5e 1479 */
SquirrelGod 2:99b1cb0d9f5e 1480
SquirrelGod 2:99b1cb0d9f5e 1481 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
SquirrelGod 2:99b1cb0d9f5e 1482 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
SquirrelGod 2:99b1cb0d9f5e 1483
SquirrelGod 2:99b1cb0d9f5e 1484
SquirrelGod 2:99b1cb0d9f5e 1485 /** \brief ITM Send Character
SquirrelGod 2:99b1cb0d9f5e 1486
SquirrelGod 2:99b1cb0d9f5e 1487 The function transmits a character via the ITM channel 0, and
SquirrelGod 2:99b1cb0d9f5e 1488 \li Just returns when no debugger is connected that has booked the output.
SquirrelGod 2:99b1cb0d9f5e 1489 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
SquirrelGod 2:99b1cb0d9f5e 1490
SquirrelGod 2:99b1cb0d9f5e 1491 \param [in] ch Character to transmit.
SquirrelGod 2:99b1cb0d9f5e 1492
SquirrelGod 2:99b1cb0d9f5e 1493 \returns Character to transmit.
SquirrelGod 2:99b1cb0d9f5e 1494 */
SquirrelGod 2:99b1cb0d9f5e 1495 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
SquirrelGod 2:99b1cb0d9f5e 1496 {
SquirrelGod 2:99b1cb0d9f5e 1497 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
SquirrelGod 2:99b1cb0d9f5e 1498 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
SquirrelGod 2:99b1cb0d9f5e 1499 {
SquirrelGod 2:99b1cb0d9f5e 1500 while (ITM->PORT[0].u32 == 0);
SquirrelGod 2:99b1cb0d9f5e 1501 ITM->PORT[0].u8 = (uint8_t) ch;
SquirrelGod 2:99b1cb0d9f5e 1502 }
SquirrelGod 2:99b1cb0d9f5e 1503 return (ch);
SquirrelGod 2:99b1cb0d9f5e 1504 }
SquirrelGod 2:99b1cb0d9f5e 1505
SquirrelGod 2:99b1cb0d9f5e 1506
SquirrelGod 2:99b1cb0d9f5e 1507 /** \brief ITM Receive Character
SquirrelGod 2:99b1cb0d9f5e 1508
SquirrelGod 2:99b1cb0d9f5e 1509 The function inputs a character via the external variable \ref ITM_RxBuffer.
SquirrelGod 2:99b1cb0d9f5e 1510
SquirrelGod 2:99b1cb0d9f5e 1511 \return Received character.
SquirrelGod 2:99b1cb0d9f5e 1512 \return -1 No character pending.
SquirrelGod 2:99b1cb0d9f5e 1513 */
SquirrelGod 2:99b1cb0d9f5e 1514 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
SquirrelGod 2:99b1cb0d9f5e 1515 int32_t ch = -1; /* no character available */
SquirrelGod 2:99b1cb0d9f5e 1516
SquirrelGod 2:99b1cb0d9f5e 1517 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
SquirrelGod 2:99b1cb0d9f5e 1518 ch = ITM_RxBuffer;
SquirrelGod 2:99b1cb0d9f5e 1519 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
SquirrelGod 2:99b1cb0d9f5e 1520 }
SquirrelGod 2:99b1cb0d9f5e 1521
SquirrelGod 2:99b1cb0d9f5e 1522 return (ch);
SquirrelGod 2:99b1cb0d9f5e 1523 }
SquirrelGod 2:99b1cb0d9f5e 1524
SquirrelGod 2:99b1cb0d9f5e 1525
SquirrelGod 2:99b1cb0d9f5e 1526 /** \brief ITM Check Character
SquirrelGod 2:99b1cb0d9f5e 1527
SquirrelGod 2:99b1cb0d9f5e 1528 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
SquirrelGod 2:99b1cb0d9f5e 1529
SquirrelGod 2:99b1cb0d9f5e 1530 \return 0 No character available.
SquirrelGod 2:99b1cb0d9f5e 1531 \return 1 Character available.
SquirrelGod 2:99b1cb0d9f5e 1532 */
SquirrelGod 2:99b1cb0d9f5e 1533 __STATIC_INLINE int32_t ITM_CheckChar (void) {
SquirrelGod 2:99b1cb0d9f5e 1534
SquirrelGod 2:99b1cb0d9f5e 1535 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
SquirrelGod 2:99b1cb0d9f5e 1536 return (0); /* no character available */
SquirrelGod 2:99b1cb0d9f5e 1537 } else {
SquirrelGod 2:99b1cb0d9f5e 1538 return (1); /* character available */
SquirrelGod 2:99b1cb0d9f5e 1539 }
SquirrelGod 2:99b1cb0d9f5e 1540 }
SquirrelGod 2:99b1cb0d9f5e 1541
SquirrelGod 2:99b1cb0d9f5e 1542 /*@} end of CMSIS_core_DebugFunctions */
SquirrelGod 2:99b1cb0d9f5e 1543
SquirrelGod 2:99b1cb0d9f5e 1544 #endif /* __CORE_CM3_H_DEPENDANT */
SquirrelGod 2:99b1cb0d9f5e 1545
SquirrelGod 2:99b1cb0d9f5e 1546 #endif /* __CMSIS_GENERIC */
SquirrelGod 2:99b1cb0d9f5e 1547
SquirrelGod 2:99b1cb0d9f5e 1548 #ifdef __cplusplus
SquirrelGod 2:99b1cb0d9f5e 1549 }
SquirrelGod 2:99b1cb0d9f5e 1550 #endif