CRAC Team / Utilisatio_MX12_V2

Programme d'utilisation des AX12 avec rajout de l'MX12

Fork of test_carteAToutFaire_PR by CRAC Team

mbed/LPC1768/LPC17xx.h@1:f3f702086a30, 2017-05-11 (annotated)

Committer:
ClementBreteau
Date:
Thu May 11 11:49:50 2017 +0000
Revision:
1:f3f702086a30
test de la carte ? tout faire du petit robot

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ClementBreteau 1:f3f702086a30 1 /**************************************************************************//**
ClementBreteau 1:f3f702086a30 2 * @file LPC17xx.h
ClementBreteau 1:f3f702086a30 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
ClementBreteau 1:f3f702086a30 4 * NXP LPC17xx Device Series
ClementBreteau 1:f3f702086a30 5 * @version: V1.09
ClementBreteau 1:f3f702086a30 6 * @date: 17. March 2010
ClementBreteau 1:f3f702086a30 7
ClementBreteau 1:f3f702086a30 8 *
ClementBreteau 1:f3f702086a30 9 * @note
ClementBreteau 1:f3f702086a30 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
ClementBreteau 1:f3f702086a30 11 *
ClementBreteau 1:f3f702086a30 12 * @par
ClementBreteau 1:f3f702086a30 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
ClementBreteau 1:f3f702086a30 14 * processor based microcontrollers. This file can be freely distributed
ClementBreteau 1:f3f702086a30 15 * within development tools that are supporting such ARM based processors.
ClementBreteau 1:f3f702086a30 16 *
ClementBreteau 1:f3f702086a30 17 * @par
ClementBreteau 1:f3f702086a30 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
ClementBreteau 1:f3f702086a30 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
ClementBreteau 1:f3f702086a30 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
ClementBreteau 1:f3f702086a30 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
ClementBreteau 1:f3f702086a30 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
ClementBreteau 1:f3f702086a30 23 *
ClementBreteau 1:f3f702086a30 24 ******************************************************************************/
ClementBreteau 1:f3f702086a30 25
ClementBreteau 1:f3f702086a30 26
ClementBreteau 1:f3f702086a30 27 #ifndef __LPC17xx_H__
ClementBreteau 1:f3f702086a30 28 #define __LPC17xx_H__
ClementBreteau 1:f3f702086a30 29
ClementBreteau 1:f3f702086a30 30 /*
ClementBreteau 1:f3f702086a30 31 * ==========================================================================
ClementBreteau 1:f3f702086a30 32 * ---------- Interrupt Number Definition -----------------------------------
ClementBreteau 1:f3f702086a30 33 * ==========================================================================
ClementBreteau 1:f3f702086a30 34 */
ClementBreteau 1:f3f702086a30 35
ClementBreteau 1:f3f702086a30 36 typedef enum IRQn
ClementBreteau 1:f3f702086a30 37 {
ClementBreteau 1:f3f702086a30 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
ClementBreteau 1:f3f702086a30 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ClementBreteau 1:f3f702086a30 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
ClementBreteau 1:f3f702086a30 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
ClementBreteau 1:f3f702086a30 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
ClementBreteau 1:f3f702086a30 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
ClementBreteau 1:f3f702086a30 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
ClementBreteau 1:f3f702086a30 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
ClementBreteau 1:f3f702086a30 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
ClementBreteau 1:f3f702086a30 47
ClementBreteau 1:f3f702086a30 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
ClementBreteau 1:f3f702086a30 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
ClementBreteau 1:f3f702086a30 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
ClementBreteau 1:f3f702086a30 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
ClementBreteau 1:f3f702086a30 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
ClementBreteau 1:f3f702086a30 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
ClementBreteau 1:f3f702086a30 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
ClementBreteau 1:f3f702086a30 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
ClementBreteau 1:f3f702086a30 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
ClementBreteau 1:f3f702086a30 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
ClementBreteau 1:f3f702086a30 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
ClementBreteau 1:f3f702086a30 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
ClementBreteau 1:f3f702086a30 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
ClementBreteau 1:f3f702086a30 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
ClementBreteau 1:f3f702086a30 62 SPI_IRQn = 13, /*!< SPI Interrupt */
ClementBreteau 1:f3f702086a30 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
ClementBreteau 1:f3f702086a30 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
ClementBreteau 1:f3f702086a30 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
ClementBreteau 1:f3f702086a30 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
ClementBreteau 1:f3f702086a30 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
ClementBreteau 1:f3f702086a30 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
ClementBreteau 1:f3f702086a30 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
ClementBreteau 1:f3f702086a30 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ClementBreteau 1:f3f702086a30 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
ClementBreteau 1:f3f702086a30 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
ClementBreteau 1:f3f702086a30 73 USB_IRQn = 24, /*!< USB Interrupt */
ClementBreteau 1:f3f702086a30 74 CAN_IRQn = 25, /*!< CAN Interrupt */
ClementBreteau 1:f3f702086a30 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
ClementBreteau 1:f3f702086a30 76 I2S_IRQn = 27, /*!< I2S Interrupt */
ClementBreteau 1:f3f702086a30 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
ClementBreteau 1:f3f702086a30 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
ClementBreteau 1:f3f702086a30 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
ClementBreteau 1:f3f702086a30 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
ClementBreteau 1:f3f702086a30 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
ClementBreteau 1:f3f702086a30 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
ClementBreteau 1:f3f702086a30 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
ClementBreteau 1:f3f702086a30 84 } IRQn_Type;
ClementBreteau 1:f3f702086a30 85
ClementBreteau 1:f3f702086a30 86
ClementBreteau 1:f3f702086a30 87 /*
ClementBreteau 1:f3f702086a30 88 * ==========================================================================
ClementBreteau 1:f3f702086a30 89 * ----------- Processor and Core Peripheral Section ------------------------
ClementBreteau 1:f3f702086a30 90 * ==========================================================================
ClementBreteau 1:f3f702086a30 91 */
ClementBreteau 1:f3f702086a30 92
ClementBreteau 1:f3f702086a30 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
ClementBreteau 1:f3f702086a30 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
ClementBreteau 1:f3f702086a30 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
ClementBreteau 1:f3f702086a30 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ClementBreteau 1:f3f702086a30 97
ClementBreteau 1:f3f702086a30 98
ClementBreteau 1:f3f702086a30 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
ClementBreteau 1:f3f702086a30 100 #include "system_LPC17xx.h" /* System Header */
ClementBreteau 1:f3f702086a30 101
ClementBreteau 1:f3f702086a30 102
ClementBreteau 1:f3f702086a30 103 /******************************************************************************/
ClementBreteau 1:f3f702086a30 104 /* Device Specific Peripheral registers structures */
ClementBreteau 1:f3f702086a30 105 /******************************************************************************/
ClementBreteau 1:f3f702086a30 106
ClementBreteau 1:f3f702086a30 107 #if defined ( __CC_ARM )
ClementBreteau 1:f3f702086a30 108 #pragma anon_unions
ClementBreteau 1:f3f702086a30 109 #endif
ClementBreteau 1:f3f702086a30 110
ClementBreteau 1:f3f702086a30 111 /*------------- System Control (SC) ------------------------------------------*/
ClementBreteau 1:f3f702086a30 112 typedef struct
ClementBreteau 1:f3f702086a30 113 {
ClementBreteau 1:f3f702086a30 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
ClementBreteau 1:f3f702086a30 115 uint32_t RESERVED0[31];
ClementBreteau 1:f3f702086a30 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
ClementBreteau 1:f3f702086a30 117 __IO uint32_t PLL0CFG;
ClementBreteau 1:f3f702086a30 118 __I uint32_t PLL0STAT;
ClementBreteau 1:f3f702086a30 119 __O uint32_t PLL0FEED;
ClementBreteau 1:f3f702086a30 120 uint32_t RESERVED1[4];
ClementBreteau 1:f3f702086a30 121 __IO uint32_t PLL1CON;
ClementBreteau 1:f3f702086a30 122 __IO uint32_t PLL1CFG;
ClementBreteau 1:f3f702086a30 123 __I uint32_t PLL1STAT;
ClementBreteau 1:f3f702086a30 124 __O uint32_t PLL1FEED;
ClementBreteau 1:f3f702086a30 125 uint32_t RESERVED2[4];
ClementBreteau 1:f3f702086a30 126 __IO uint32_t PCON;
ClementBreteau 1:f3f702086a30 127 __IO uint32_t PCONP;
ClementBreteau 1:f3f702086a30 128 uint32_t RESERVED3[15];
ClementBreteau 1:f3f702086a30 129 __IO uint32_t CCLKCFG;
ClementBreteau 1:f3f702086a30 130 __IO uint32_t USBCLKCFG;
ClementBreteau 1:f3f702086a30 131 __IO uint32_t CLKSRCSEL;
ClementBreteau 1:f3f702086a30 132 __IO uint32_t CANSLEEPCLR;
ClementBreteau 1:f3f702086a30 133 __IO uint32_t CANWAKEFLAGS;
ClementBreteau 1:f3f702086a30 134 uint32_t RESERVED4[10];
ClementBreteau 1:f3f702086a30 135 __IO uint32_t EXTINT; /* External Interrupts */
ClementBreteau 1:f3f702086a30 136 uint32_t RESERVED5;
ClementBreteau 1:f3f702086a30 137 __IO uint32_t EXTMODE;
ClementBreteau 1:f3f702086a30 138 __IO uint32_t EXTPOLAR;
ClementBreteau 1:f3f702086a30 139 uint32_t RESERVED6[12];
ClementBreteau 1:f3f702086a30 140 __IO uint32_t RSID; /* Reset */
ClementBreteau 1:f3f702086a30 141 uint32_t RESERVED7[7];
ClementBreteau 1:f3f702086a30 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
ClementBreteau 1:f3f702086a30 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
ClementBreteau 1:f3f702086a30 144 __IO uint32_t PCLKSEL0;
ClementBreteau 1:f3f702086a30 145 __IO uint32_t PCLKSEL1;
ClementBreteau 1:f3f702086a30 146 uint32_t RESERVED8[4];
ClementBreteau 1:f3f702086a30 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
ClementBreteau 1:f3f702086a30 148 __IO uint32_t DMAREQSEL;
ClementBreteau 1:f3f702086a30 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
ClementBreteau 1:f3f702086a30 150 } LPC_SC_TypeDef;
ClementBreteau 1:f3f702086a30 151
ClementBreteau 1:f3f702086a30 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
ClementBreteau 1:f3f702086a30 153 typedef struct
ClementBreteau 1:f3f702086a30 154 {
ClementBreteau 1:f3f702086a30 155 __IO uint32_t PINSEL0;
ClementBreteau 1:f3f702086a30 156 __IO uint32_t PINSEL1;
ClementBreteau 1:f3f702086a30 157 __IO uint32_t PINSEL2;
ClementBreteau 1:f3f702086a30 158 __IO uint32_t PINSEL3;
ClementBreteau 1:f3f702086a30 159 __IO uint32_t PINSEL4;
ClementBreteau 1:f3f702086a30 160 __IO uint32_t PINSEL5;
ClementBreteau 1:f3f702086a30 161 __IO uint32_t PINSEL6;
ClementBreteau 1:f3f702086a30 162 __IO uint32_t PINSEL7;
ClementBreteau 1:f3f702086a30 163 __IO uint32_t PINSEL8;
ClementBreteau 1:f3f702086a30 164 __IO uint32_t PINSEL9;
ClementBreteau 1:f3f702086a30 165 __IO uint32_t PINSEL10;
ClementBreteau 1:f3f702086a30 166 uint32_t RESERVED0[5];
ClementBreteau 1:f3f702086a30 167 __IO uint32_t PINMODE0;
ClementBreteau 1:f3f702086a30 168 __IO uint32_t PINMODE1;
ClementBreteau 1:f3f702086a30 169 __IO uint32_t PINMODE2;
ClementBreteau 1:f3f702086a30 170 __IO uint32_t PINMODE3;
ClementBreteau 1:f3f702086a30 171 __IO uint32_t PINMODE4;
ClementBreteau 1:f3f702086a30 172 __IO uint32_t PINMODE5;
ClementBreteau 1:f3f702086a30 173 __IO uint32_t PINMODE6;
ClementBreteau 1:f3f702086a30 174 __IO uint32_t PINMODE7;
ClementBreteau 1:f3f702086a30 175 __IO uint32_t PINMODE8;
ClementBreteau 1:f3f702086a30 176 __IO uint32_t PINMODE9;
ClementBreteau 1:f3f702086a30 177 __IO uint32_t PINMODE_OD0;
ClementBreteau 1:f3f702086a30 178 __IO uint32_t PINMODE_OD1;
ClementBreteau 1:f3f702086a30 179 __IO uint32_t PINMODE_OD2;
ClementBreteau 1:f3f702086a30 180 __IO uint32_t PINMODE_OD3;
ClementBreteau 1:f3f702086a30 181 __IO uint32_t PINMODE_OD4;
ClementBreteau 1:f3f702086a30 182 __IO uint32_t I2CPADCFG;
ClementBreteau 1:f3f702086a30 183 } LPC_PINCON_TypeDef;
ClementBreteau 1:f3f702086a30 184
ClementBreteau 1:f3f702086a30 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
ClementBreteau 1:f3f702086a30 186 typedef struct
ClementBreteau 1:f3f702086a30 187 {
ClementBreteau 1:f3f702086a30 188 union {
ClementBreteau 1:f3f702086a30 189 __IO uint32_t FIODIR;
ClementBreteau 1:f3f702086a30 190 struct {
ClementBreteau 1:f3f702086a30 191 __IO uint16_t FIODIRL;
ClementBreteau 1:f3f702086a30 192 __IO uint16_t FIODIRH;
ClementBreteau 1:f3f702086a30 193 };
ClementBreteau 1:f3f702086a30 194 struct {
ClementBreteau 1:f3f702086a30 195 __IO uint8_t FIODIR0;
ClementBreteau 1:f3f702086a30 196 __IO uint8_t FIODIR1;
ClementBreteau 1:f3f702086a30 197 __IO uint8_t FIODIR2;
ClementBreteau 1:f3f702086a30 198 __IO uint8_t FIODIR3;
ClementBreteau 1:f3f702086a30 199 };
ClementBreteau 1:f3f702086a30 200 };
ClementBreteau 1:f3f702086a30 201 uint32_t RESERVED0[3];
ClementBreteau 1:f3f702086a30 202 union {
ClementBreteau 1:f3f702086a30 203 __IO uint32_t FIOMASK;
ClementBreteau 1:f3f702086a30 204 struct {
ClementBreteau 1:f3f702086a30 205 __IO uint16_t FIOMASKL;
ClementBreteau 1:f3f702086a30 206 __IO uint16_t FIOMASKH;
ClementBreteau 1:f3f702086a30 207 };
ClementBreteau 1:f3f702086a30 208 struct {
ClementBreteau 1:f3f702086a30 209 __IO uint8_t FIOMASK0;
ClementBreteau 1:f3f702086a30 210 __IO uint8_t FIOMASK1;
ClementBreteau 1:f3f702086a30 211 __IO uint8_t FIOMASK2;
ClementBreteau 1:f3f702086a30 212 __IO uint8_t FIOMASK3;
ClementBreteau 1:f3f702086a30 213 };
ClementBreteau 1:f3f702086a30 214 };
ClementBreteau 1:f3f702086a30 215 union {
ClementBreteau 1:f3f702086a30 216 __IO uint32_t FIOPIN;
ClementBreteau 1:f3f702086a30 217 struct {
ClementBreteau 1:f3f702086a30 218 __IO uint16_t FIOPINL;
ClementBreteau 1:f3f702086a30 219 __IO uint16_t FIOPINH;
ClementBreteau 1:f3f702086a30 220 };
ClementBreteau 1:f3f702086a30 221 struct {
ClementBreteau 1:f3f702086a30 222 __IO uint8_t FIOPIN0;
ClementBreteau 1:f3f702086a30 223 __IO uint8_t FIOPIN1;
ClementBreteau 1:f3f702086a30 224 __IO uint8_t FIOPIN2;
ClementBreteau 1:f3f702086a30 225 __IO uint8_t FIOPIN3;
ClementBreteau 1:f3f702086a30 226 };
ClementBreteau 1:f3f702086a30 227 };
ClementBreteau 1:f3f702086a30 228 union {
ClementBreteau 1:f3f702086a30 229 __IO uint32_t FIOSET;
ClementBreteau 1:f3f702086a30 230 struct {
ClementBreteau 1:f3f702086a30 231 __IO uint16_t FIOSETL;
ClementBreteau 1:f3f702086a30 232 __IO uint16_t FIOSETH;
ClementBreteau 1:f3f702086a30 233 };
ClementBreteau 1:f3f702086a30 234 struct {
ClementBreteau 1:f3f702086a30 235 __IO uint8_t FIOSET0;
ClementBreteau 1:f3f702086a30 236 __IO uint8_t FIOSET1;
ClementBreteau 1:f3f702086a30 237 __IO uint8_t FIOSET2;
ClementBreteau 1:f3f702086a30 238 __IO uint8_t FIOSET3;
ClementBreteau 1:f3f702086a30 239 };
ClementBreteau 1:f3f702086a30 240 };
ClementBreteau 1:f3f702086a30 241 union {
ClementBreteau 1:f3f702086a30 242 __O uint32_t FIOCLR;
ClementBreteau 1:f3f702086a30 243 struct {
ClementBreteau 1:f3f702086a30 244 __O uint16_t FIOCLRL;
ClementBreteau 1:f3f702086a30 245 __O uint16_t FIOCLRH;
ClementBreteau 1:f3f702086a30 246 };
ClementBreteau 1:f3f702086a30 247 struct {
ClementBreteau 1:f3f702086a30 248 __O uint8_t FIOCLR0;
ClementBreteau 1:f3f702086a30 249 __O uint8_t FIOCLR1;
ClementBreteau 1:f3f702086a30 250 __O uint8_t FIOCLR2;
ClementBreteau 1:f3f702086a30 251 __O uint8_t FIOCLR3;
ClementBreteau 1:f3f702086a30 252 };
ClementBreteau 1:f3f702086a30 253 };
ClementBreteau 1:f3f702086a30 254 } LPC_GPIO_TypeDef;
ClementBreteau 1:f3f702086a30 255
ClementBreteau 1:f3f702086a30 256 typedef struct
ClementBreteau 1:f3f702086a30 257 {
ClementBreteau 1:f3f702086a30 258 __I uint32_t IntStatus;
ClementBreteau 1:f3f702086a30 259 __I uint32_t IO0IntStatR;
ClementBreteau 1:f3f702086a30 260 __I uint32_t IO0IntStatF;
ClementBreteau 1:f3f702086a30 261 __O uint32_t IO0IntClr;
ClementBreteau 1:f3f702086a30 262 __IO uint32_t IO0IntEnR;
ClementBreteau 1:f3f702086a30 263 __IO uint32_t IO0IntEnF;
ClementBreteau 1:f3f702086a30 264 uint32_t RESERVED0[3];
ClementBreteau 1:f3f702086a30 265 __I uint32_t IO2IntStatR;
ClementBreteau 1:f3f702086a30 266 __I uint32_t IO2IntStatF;
ClementBreteau 1:f3f702086a30 267 __O uint32_t IO2IntClr;
ClementBreteau 1:f3f702086a30 268 __IO uint32_t IO2IntEnR;
ClementBreteau 1:f3f702086a30 269 __IO uint32_t IO2IntEnF;
ClementBreteau 1:f3f702086a30 270 } LPC_GPIOINT_TypeDef;
ClementBreteau 1:f3f702086a30 271
ClementBreteau 1:f3f702086a30 272 /*------------- Timer (TIM) --------------------------------------------------*/
ClementBreteau 1:f3f702086a30 273 typedef struct
ClementBreteau 1:f3f702086a30 274 {
ClementBreteau 1:f3f702086a30 275 __IO uint32_t IR;
ClementBreteau 1:f3f702086a30 276 __IO uint32_t TCR;
ClementBreteau 1:f3f702086a30 277 __IO uint32_t TC;
ClementBreteau 1:f3f702086a30 278 __IO uint32_t PR;
ClementBreteau 1:f3f702086a30 279 __IO uint32_t PC;
ClementBreteau 1:f3f702086a30 280 __IO uint32_t MCR;
ClementBreteau 1:f3f702086a30 281 __IO uint32_t MR0;
ClementBreteau 1:f3f702086a30 282 __IO uint32_t MR1;
ClementBreteau 1:f3f702086a30 283 __IO uint32_t MR2;
ClementBreteau 1:f3f702086a30 284 __IO uint32_t MR3;
ClementBreteau 1:f3f702086a30 285 __IO uint32_t CCR;
ClementBreteau 1:f3f702086a30 286 __I uint32_t CR0;
ClementBreteau 1:f3f702086a30 287 __I uint32_t CR1;
ClementBreteau 1:f3f702086a30 288 uint32_t RESERVED0[2];
ClementBreteau 1:f3f702086a30 289 __IO uint32_t EMR;
ClementBreteau 1:f3f702086a30 290 uint32_t RESERVED1[12];
ClementBreteau 1:f3f702086a30 291 __IO uint32_t CTCR;
ClementBreteau 1:f3f702086a30 292 } LPC_TIM_TypeDef;
ClementBreteau 1:f3f702086a30 293
ClementBreteau 1:f3f702086a30 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
ClementBreteau 1:f3f702086a30 295 typedef struct
ClementBreteau 1:f3f702086a30 296 {
ClementBreteau 1:f3f702086a30 297 __IO uint32_t IR;
ClementBreteau 1:f3f702086a30 298 __IO uint32_t TCR;
ClementBreteau 1:f3f702086a30 299 __IO uint32_t TC;
ClementBreteau 1:f3f702086a30 300 __IO uint32_t PR;
ClementBreteau 1:f3f702086a30 301 __IO uint32_t PC;
ClementBreteau 1:f3f702086a30 302 __IO uint32_t MCR;
ClementBreteau 1:f3f702086a30 303 __IO uint32_t MR0;
ClementBreteau 1:f3f702086a30 304 __IO uint32_t MR1;
ClementBreteau 1:f3f702086a30 305 __IO uint32_t MR2;
ClementBreteau 1:f3f702086a30 306 __IO uint32_t MR3;
ClementBreteau 1:f3f702086a30 307 __IO uint32_t CCR;
ClementBreteau 1:f3f702086a30 308 __I uint32_t CR0;
ClementBreteau 1:f3f702086a30 309 __I uint32_t CR1;
ClementBreteau 1:f3f702086a30 310 __I uint32_t CR2;
ClementBreteau 1:f3f702086a30 311 __I uint32_t CR3;
ClementBreteau 1:f3f702086a30 312 uint32_t RESERVED0;
ClementBreteau 1:f3f702086a30 313 __IO uint32_t MR4;
ClementBreteau 1:f3f702086a30 314 __IO uint32_t MR5;
ClementBreteau 1:f3f702086a30 315 __IO uint32_t MR6;
ClementBreteau 1:f3f702086a30 316 __IO uint32_t PCR;
ClementBreteau 1:f3f702086a30 317 __IO uint32_t LER;
ClementBreteau 1:f3f702086a30 318 uint32_t RESERVED1[7];
ClementBreteau 1:f3f702086a30 319 __IO uint32_t CTCR;
ClementBreteau 1:f3f702086a30 320 } LPC_PWM_TypeDef;
ClementBreteau 1:f3f702086a30 321
ClementBreteau 1:f3f702086a30 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
ClementBreteau 1:f3f702086a30 323 typedef struct
ClementBreteau 1:f3f702086a30 324 {
ClementBreteau 1:f3f702086a30 325 union {
ClementBreteau 1:f3f702086a30 326 __I uint8_t RBR;
ClementBreteau 1:f3f702086a30 327 __O uint8_t THR;
ClementBreteau 1:f3f702086a30 328 __IO uint8_t DLL;
ClementBreteau 1:f3f702086a30 329 uint32_t RESERVED0;
ClementBreteau 1:f3f702086a30 330 };
ClementBreteau 1:f3f702086a30 331 union {
ClementBreteau 1:f3f702086a30 332 __IO uint8_t DLM;
ClementBreteau 1:f3f702086a30 333 __IO uint32_t IER;
ClementBreteau 1:f3f702086a30 334 };
ClementBreteau 1:f3f702086a30 335 union {
ClementBreteau 1:f3f702086a30 336 __I uint32_t IIR;
ClementBreteau 1:f3f702086a30 337 __O uint8_t FCR;
ClementBreteau 1:f3f702086a30 338 };
ClementBreteau 1:f3f702086a30 339 __IO uint8_t LCR;
ClementBreteau 1:f3f702086a30 340 uint8_t RESERVED1[7];
ClementBreteau 1:f3f702086a30 341 __I uint8_t LSR;
ClementBreteau 1:f3f702086a30 342 uint8_t RESERVED2[7];
ClementBreteau 1:f3f702086a30 343 __IO uint8_t SCR;
ClementBreteau 1:f3f702086a30 344 uint8_t RESERVED3[3];
ClementBreteau 1:f3f702086a30 345 __IO uint32_t ACR;
ClementBreteau 1:f3f702086a30 346 __IO uint8_t ICR;
ClementBreteau 1:f3f702086a30 347 uint8_t RESERVED4[3];
ClementBreteau 1:f3f702086a30 348 __IO uint8_t FDR;
ClementBreteau 1:f3f702086a30 349 uint8_t RESERVED5[7];
ClementBreteau 1:f3f702086a30 350 __IO uint8_t TER;
ClementBreteau 1:f3f702086a30 351 uint8_t RESERVED6[39];
ClementBreteau 1:f3f702086a30 352 __IO uint32_t FIFOLVL;
ClementBreteau 1:f3f702086a30 353 } LPC_UART_TypeDef;
ClementBreteau 1:f3f702086a30 354
ClementBreteau 1:f3f702086a30 355 typedef struct
ClementBreteau 1:f3f702086a30 356 {
ClementBreteau 1:f3f702086a30 357 union {
ClementBreteau 1:f3f702086a30 358 __I uint8_t RBR;
ClementBreteau 1:f3f702086a30 359 __O uint8_t THR;
ClementBreteau 1:f3f702086a30 360 __IO uint8_t DLL;
ClementBreteau 1:f3f702086a30 361 uint32_t RESERVED0;
ClementBreteau 1:f3f702086a30 362 };
ClementBreteau 1:f3f702086a30 363 union {
ClementBreteau 1:f3f702086a30 364 __IO uint8_t DLM;
ClementBreteau 1:f3f702086a30 365 __IO uint32_t IER;
ClementBreteau 1:f3f702086a30 366 };
ClementBreteau 1:f3f702086a30 367 union {
ClementBreteau 1:f3f702086a30 368 __I uint32_t IIR;
ClementBreteau 1:f3f702086a30 369 __O uint8_t FCR;
ClementBreteau 1:f3f702086a30 370 };
ClementBreteau 1:f3f702086a30 371 __IO uint8_t LCR;
ClementBreteau 1:f3f702086a30 372 uint8_t RESERVED1[7];
ClementBreteau 1:f3f702086a30 373 __I uint8_t LSR;
ClementBreteau 1:f3f702086a30 374 uint8_t RESERVED2[7];
ClementBreteau 1:f3f702086a30 375 __IO uint8_t SCR;
ClementBreteau 1:f3f702086a30 376 uint8_t RESERVED3[3];
ClementBreteau 1:f3f702086a30 377 __IO uint32_t ACR;
ClementBreteau 1:f3f702086a30 378 __IO uint8_t ICR;
ClementBreteau 1:f3f702086a30 379 uint8_t RESERVED4[3];
ClementBreteau 1:f3f702086a30 380 __IO uint8_t FDR;
ClementBreteau 1:f3f702086a30 381 uint8_t RESERVED5[7];
ClementBreteau 1:f3f702086a30 382 __IO uint8_t TER;
ClementBreteau 1:f3f702086a30 383 uint8_t RESERVED6[39];
ClementBreteau 1:f3f702086a30 384 __IO uint32_t FIFOLVL;
ClementBreteau 1:f3f702086a30 385 } LPC_UART0_TypeDef;
ClementBreteau 1:f3f702086a30 386
ClementBreteau 1:f3f702086a30 387 typedef struct
ClementBreteau 1:f3f702086a30 388 {
ClementBreteau 1:f3f702086a30 389 union {
ClementBreteau 1:f3f702086a30 390 __I uint8_t RBR;
ClementBreteau 1:f3f702086a30 391 __O uint8_t THR;
ClementBreteau 1:f3f702086a30 392 __IO uint8_t DLL;
ClementBreteau 1:f3f702086a30 393 uint32_t RESERVED0;
ClementBreteau 1:f3f702086a30 394 };
ClementBreteau 1:f3f702086a30 395 union {
ClementBreteau 1:f3f702086a30 396 __IO uint8_t DLM;
ClementBreteau 1:f3f702086a30 397 __IO uint32_t IER;
ClementBreteau 1:f3f702086a30 398 };
ClementBreteau 1:f3f702086a30 399 union {
ClementBreteau 1:f3f702086a30 400 __I uint32_t IIR;
ClementBreteau 1:f3f702086a30 401 __O uint8_t FCR;
ClementBreteau 1:f3f702086a30 402 };
ClementBreteau 1:f3f702086a30 403 __IO uint8_t LCR;
ClementBreteau 1:f3f702086a30 404 uint8_t RESERVED1[3];
ClementBreteau 1:f3f702086a30 405 __IO uint8_t MCR;
ClementBreteau 1:f3f702086a30 406 uint8_t RESERVED2[3];
ClementBreteau 1:f3f702086a30 407 __I uint8_t LSR;
ClementBreteau 1:f3f702086a30 408 uint8_t RESERVED3[3];
ClementBreteau 1:f3f702086a30 409 __I uint8_t MSR;
ClementBreteau 1:f3f702086a30 410 uint8_t RESERVED4[3];
ClementBreteau 1:f3f702086a30 411 __IO uint8_t SCR;
ClementBreteau 1:f3f702086a30 412 uint8_t RESERVED5[3];
ClementBreteau 1:f3f702086a30 413 __IO uint32_t ACR;
ClementBreteau 1:f3f702086a30 414 uint32_t RESERVED6;
ClementBreteau 1:f3f702086a30 415 __IO uint32_t FDR;
ClementBreteau 1:f3f702086a30 416 uint32_t RESERVED7;
ClementBreteau 1:f3f702086a30 417 __IO uint8_t TER;
ClementBreteau 1:f3f702086a30 418 uint8_t RESERVED8[27];
ClementBreteau 1:f3f702086a30 419 __IO uint8_t RS485CTRL;
ClementBreteau 1:f3f702086a30 420 uint8_t RESERVED9[3];
ClementBreteau 1:f3f702086a30 421 __IO uint8_t ADRMATCH;
ClementBreteau 1:f3f702086a30 422 uint8_t RESERVED10[3];
ClementBreteau 1:f3f702086a30 423 __IO uint8_t RS485DLY;
ClementBreteau 1:f3f702086a30 424 uint8_t RESERVED11[3];
ClementBreteau 1:f3f702086a30 425 __IO uint32_t FIFOLVL;
ClementBreteau 1:f3f702086a30 426 } LPC_UART1_TypeDef;
ClementBreteau 1:f3f702086a30 427
ClementBreteau 1:f3f702086a30 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
ClementBreteau 1:f3f702086a30 429 typedef struct
ClementBreteau 1:f3f702086a30 430 {
ClementBreteau 1:f3f702086a30 431 __IO uint32_t SPCR;
ClementBreteau 1:f3f702086a30 432 __I uint32_t SPSR;
ClementBreteau 1:f3f702086a30 433 __IO uint32_t SPDR;
ClementBreteau 1:f3f702086a30 434 __IO uint32_t SPCCR;
ClementBreteau 1:f3f702086a30 435 uint32_t RESERVED0[3];
ClementBreteau 1:f3f702086a30 436 __IO uint32_t SPINT;
ClementBreteau 1:f3f702086a30 437 } LPC_SPI_TypeDef;
ClementBreteau 1:f3f702086a30 438
ClementBreteau 1:f3f702086a30 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
ClementBreteau 1:f3f702086a30 440 typedef struct
ClementBreteau 1:f3f702086a30 441 {
ClementBreteau 1:f3f702086a30 442 __IO uint32_t CR0;
ClementBreteau 1:f3f702086a30 443 __IO uint32_t CR1;
ClementBreteau 1:f3f702086a30 444 __IO uint32_t DR;
ClementBreteau 1:f3f702086a30 445 __I uint32_t SR;
ClementBreteau 1:f3f702086a30 446 __IO uint32_t CPSR;
ClementBreteau 1:f3f702086a30 447 __IO uint32_t IMSC;
ClementBreteau 1:f3f702086a30 448 __IO uint32_t RIS;
ClementBreteau 1:f3f702086a30 449 __IO uint32_t MIS;
ClementBreteau 1:f3f702086a30 450 __IO uint32_t ICR;
ClementBreteau 1:f3f702086a30 451 __IO uint32_t DMACR;
ClementBreteau 1:f3f702086a30 452 } LPC_SSP_TypeDef;
ClementBreteau 1:f3f702086a30 453
ClementBreteau 1:f3f702086a30 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
ClementBreteau 1:f3f702086a30 455 typedef struct
ClementBreteau 1:f3f702086a30 456 {
ClementBreteau 1:f3f702086a30 457 __IO uint32_t I2CONSET;
ClementBreteau 1:f3f702086a30 458 __I uint32_t I2STAT;
ClementBreteau 1:f3f702086a30 459 __IO uint32_t I2DAT;
ClementBreteau 1:f3f702086a30 460 __IO uint32_t I2ADR0;
ClementBreteau 1:f3f702086a30 461 __IO uint32_t I2SCLH;
ClementBreteau 1:f3f702086a30 462 __IO uint32_t I2SCLL;
ClementBreteau 1:f3f702086a30 463 __O uint32_t I2CONCLR;
ClementBreteau 1:f3f702086a30 464 __IO uint32_t MMCTRL;
ClementBreteau 1:f3f702086a30 465 __IO uint32_t I2ADR1;
ClementBreteau 1:f3f702086a30 466 __IO uint32_t I2ADR2;
ClementBreteau 1:f3f702086a30 467 __IO uint32_t I2ADR3;
ClementBreteau 1:f3f702086a30 468 __I uint32_t I2DATA_BUFFER;
ClementBreteau 1:f3f702086a30 469 __IO uint32_t I2MASK0;
ClementBreteau 1:f3f702086a30 470 __IO uint32_t I2MASK1;
ClementBreteau 1:f3f702086a30 471 __IO uint32_t I2MASK2;
ClementBreteau 1:f3f702086a30 472 __IO uint32_t I2MASK3;
ClementBreteau 1:f3f702086a30 473 } LPC_I2C_TypeDef;
ClementBreteau 1:f3f702086a30 474
ClementBreteau 1:f3f702086a30 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
ClementBreteau 1:f3f702086a30 476 typedef struct
ClementBreteau 1:f3f702086a30 477 {
ClementBreteau 1:f3f702086a30 478 __IO uint32_t I2SDAO;
ClementBreteau 1:f3f702086a30 479 __IO uint32_t I2SDAI;
ClementBreteau 1:f3f702086a30 480 __O uint32_t I2STXFIFO;
ClementBreteau 1:f3f702086a30 481 __I uint32_t I2SRXFIFO;
ClementBreteau 1:f3f702086a30 482 __I uint32_t I2SSTATE;
ClementBreteau 1:f3f702086a30 483 __IO uint32_t I2SDMA1;
ClementBreteau 1:f3f702086a30 484 __IO uint32_t I2SDMA2;
ClementBreteau 1:f3f702086a30 485 __IO uint32_t I2SIRQ;
ClementBreteau 1:f3f702086a30 486 __IO uint32_t I2STXRATE;
ClementBreteau 1:f3f702086a30 487 __IO uint32_t I2SRXRATE;
ClementBreteau 1:f3f702086a30 488 __IO uint32_t I2STXBITRATE;
ClementBreteau 1:f3f702086a30 489 __IO uint32_t I2SRXBITRATE;
ClementBreteau 1:f3f702086a30 490 __IO uint32_t I2STXMODE;
ClementBreteau 1:f3f702086a30 491 __IO uint32_t I2SRXMODE;
ClementBreteau 1:f3f702086a30 492 } LPC_I2S_TypeDef;
ClementBreteau 1:f3f702086a30 493
ClementBreteau 1:f3f702086a30 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
ClementBreteau 1:f3f702086a30 495 typedef struct
ClementBreteau 1:f3f702086a30 496 {
ClementBreteau 1:f3f702086a30 497 __IO uint32_t RICOMPVAL;
ClementBreteau 1:f3f702086a30 498 __IO uint32_t RIMASK;
ClementBreteau 1:f3f702086a30 499 __IO uint8_t RICTRL;
ClementBreteau 1:f3f702086a30 500 uint8_t RESERVED0[3];
ClementBreteau 1:f3f702086a30 501 __IO uint32_t RICOUNTER;
ClementBreteau 1:f3f702086a30 502 } LPC_RIT_TypeDef;
ClementBreteau 1:f3f702086a30 503
ClementBreteau 1:f3f702086a30 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
ClementBreteau 1:f3f702086a30 505 typedef struct
ClementBreteau 1:f3f702086a30 506 {
ClementBreteau 1:f3f702086a30 507 __IO uint8_t ILR;
ClementBreteau 1:f3f702086a30 508 uint8_t RESERVED0[7];
ClementBreteau 1:f3f702086a30 509 __IO uint8_t CCR;
ClementBreteau 1:f3f702086a30 510 uint8_t RESERVED1[3];
ClementBreteau 1:f3f702086a30 511 __IO uint8_t CIIR;
ClementBreteau 1:f3f702086a30 512 uint8_t RESERVED2[3];
ClementBreteau 1:f3f702086a30 513 __IO uint8_t AMR;
ClementBreteau 1:f3f702086a30 514 uint8_t RESERVED3[3];
ClementBreteau 1:f3f702086a30 515 __I uint32_t CTIME0;
ClementBreteau 1:f3f702086a30 516 __I uint32_t CTIME1;
ClementBreteau 1:f3f702086a30 517 __I uint32_t CTIME2;
ClementBreteau 1:f3f702086a30 518 __IO uint8_t SEC;
ClementBreteau 1:f3f702086a30 519 uint8_t RESERVED4[3];
ClementBreteau 1:f3f702086a30 520 __IO uint8_t MIN;
ClementBreteau 1:f3f702086a30 521 uint8_t RESERVED5[3];
ClementBreteau 1:f3f702086a30 522 __IO uint8_t HOUR;
ClementBreteau 1:f3f702086a30 523 uint8_t RESERVED6[3];
ClementBreteau 1:f3f702086a30 524 __IO uint8_t DOM;
ClementBreteau 1:f3f702086a30 525 uint8_t RESERVED7[3];
ClementBreteau 1:f3f702086a30 526 __IO uint8_t DOW;
ClementBreteau 1:f3f702086a30 527 uint8_t RESERVED8[3];
ClementBreteau 1:f3f702086a30 528 __IO uint16_t DOY;
ClementBreteau 1:f3f702086a30 529 uint16_t RESERVED9;
ClementBreteau 1:f3f702086a30 530 __IO uint8_t MONTH;
ClementBreteau 1:f3f702086a30 531 uint8_t RESERVED10[3];
ClementBreteau 1:f3f702086a30 532 __IO uint16_t YEAR;
ClementBreteau 1:f3f702086a30 533 uint16_t RESERVED11;
ClementBreteau 1:f3f702086a30 534 __IO uint32_t CALIBRATION;
ClementBreteau 1:f3f702086a30 535 __IO uint32_t GPREG0;
ClementBreteau 1:f3f702086a30 536 __IO uint32_t GPREG1;
ClementBreteau 1:f3f702086a30 537 __IO uint32_t GPREG2;
ClementBreteau 1:f3f702086a30 538 __IO uint32_t GPREG3;
ClementBreteau 1:f3f702086a30 539 __IO uint32_t GPREG4;
ClementBreteau 1:f3f702086a30 540 __IO uint8_t RTC_AUXEN;
ClementBreteau 1:f3f702086a30 541 uint8_t RESERVED12[3];
ClementBreteau 1:f3f702086a30 542 __IO uint8_t RTC_AUX;
ClementBreteau 1:f3f702086a30 543 uint8_t RESERVED13[3];
ClementBreteau 1:f3f702086a30 544 __IO uint8_t ALSEC;
ClementBreteau 1:f3f702086a30 545 uint8_t RESERVED14[3];
ClementBreteau 1:f3f702086a30 546 __IO uint8_t ALMIN;
ClementBreteau 1:f3f702086a30 547 uint8_t RESERVED15[3];
ClementBreteau 1:f3f702086a30 548 __IO uint8_t ALHOUR;
ClementBreteau 1:f3f702086a30 549 uint8_t RESERVED16[3];
ClementBreteau 1:f3f702086a30 550 __IO uint8_t ALDOM;
ClementBreteau 1:f3f702086a30 551 uint8_t RESERVED17[3];
ClementBreteau 1:f3f702086a30 552 __IO uint8_t ALDOW;
ClementBreteau 1:f3f702086a30 553 uint8_t RESERVED18[3];
ClementBreteau 1:f3f702086a30 554 __IO uint16_t ALDOY;
ClementBreteau 1:f3f702086a30 555 uint16_t RESERVED19;
ClementBreteau 1:f3f702086a30 556 __IO uint8_t ALMON;
ClementBreteau 1:f3f702086a30 557 uint8_t RESERVED20[3];
ClementBreteau 1:f3f702086a30 558 __IO uint16_t ALYEAR;
ClementBreteau 1:f3f702086a30 559 uint16_t RESERVED21;
ClementBreteau 1:f3f702086a30 560 } LPC_RTC_TypeDef;
ClementBreteau 1:f3f702086a30 561
ClementBreteau 1:f3f702086a30 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
ClementBreteau 1:f3f702086a30 563 typedef struct
ClementBreteau 1:f3f702086a30 564 {
ClementBreteau 1:f3f702086a30 565 __IO uint8_t WDMOD;
ClementBreteau 1:f3f702086a30 566 uint8_t RESERVED0[3];
ClementBreteau 1:f3f702086a30 567 __IO uint32_t WDTC;
ClementBreteau 1:f3f702086a30 568 __O uint8_t WDFEED;
ClementBreteau 1:f3f702086a30 569 uint8_t RESERVED1[3];
ClementBreteau 1:f3f702086a30 570 __I uint32_t WDTV;
ClementBreteau 1:f3f702086a30 571 __IO uint32_t WDCLKSEL;
ClementBreteau 1:f3f702086a30 572 } LPC_WDT_TypeDef;
ClementBreteau 1:f3f702086a30 573
ClementBreteau 1:f3f702086a30 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
ClementBreteau 1:f3f702086a30 575 typedef struct
ClementBreteau 1:f3f702086a30 576 {
ClementBreteau 1:f3f702086a30 577 __IO uint32_t ADCR;
ClementBreteau 1:f3f702086a30 578 __IO uint32_t ADGDR;
ClementBreteau 1:f3f702086a30 579 uint32_t RESERVED0;
ClementBreteau 1:f3f702086a30 580 __IO uint32_t ADINTEN;
ClementBreteau 1:f3f702086a30 581 __I uint32_t ADDR0;
ClementBreteau 1:f3f702086a30 582 __I uint32_t ADDR1;
ClementBreteau 1:f3f702086a30 583 __I uint32_t ADDR2;
ClementBreteau 1:f3f702086a30 584 __I uint32_t ADDR3;
ClementBreteau 1:f3f702086a30 585 __I uint32_t ADDR4;
ClementBreteau 1:f3f702086a30 586 __I uint32_t ADDR5;
ClementBreteau 1:f3f702086a30 587 __I uint32_t ADDR6;
ClementBreteau 1:f3f702086a30 588 __I uint32_t ADDR7;
ClementBreteau 1:f3f702086a30 589 __I uint32_t ADSTAT;
ClementBreteau 1:f3f702086a30 590 __IO uint32_t ADTRM;
ClementBreteau 1:f3f702086a30 591 } LPC_ADC_TypeDef;
ClementBreteau 1:f3f702086a30 592
ClementBreteau 1:f3f702086a30 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
ClementBreteau 1:f3f702086a30 594 typedef struct
ClementBreteau 1:f3f702086a30 595 {
ClementBreteau 1:f3f702086a30 596 __IO uint32_t DACR;
ClementBreteau 1:f3f702086a30 597 __IO uint32_t DACCTRL;
ClementBreteau 1:f3f702086a30 598 __IO uint16_t DACCNTVAL;
ClementBreteau 1:f3f702086a30 599 } LPC_DAC_TypeDef;
ClementBreteau 1:f3f702086a30 600
ClementBreteau 1:f3f702086a30 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
ClementBreteau 1:f3f702086a30 602 typedef struct
ClementBreteau 1:f3f702086a30 603 {
ClementBreteau 1:f3f702086a30 604 __I uint32_t MCCON;
ClementBreteau 1:f3f702086a30 605 __O uint32_t MCCON_SET;
ClementBreteau 1:f3f702086a30 606 __O uint32_t MCCON_CLR;
ClementBreteau 1:f3f702086a30 607 __I uint32_t MCCAPCON;
ClementBreteau 1:f3f702086a30 608 __O uint32_t MCCAPCON_SET;
ClementBreteau 1:f3f702086a30 609 __O uint32_t MCCAPCON_CLR;
ClementBreteau 1:f3f702086a30 610 __IO uint32_t MCTIM0;
ClementBreteau 1:f3f702086a30 611 __IO uint32_t MCTIM1;
ClementBreteau 1:f3f702086a30 612 __IO uint32_t MCTIM2;
ClementBreteau 1:f3f702086a30 613 __IO uint32_t MCPER0;
ClementBreteau 1:f3f702086a30 614 __IO uint32_t MCPER1;
ClementBreteau 1:f3f702086a30 615 __IO uint32_t MCPER2;
ClementBreteau 1:f3f702086a30 616 __IO uint32_t MCPW0;
ClementBreteau 1:f3f702086a30 617 __IO uint32_t MCPW1;
ClementBreteau 1:f3f702086a30 618 __IO uint32_t MCPW2;
ClementBreteau 1:f3f702086a30 619 __IO uint32_t MCDEADTIME;
ClementBreteau 1:f3f702086a30 620 __IO uint32_t MCCCP;
ClementBreteau 1:f3f702086a30 621 __IO uint32_t MCCR0;
ClementBreteau 1:f3f702086a30 622 __IO uint32_t MCCR1;
ClementBreteau 1:f3f702086a30 623 __IO uint32_t MCCR2;
ClementBreteau 1:f3f702086a30 624 __I uint32_t MCINTEN;
ClementBreteau 1:f3f702086a30 625 __O uint32_t MCINTEN_SET;
ClementBreteau 1:f3f702086a30 626 __O uint32_t MCINTEN_CLR;
ClementBreteau 1:f3f702086a30 627 __I uint32_t MCCNTCON;
ClementBreteau 1:f3f702086a30 628 __O uint32_t MCCNTCON_SET;
ClementBreteau 1:f3f702086a30 629 __O uint32_t MCCNTCON_CLR;
ClementBreteau 1:f3f702086a30 630 __I uint32_t MCINTFLAG;
ClementBreteau 1:f3f702086a30 631 __O uint32_t MCINTFLAG_SET;
ClementBreteau 1:f3f702086a30 632 __O uint32_t MCINTFLAG_CLR;
ClementBreteau 1:f3f702086a30 633 __O uint32_t MCCAP_CLR;
ClementBreteau 1:f3f702086a30 634 } LPC_MCPWM_TypeDef;
ClementBreteau 1:f3f702086a30 635
ClementBreteau 1:f3f702086a30 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
ClementBreteau 1:f3f702086a30 637 typedef struct
ClementBreteau 1:f3f702086a30 638 {
ClementBreteau 1:f3f702086a30 639 __O uint32_t QEICON;
ClementBreteau 1:f3f702086a30 640 __I uint32_t QEISTAT;
ClementBreteau 1:f3f702086a30 641 __IO uint32_t QEICONF;
ClementBreteau 1:f3f702086a30 642 __I uint32_t QEIPOS;
ClementBreteau 1:f3f702086a30 643 __IO uint32_t QEIMAXPOS;
ClementBreteau 1:f3f702086a30 644 __IO uint32_t CMPOS0;
ClementBreteau 1:f3f702086a30 645 __IO uint32_t CMPOS1;
ClementBreteau 1:f3f702086a30 646 __IO uint32_t CMPOS2;
ClementBreteau 1:f3f702086a30 647 __I uint32_t INXCNT;
ClementBreteau 1:f3f702086a30 648 __IO uint32_t INXCMP;
ClementBreteau 1:f3f702086a30 649 __IO uint32_t QEILOAD;
ClementBreteau 1:f3f702086a30 650 __I uint32_t QEITIME;
ClementBreteau 1:f3f702086a30 651 __I uint32_t QEIVEL;
ClementBreteau 1:f3f702086a30 652 __I uint32_t QEICAP;
ClementBreteau 1:f3f702086a30 653 __IO uint32_t VELCOMP;
ClementBreteau 1:f3f702086a30 654 __IO uint32_t FILTER;
ClementBreteau 1:f3f702086a30 655 uint32_t RESERVED0[998];
ClementBreteau 1:f3f702086a30 656 __O uint32_t QEIIEC;
ClementBreteau 1:f3f702086a30 657 __O uint32_t QEIIES;
ClementBreteau 1:f3f702086a30 658 __I uint32_t QEIINTSTAT;
ClementBreteau 1:f3f702086a30 659 __I uint32_t QEIIE;
ClementBreteau 1:f3f702086a30 660 __O uint32_t QEICLR;
ClementBreteau 1:f3f702086a30 661 __O uint32_t QEISET;
ClementBreteau 1:f3f702086a30 662 } LPC_QEI_TypeDef;
ClementBreteau 1:f3f702086a30 663
ClementBreteau 1:f3f702086a30 664 /*------------- Controller Area Network (CAN) --------------------------------*/
ClementBreteau 1:f3f702086a30 665 typedef struct
ClementBreteau 1:f3f702086a30 666 {
ClementBreteau 1:f3f702086a30 667 __IO uint32_t mask[512]; /* ID Masks */
ClementBreteau 1:f3f702086a30 668 } LPC_CANAF_RAM_TypeDef;
ClementBreteau 1:f3f702086a30 669
ClementBreteau 1:f3f702086a30 670 typedef struct /* Acceptance Filter Registers */
ClementBreteau 1:f3f702086a30 671 {
ClementBreteau 1:f3f702086a30 672 __IO uint32_t AFMR;
ClementBreteau 1:f3f702086a30 673 __IO uint32_t SFF_sa;
ClementBreteau 1:f3f702086a30 674 __IO uint32_t SFF_GRP_sa;
ClementBreteau 1:f3f702086a30 675 __IO uint32_t EFF_sa;
ClementBreteau 1:f3f702086a30 676 __IO uint32_t EFF_GRP_sa;
ClementBreteau 1:f3f702086a30 677 __IO uint32_t ENDofTable;
ClementBreteau 1:f3f702086a30 678 __I uint32_t LUTerrAd;
ClementBreteau 1:f3f702086a30 679 __I uint32_t LUTerr;
ClementBreteau 1:f3f702086a30 680 __IO uint32_t FCANIE;
ClementBreteau 1:f3f702086a30 681 __IO uint32_t FCANIC0;
ClementBreteau 1:f3f702086a30 682 __IO uint32_t FCANIC1;
ClementBreteau 1:f3f702086a30 683 } LPC_CANAF_TypeDef;
ClementBreteau 1:f3f702086a30 684
ClementBreteau 1:f3f702086a30 685 typedef struct /* Central Registers */
ClementBreteau 1:f3f702086a30 686 {
ClementBreteau 1:f3f702086a30 687 __I uint32_t CANTxSR;
ClementBreteau 1:f3f702086a30 688 __I uint32_t CANRxSR;
ClementBreteau 1:f3f702086a30 689 __I uint32_t CANMSR;
ClementBreteau 1:f3f702086a30 690 } LPC_CANCR_TypeDef;
ClementBreteau 1:f3f702086a30 691
ClementBreteau 1:f3f702086a30 692 typedef struct /* Controller Registers */
ClementBreteau 1:f3f702086a30 693 {
ClementBreteau 1:f3f702086a30 694 __IO uint32_t MOD;
ClementBreteau 1:f3f702086a30 695 __O uint32_t CMR;
ClementBreteau 1:f3f702086a30 696 __IO uint32_t GSR;
ClementBreteau 1:f3f702086a30 697 __I uint32_t ICR;
ClementBreteau 1:f3f702086a30 698 __IO uint32_t IER;
ClementBreteau 1:f3f702086a30 699 __IO uint32_t BTR;
ClementBreteau 1:f3f702086a30 700 __IO uint32_t EWL;
ClementBreteau 1:f3f702086a30 701 __I uint32_t SR;
ClementBreteau 1:f3f702086a30 702 __IO uint32_t RFS;
ClementBreteau 1:f3f702086a30 703 __IO uint32_t RID;
ClementBreteau 1:f3f702086a30 704 __IO uint32_t RDA;
ClementBreteau 1:f3f702086a30 705 __IO uint32_t RDB;
ClementBreteau 1:f3f702086a30 706 __IO uint32_t TFI1;
ClementBreteau 1:f3f702086a30 707 __IO uint32_t TID1;
ClementBreteau 1:f3f702086a30 708 __IO uint32_t TDA1;
ClementBreteau 1:f3f702086a30 709 __IO uint32_t TDB1;
ClementBreteau 1:f3f702086a30 710 __IO uint32_t TFI2;
ClementBreteau 1:f3f702086a30 711 __IO uint32_t TID2;
ClementBreteau 1:f3f702086a30 712 __IO uint32_t TDA2;
ClementBreteau 1:f3f702086a30 713 __IO uint32_t TDB2;
ClementBreteau 1:f3f702086a30 714 __IO uint32_t TFI3;
ClementBreteau 1:f3f702086a30 715 __IO uint32_t TID3;
ClementBreteau 1:f3f702086a30 716 __IO uint32_t TDA3;
ClementBreteau 1:f3f702086a30 717 __IO uint32_t TDB3;
ClementBreteau 1:f3f702086a30 718 } LPC_CAN_TypeDef;
ClementBreteau 1:f3f702086a30 719
ClementBreteau 1:f3f702086a30 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
ClementBreteau 1:f3f702086a30 721 typedef struct /* Common Registers */
ClementBreteau 1:f3f702086a30 722 {
ClementBreteau 1:f3f702086a30 723 __I uint32_t DMACIntStat;
ClementBreteau 1:f3f702086a30 724 __I uint32_t DMACIntTCStat;
ClementBreteau 1:f3f702086a30 725 __O uint32_t DMACIntTCClear;
ClementBreteau 1:f3f702086a30 726 __I uint32_t DMACIntErrStat;
ClementBreteau 1:f3f702086a30 727 __O uint32_t DMACIntErrClr;
ClementBreteau 1:f3f702086a30 728 __I uint32_t DMACRawIntTCStat;
ClementBreteau 1:f3f702086a30 729 __I uint32_t DMACRawIntErrStat;
ClementBreteau 1:f3f702086a30 730 __I uint32_t DMACEnbldChns;
ClementBreteau 1:f3f702086a30 731 __IO uint32_t DMACSoftBReq;
ClementBreteau 1:f3f702086a30 732 __IO uint32_t DMACSoftSReq;
ClementBreteau 1:f3f702086a30 733 __IO uint32_t DMACSoftLBReq;
ClementBreteau 1:f3f702086a30 734 __IO uint32_t DMACSoftLSReq;
ClementBreteau 1:f3f702086a30 735 __IO uint32_t DMACConfig;
ClementBreteau 1:f3f702086a30 736 __IO uint32_t DMACSync;
ClementBreteau 1:f3f702086a30 737 } LPC_GPDMA_TypeDef;
ClementBreteau 1:f3f702086a30 738
ClementBreteau 1:f3f702086a30 739 typedef struct /* Channel Registers */
ClementBreteau 1:f3f702086a30 740 {
ClementBreteau 1:f3f702086a30 741 __IO uint32_t DMACCSrcAddr;
ClementBreteau 1:f3f702086a30 742 __IO uint32_t DMACCDestAddr;
ClementBreteau 1:f3f702086a30 743 __IO uint32_t DMACCLLI;
ClementBreteau 1:f3f702086a30 744 __IO uint32_t DMACCControl;
ClementBreteau 1:f3f702086a30 745 __IO uint32_t DMACCConfig;
ClementBreteau 1:f3f702086a30 746 } LPC_GPDMACH_TypeDef;
ClementBreteau 1:f3f702086a30 747
ClementBreteau 1:f3f702086a30 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
ClementBreteau 1:f3f702086a30 749 typedef struct
ClementBreteau 1:f3f702086a30 750 {
ClementBreteau 1:f3f702086a30 751 __I uint32_t HcRevision; /* USB Host Registers */
ClementBreteau 1:f3f702086a30 752 __IO uint32_t HcControl;
ClementBreteau 1:f3f702086a30 753 __IO uint32_t HcCommandStatus;
ClementBreteau 1:f3f702086a30 754 __IO uint32_t HcInterruptStatus;
ClementBreteau 1:f3f702086a30 755 __IO uint32_t HcInterruptEnable;
ClementBreteau 1:f3f702086a30 756 __IO uint32_t HcInterruptDisable;
ClementBreteau 1:f3f702086a30 757 __IO uint32_t HcHCCA;
ClementBreteau 1:f3f702086a30 758 __I uint32_t HcPeriodCurrentED;
ClementBreteau 1:f3f702086a30 759 __IO uint32_t HcControlHeadED;
ClementBreteau 1:f3f702086a30 760 __IO uint32_t HcControlCurrentED;
ClementBreteau 1:f3f702086a30 761 __IO uint32_t HcBulkHeadED;
ClementBreteau 1:f3f702086a30 762 __IO uint32_t HcBulkCurrentED;
ClementBreteau 1:f3f702086a30 763 __I uint32_t HcDoneHead;
ClementBreteau 1:f3f702086a30 764 __IO uint32_t HcFmInterval;
ClementBreteau 1:f3f702086a30 765 __I uint32_t HcFmRemaining;
ClementBreteau 1:f3f702086a30 766 __I uint32_t HcFmNumber;
ClementBreteau 1:f3f702086a30 767 __IO uint32_t HcPeriodicStart;
ClementBreteau 1:f3f702086a30 768 __IO uint32_t HcLSTreshold;
ClementBreteau 1:f3f702086a30 769 __IO uint32_t HcRhDescriptorA;
ClementBreteau 1:f3f702086a30 770 __IO uint32_t HcRhDescriptorB;
ClementBreteau 1:f3f702086a30 771 __IO uint32_t HcRhStatus;
ClementBreteau 1:f3f702086a30 772 __IO uint32_t HcRhPortStatus1;
ClementBreteau 1:f3f702086a30 773 __IO uint32_t HcRhPortStatus2;
ClementBreteau 1:f3f702086a30 774 uint32_t RESERVED0[40];
ClementBreteau 1:f3f702086a30 775 __I uint32_t Module_ID;
ClementBreteau 1:f3f702086a30 776
ClementBreteau 1:f3f702086a30 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
ClementBreteau 1:f3f702086a30 778 __IO uint32_t OTGIntEn;
ClementBreteau 1:f3f702086a30 779 __O uint32_t OTGIntSet;
ClementBreteau 1:f3f702086a30 780 __O uint32_t OTGIntClr;
ClementBreteau 1:f3f702086a30 781 __IO uint32_t OTGStCtrl;
ClementBreteau 1:f3f702086a30 782 __IO uint32_t OTGTmr;
ClementBreteau 1:f3f702086a30 783 uint32_t RESERVED1[58];
ClementBreteau 1:f3f702086a30 784
ClementBreteau 1:f3f702086a30 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
ClementBreteau 1:f3f702086a30 786 __IO uint32_t USBDevIntEn;
ClementBreteau 1:f3f702086a30 787 __O uint32_t USBDevIntClr;
ClementBreteau 1:f3f702086a30 788 __O uint32_t USBDevIntSet;
ClementBreteau 1:f3f702086a30 789
ClementBreteau 1:f3f702086a30 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
ClementBreteau 1:f3f702086a30 791 __I uint32_t USBCmdData;
ClementBreteau 1:f3f702086a30 792
ClementBreteau 1:f3f702086a30 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
ClementBreteau 1:f3f702086a30 794 __O uint32_t USBTxData;
ClementBreteau 1:f3f702086a30 795 __I uint32_t USBRxPLen;
ClementBreteau 1:f3f702086a30 796 __O uint32_t USBTxPLen;
ClementBreteau 1:f3f702086a30 797 __IO uint32_t USBCtrl;
ClementBreteau 1:f3f702086a30 798 __O uint32_t USBDevIntPri;
ClementBreteau 1:f3f702086a30 799
ClementBreteau 1:f3f702086a30 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
ClementBreteau 1:f3f702086a30 801 __IO uint32_t USBEpIntEn;
ClementBreteau 1:f3f702086a30 802 __O uint32_t USBEpIntClr;
ClementBreteau 1:f3f702086a30 803 __O uint32_t USBEpIntSet;
ClementBreteau 1:f3f702086a30 804 __O uint32_t USBEpIntPri;
ClementBreteau 1:f3f702086a30 805
ClementBreteau 1:f3f702086a30 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
ClementBreteau 1:f3f702086a30 807 __O uint32_t USBEpInd;
ClementBreteau 1:f3f702086a30 808 __IO uint32_t USBMaxPSize;
ClementBreteau 1:f3f702086a30 809
ClementBreteau 1:f3f702086a30 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
ClementBreteau 1:f3f702086a30 811 __O uint32_t USBDMARClr;
ClementBreteau 1:f3f702086a30 812 __O uint32_t USBDMARSet;
ClementBreteau 1:f3f702086a30 813 uint32_t RESERVED2[9];
ClementBreteau 1:f3f702086a30 814 __IO uint32_t USBUDCAH;
ClementBreteau 1:f3f702086a30 815 __I uint32_t USBEpDMASt;
ClementBreteau 1:f3f702086a30 816 __O uint32_t USBEpDMAEn;
ClementBreteau 1:f3f702086a30 817 __O uint32_t USBEpDMADis;
ClementBreteau 1:f3f702086a30 818 __I uint32_t USBDMAIntSt;
ClementBreteau 1:f3f702086a30 819 __IO uint32_t USBDMAIntEn;
ClementBreteau 1:f3f702086a30 820 uint32_t RESERVED3[2];
ClementBreteau 1:f3f702086a30 821 __I uint32_t USBEoTIntSt;
ClementBreteau 1:f3f702086a30 822 __O uint32_t USBEoTIntClr;
ClementBreteau 1:f3f702086a30 823 __O uint32_t USBEoTIntSet;
ClementBreteau 1:f3f702086a30 824 __I uint32_t USBNDDRIntSt;
ClementBreteau 1:f3f702086a30 825 __O uint32_t USBNDDRIntClr;
ClementBreteau 1:f3f702086a30 826 __O uint32_t USBNDDRIntSet;
ClementBreteau 1:f3f702086a30 827 __I uint32_t USBSysErrIntSt;
ClementBreteau 1:f3f702086a30 828 __O uint32_t USBSysErrIntClr;
ClementBreteau 1:f3f702086a30 829 __O uint32_t USBSysErrIntSet;
ClementBreteau 1:f3f702086a30 830 uint32_t RESERVED4[15];
ClementBreteau 1:f3f702086a30 831
ClementBreteau 1:f3f702086a30 832 union {
ClementBreteau 1:f3f702086a30 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
ClementBreteau 1:f3f702086a30 834 __O uint32_t I2C_TX;
ClementBreteau 1:f3f702086a30 835 };
ClementBreteau 1:f3f702086a30 836 __I uint32_t I2C_STS;
ClementBreteau 1:f3f702086a30 837 __IO uint32_t I2C_CTL;
ClementBreteau 1:f3f702086a30 838 __IO uint32_t I2C_CLKHI;
ClementBreteau 1:f3f702086a30 839 __O uint32_t I2C_CLKLO;
ClementBreteau 1:f3f702086a30 840 uint32_t RESERVED5[824];
ClementBreteau 1:f3f702086a30 841
ClementBreteau 1:f3f702086a30 842 union {
ClementBreteau 1:f3f702086a30 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
ClementBreteau 1:f3f702086a30 844 __IO uint32_t OTGClkCtrl;
ClementBreteau 1:f3f702086a30 845 };
ClementBreteau 1:f3f702086a30 846 union {
ClementBreteau 1:f3f702086a30 847 __I uint32_t USBClkSt;
ClementBreteau 1:f3f702086a30 848 __I uint32_t OTGClkSt;
ClementBreteau 1:f3f702086a30 849 };
ClementBreteau 1:f3f702086a30 850 } LPC_USB_TypeDef;
ClementBreteau 1:f3f702086a30 851
ClementBreteau 1:f3f702086a30 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
ClementBreteau 1:f3f702086a30 853 typedef struct
ClementBreteau 1:f3f702086a30 854 {
ClementBreteau 1:f3f702086a30 855 __IO uint32_t MAC1; /* MAC Registers */
ClementBreteau 1:f3f702086a30 856 __IO uint32_t MAC2;
ClementBreteau 1:f3f702086a30 857 __IO uint32_t IPGT;
ClementBreteau 1:f3f702086a30 858 __IO uint32_t IPGR;
ClementBreteau 1:f3f702086a30 859 __IO uint32_t CLRT;
ClementBreteau 1:f3f702086a30 860 __IO uint32_t MAXF;
ClementBreteau 1:f3f702086a30 861 __IO uint32_t SUPP;
ClementBreteau 1:f3f702086a30 862 __IO uint32_t TEST;
ClementBreteau 1:f3f702086a30 863 __IO uint32_t MCFG;
ClementBreteau 1:f3f702086a30 864 __IO uint32_t MCMD;
ClementBreteau 1:f3f702086a30 865 __IO uint32_t MADR;
ClementBreteau 1:f3f702086a30 866 __O uint32_t MWTD;
ClementBreteau 1:f3f702086a30 867 __I uint32_t MRDD;
ClementBreteau 1:f3f702086a30 868 __I uint32_t MIND;
ClementBreteau 1:f3f702086a30 869 uint32_t RESERVED0[2];
ClementBreteau 1:f3f702086a30 870 __IO uint32_t SA0;
ClementBreteau 1:f3f702086a30 871 __IO uint32_t SA1;
ClementBreteau 1:f3f702086a30 872 __IO uint32_t SA2;
ClementBreteau 1:f3f702086a30 873 uint32_t RESERVED1[45];
ClementBreteau 1:f3f702086a30 874 __IO uint32_t Command; /* Control Registers */
ClementBreteau 1:f3f702086a30 875 __I uint32_t Status;
ClementBreteau 1:f3f702086a30 876 __IO uint32_t RxDescriptor;
ClementBreteau 1:f3f702086a30 877 __IO uint32_t RxStatus;
ClementBreteau 1:f3f702086a30 878 __IO uint32_t RxDescriptorNumber;
ClementBreteau 1:f3f702086a30 879 __I uint32_t RxProduceIndex;
ClementBreteau 1:f3f702086a30 880 __IO uint32_t RxConsumeIndex;
ClementBreteau 1:f3f702086a30 881 __IO uint32_t TxDescriptor;
ClementBreteau 1:f3f702086a30 882 __IO uint32_t TxStatus;
ClementBreteau 1:f3f702086a30 883 __IO uint32_t TxDescriptorNumber;
ClementBreteau 1:f3f702086a30 884 __IO uint32_t TxProduceIndex;
ClementBreteau 1:f3f702086a30 885 __I uint32_t TxConsumeIndex;
ClementBreteau 1:f3f702086a30 886 uint32_t RESERVED2[10];
ClementBreteau 1:f3f702086a30 887 __I uint32_t TSV0;
ClementBreteau 1:f3f702086a30 888 __I uint32_t TSV1;
ClementBreteau 1:f3f702086a30 889 __I uint32_t RSV;
ClementBreteau 1:f3f702086a30 890 uint32_t RESERVED3[3];
ClementBreteau 1:f3f702086a30 891 __IO uint32_t FlowControlCounter;
ClementBreteau 1:f3f702086a30 892 __I uint32_t FlowControlStatus;
ClementBreteau 1:f3f702086a30 893 uint32_t RESERVED4[34];
ClementBreteau 1:f3f702086a30 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
ClementBreteau 1:f3f702086a30 895 __IO uint32_t RxFilterWoLStatus;
ClementBreteau 1:f3f702086a30 896 __IO uint32_t RxFilterWoLClear;
ClementBreteau 1:f3f702086a30 897 uint32_t RESERVED5;
ClementBreteau 1:f3f702086a30 898 __IO uint32_t HashFilterL;
ClementBreteau 1:f3f702086a30 899 __IO uint32_t HashFilterH;
ClementBreteau 1:f3f702086a30 900 uint32_t RESERVED6[882];
ClementBreteau 1:f3f702086a30 901 __I uint32_t IntStatus; /* Module Control Registers */
ClementBreteau 1:f3f702086a30 902 __IO uint32_t IntEnable;
ClementBreteau 1:f3f702086a30 903 __O uint32_t IntClear;
ClementBreteau 1:f3f702086a30 904 __O uint32_t IntSet;
ClementBreteau 1:f3f702086a30 905 uint32_t RESERVED7;
ClementBreteau 1:f3f702086a30 906 __IO uint32_t PowerDown;
ClementBreteau 1:f3f702086a30 907 uint32_t RESERVED8;
ClementBreteau 1:f3f702086a30 908 __IO uint32_t Module_ID;
ClementBreteau 1:f3f702086a30 909 } LPC_EMAC_TypeDef;
ClementBreteau 1:f3f702086a30 910
ClementBreteau 1:f3f702086a30 911 #if defined ( __CC_ARM )
ClementBreteau 1:f3f702086a30 912 #pragma no_anon_unions
ClementBreteau 1:f3f702086a30 913 #endif
ClementBreteau 1:f3f702086a30 914
ClementBreteau 1:f3f702086a30 915
ClementBreteau 1:f3f702086a30 916 /******************************************************************************/
ClementBreteau 1:f3f702086a30 917 /* Peripheral memory map */
ClementBreteau 1:f3f702086a30 918 /******************************************************************************/
ClementBreteau 1:f3f702086a30 919 /* Base addresses */
ClementBreteau 1:f3f702086a30 920 #define LPC_FLASH_BASE (0x00000000UL)
ClementBreteau 1:f3f702086a30 921 #define LPC_RAM_BASE (0x10000000UL)
ClementBreteau 1:f3f702086a30 922 #define LPC_GPIO_BASE (0x2009C000UL)
ClementBreteau 1:f3f702086a30 923 #define LPC_APB0_BASE (0x40000000UL)
ClementBreteau 1:f3f702086a30 924 #define LPC_APB1_BASE (0x40080000UL)
ClementBreteau 1:f3f702086a30 925 #define LPC_AHB_BASE (0x50000000UL)
ClementBreteau 1:f3f702086a30 926 #define LPC_CM3_BASE (0xE0000000UL)
ClementBreteau 1:f3f702086a30 927
ClementBreteau 1:f3f702086a30 928 /* APB0 peripherals */
ClementBreteau 1:f3f702086a30 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
ClementBreteau 1:f3f702086a30 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
ClementBreteau 1:f3f702086a30 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
ClementBreteau 1:f3f702086a30 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
ClementBreteau 1:f3f702086a30 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
ClementBreteau 1:f3f702086a30 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
ClementBreteau 1:f3f702086a30 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
ClementBreteau 1:f3f702086a30 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
ClementBreteau 1:f3f702086a30 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
ClementBreteau 1:f3f702086a30 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
ClementBreteau 1:f3f702086a30 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
ClementBreteau 1:f3f702086a30 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
ClementBreteau 1:f3f702086a30 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
ClementBreteau 1:f3f702086a30 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
ClementBreteau 1:f3f702086a30 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
ClementBreteau 1:f3f702086a30 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
ClementBreteau 1:f3f702086a30 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
ClementBreteau 1:f3f702086a30 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
ClementBreteau 1:f3f702086a30 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
ClementBreteau 1:f3f702086a30 948
ClementBreteau 1:f3f702086a30 949 /* APB1 peripherals */
ClementBreteau 1:f3f702086a30 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
ClementBreteau 1:f3f702086a30 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
ClementBreteau 1:f3f702086a30 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
ClementBreteau 1:f3f702086a30 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
ClementBreteau 1:f3f702086a30 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
ClementBreteau 1:f3f702086a30 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
ClementBreteau 1:f3f702086a30 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
ClementBreteau 1:f3f702086a30 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
ClementBreteau 1:f3f702086a30 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
ClementBreteau 1:f3f702086a30 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
ClementBreteau 1:f3f702086a30 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
ClementBreteau 1:f3f702086a30 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
ClementBreteau 1:f3f702086a30 962
ClementBreteau 1:f3f702086a30 963 /* AHB peripherals */
ClementBreteau 1:f3f702086a30 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
ClementBreteau 1:f3f702086a30 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
ClementBreteau 1:f3f702086a30 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
ClementBreteau 1:f3f702086a30 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
ClementBreteau 1:f3f702086a30 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
ClementBreteau 1:f3f702086a30 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
ClementBreteau 1:f3f702086a30 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
ClementBreteau 1:f3f702086a30 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
ClementBreteau 1:f3f702086a30 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
ClementBreteau 1:f3f702086a30 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
ClementBreteau 1:f3f702086a30 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
ClementBreteau 1:f3f702086a30 975
ClementBreteau 1:f3f702086a30 976 /* GPIOs */
ClementBreteau 1:f3f702086a30 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
ClementBreteau 1:f3f702086a30 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
ClementBreteau 1:f3f702086a30 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
ClementBreteau 1:f3f702086a30 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
ClementBreteau 1:f3f702086a30 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
ClementBreteau 1:f3f702086a30 982
ClementBreteau 1:f3f702086a30 983
ClementBreteau 1:f3f702086a30 984 /******************************************************************************/
ClementBreteau 1:f3f702086a30 985 /* Peripheral declaration */
ClementBreteau 1:f3f702086a30 986 /******************************************************************************/
ClementBreteau 1:f3f702086a30 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
ClementBreteau 1:f3f702086a30 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
ClementBreteau 1:f3f702086a30 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
ClementBreteau 1:f3f702086a30 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
ClementBreteau 1:f3f702086a30 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
ClementBreteau 1:f3f702086a30 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
ClementBreteau 1:f3f702086a30 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
ClementBreteau 1:f3f702086a30 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
ClementBreteau 1:f3f702086a30 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
ClementBreteau 1:f3f702086a30 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
ClementBreteau 1:f3f702086a30 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
ClementBreteau 1:f3f702086a30 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
ClementBreteau 1:f3f702086a30 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
ClementBreteau 1:f3f702086a30 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
ClementBreteau 1:f3f702086a30 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
ClementBreteau 1:f3f702086a30 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
ClementBreteau 1:f3f702086a30 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
ClementBreteau 1:f3f702086a30 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
ClementBreteau 1:f3f702086a30 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
ClementBreteau 1:f3f702086a30 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
ClementBreteau 1:f3f702086a30 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
ClementBreteau 1:f3f702086a30 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
ClementBreteau 1:f3f702086a30 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
ClementBreteau 1:f3f702086a30 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
ClementBreteau 1:f3f702086a30 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
ClementBreteau 1:f3f702086a30 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
ClementBreteau 1:f3f702086a30 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
ClementBreteau 1:f3f702086a30 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
ClementBreteau 1:f3f702086a30 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
ClementBreteau 1:f3f702086a30 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
ClementBreteau 1:f3f702086a30 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
ClementBreteau 1:f3f702086a30 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
ClementBreteau 1:f3f702086a30 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
ClementBreteau 1:f3f702086a30 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
ClementBreteau 1:f3f702086a30 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
ClementBreteau 1:f3f702086a30 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
ClementBreteau 1:f3f702086a30 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
ClementBreteau 1:f3f702086a30 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
ClementBreteau 1:f3f702086a30 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
ClementBreteau 1:f3f702086a30 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
ClementBreteau 1:f3f702086a30 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
ClementBreteau 1:f3f702086a30 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
ClementBreteau 1:f3f702086a30 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
ClementBreteau 1:f3f702086a30 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
ClementBreteau 1:f3f702086a30 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
ClementBreteau 1:f3f702086a30 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
ClementBreteau 1:f3f702086a30 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
ClementBreteau 1:f3f702086a30 1034
ClementBreteau 1:f3f702086a30 1035 #endif // __LPC17xx_H__