Strategie_13h30
Fork of CRAC-Strat_2017_homologation_gros_rob by
mbed/LPC1768/ARM/LPC1768.sct@22:8dec8824a6f7, 2017-05-25 (annotated)
- Committer:
- matthieuvignon
- Date:
- Thu May 25 11:30:31 2017 +0000
- Revision:
- 22:8dec8824a6f7
- Parent:
- 0:ad97421fb1fb
13h30_Strategie
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
antbig | 0:ad97421fb1fb | 1 | |
antbig | 0:ad97421fb1fb | 2 | LR_IROM1 0x00000000 0x80000 { ; load region size_region |
antbig | 0:ad97421fb1fb | 3 | ER_IROM1 0x00000000 0x80000 { ; load address = execution address |
antbig | 0:ad97421fb1fb | 4 | *.o (RESET, +First) |
antbig | 0:ad97421fb1fb | 5 | *(InRoot$$Sections) |
antbig | 0:ad97421fb1fb | 6 | .ANY (+RO) |
antbig | 0:ad97421fb1fb | 7 | } |
antbig | 0:ad97421fb1fb | 8 | ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8 |
antbig | 0:ad97421fb1fb | 9 | ; 32KB - 0xC8 = 0x7F38 |
antbig | 0:ad97421fb1fb | 10 | RW_IRAM1 0x100000C8 0x7F38 { |
antbig | 0:ad97421fb1fb | 11 | .ANY (+RW +ZI) |
antbig | 0:ad97421fb1fb | 12 | } |
antbig | 0:ad97421fb1fb | 13 | RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM |
antbig | 0:ad97421fb1fb | 14 | .ANY (AHBSRAM0) |
antbig | 0:ad97421fb1fb | 15 | } |
antbig | 0:ad97421fb1fb | 16 | RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM |
antbig | 0:ad97421fb1fb | 17 | .ANY (AHBSRAM1) |
antbig | 0:ad97421fb1fb | 18 | } |
antbig | 0:ad97421fb1fb | 19 | RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM |
antbig | 0:ad97421fb1fb | 20 | .ANY (CANRAM) |
antbig | 0:ad97421fb1fb | 21 | } |
antbig | 0:ad97421fb1fb | 22 | } |