CRAC Team / CRAC-Strat_2017_homologation_gros_rob_testAck

homologation gros robot et test avec les ack de la carte a tout faire

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mbed/LPC1768/core_cmInstr.h@21:7c60d6dfcab5, 2017-05-25 (annotated)

Committer:
ClementBreteau
Date:
Thu May 25 06:36:48 2017 +0000
Revision:
21:7c60d6dfcab5
Parent:
0:ad97421fb1fb 
homologation gros robot avec test au niveau des ack

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antbig 0:ad97421fb1fb 1 /**************************************************************************//**
antbig 0:ad97421fb1fb 2 * @file core_cmInstr.h
antbig 0:ad97421fb1fb 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
antbig 0:ad97421fb1fb 4 * @version V3.00
antbig 0:ad97421fb1fb 5 * @date 09. December 2011
antbig 0:ad97421fb1fb 6 *
antbig 0:ad97421fb1fb 7 * @note
antbig 0:ad97421fb1fb 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 9 *
antbig 0:ad97421fb1fb 10 * @par
antbig 0:ad97421fb1fb 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
antbig 0:ad97421fb1fb 12 * processor based microcontrollers. This file can be freely distributed
antbig 0:ad97421fb1fb 13 * within development tools that are supporting such ARM based processors.
antbig 0:ad97421fb1fb 14 *
antbig 0:ad97421fb1fb 15 * @par
antbig 0:ad97421fb1fb 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
antbig 0:ad97421fb1fb 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
antbig 0:ad97421fb1fb 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
antbig 0:ad97421fb1fb 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
antbig 0:ad97421fb1fb 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
antbig 0:ad97421fb1fb 21 *
antbig 0:ad97421fb1fb 22 ******************************************************************************/
antbig 0:ad97421fb1fb 23
antbig 0:ad97421fb1fb 24 #ifndef __CORE_CMINSTR_H
antbig 0:ad97421fb1fb 25 #define __CORE_CMINSTR_H
antbig 0:ad97421fb1fb 26
antbig 0:ad97421fb1fb 27
antbig 0:ad97421fb1fb 28 /* ########################## Core Instruction Access ######################### */
antbig 0:ad97421fb1fb 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
antbig 0:ad97421fb1fb 30 Access to dedicated instructions
antbig 0:ad97421fb1fb 31 @{
antbig 0:ad97421fb1fb 32 */
antbig 0:ad97421fb1fb 33
antbig 0:ad97421fb1fb 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
antbig 0:ad97421fb1fb 35 /* ARM armcc specific functions */
antbig 0:ad97421fb1fb 36
antbig 0:ad97421fb1fb 37 #if (__ARMCC_VERSION < 400677)
antbig 0:ad97421fb1fb 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
antbig 0:ad97421fb1fb 39 #endif
antbig 0:ad97421fb1fb 40
antbig 0:ad97421fb1fb 41
antbig 0:ad97421fb1fb 42 /** \brief No Operation
antbig 0:ad97421fb1fb 43
antbig 0:ad97421fb1fb 44 No Operation does nothing. This instruction can be used for code alignment purposes.
antbig 0:ad97421fb1fb 45 */
antbig 0:ad97421fb1fb 46 #define __NOP __nop
antbig 0:ad97421fb1fb 47
antbig 0:ad97421fb1fb 48
antbig 0:ad97421fb1fb 49 /** \brief Wait For Interrupt
antbig 0:ad97421fb1fb 50
antbig 0:ad97421fb1fb 51 Wait For Interrupt is a hint instruction that suspends execution
antbig 0:ad97421fb1fb 52 until one of a number of events occurs.
antbig 0:ad97421fb1fb 53 */
antbig 0:ad97421fb1fb 54 #define __WFI __wfi
antbig 0:ad97421fb1fb 55
antbig 0:ad97421fb1fb 56
antbig 0:ad97421fb1fb 57 /** \brief Wait For Event
antbig 0:ad97421fb1fb 58
antbig 0:ad97421fb1fb 59 Wait For Event is a hint instruction that permits the processor to enter
antbig 0:ad97421fb1fb 60 a low-power state until one of a number of events occurs.
antbig 0:ad97421fb1fb 61 */
antbig 0:ad97421fb1fb 62 #define __WFE __wfe
antbig 0:ad97421fb1fb 63
antbig 0:ad97421fb1fb 64
antbig 0:ad97421fb1fb 65 /** \brief Send Event
antbig 0:ad97421fb1fb 66
antbig 0:ad97421fb1fb 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
antbig 0:ad97421fb1fb 68 */
antbig 0:ad97421fb1fb 69 #define __SEV __sev
antbig 0:ad97421fb1fb 70
antbig 0:ad97421fb1fb 71
antbig 0:ad97421fb1fb 72 /** \brief Instruction Synchronization Barrier
antbig 0:ad97421fb1fb 73
antbig 0:ad97421fb1fb 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
antbig 0:ad97421fb1fb 75 so that all instructions following the ISB are fetched from cache or
antbig 0:ad97421fb1fb 76 memory, after the instruction has been completed.
antbig 0:ad97421fb1fb 77 */
antbig 0:ad97421fb1fb 78 #define __ISB() __isb(0xF)
antbig 0:ad97421fb1fb 79
antbig 0:ad97421fb1fb 80
antbig 0:ad97421fb1fb 81 /** \brief Data Synchronization Barrier
antbig 0:ad97421fb1fb 82
antbig 0:ad97421fb1fb 83 This function acts as a special kind of Data Memory Barrier.
antbig 0:ad97421fb1fb 84 It completes when all explicit memory accesses before this instruction complete.
antbig 0:ad97421fb1fb 85 */
antbig 0:ad97421fb1fb 86 #define __DSB() __dsb(0xF)
antbig 0:ad97421fb1fb 87
antbig 0:ad97421fb1fb 88
antbig 0:ad97421fb1fb 89 /** \brief Data Memory Barrier
antbig 0:ad97421fb1fb 90
antbig 0:ad97421fb1fb 91 This function ensures the apparent order of the explicit memory operations before
antbig 0:ad97421fb1fb 92 and after the instruction, without ensuring their completion.
antbig 0:ad97421fb1fb 93 */
antbig 0:ad97421fb1fb 94 #define __DMB() __dmb(0xF)
antbig 0:ad97421fb1fb 95
antbig 0:ad97421fb1fb 96
antbig 0:ad97421fb1fb 97 /** \brief Reverse byte order (32 bit)
antbig 0:ad97421fb1fb 98
antbig 0:ad97421fb1fb 99 This function reverses the byte order in integer value.
antbig 0:ad97421fb1fb 100
antbig 0:ad97421fb1fb 101 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 102 \return Reversed value
antbig 0:ad97421fb1fb 103 */
antbig 0:ad97421fb1fb 104 #define __REV __rev
antbig 0:ad97421fb1fb 105
antbig 0:ad97421fb1fb 106
antbig 0:ad97421fb1fb 107 /** \brief Reverse byte order (16 bit)
antbig 0:ad97421fb1fb 108
antbig 0:ad97421fb1fb 109 This function reverses the byte order in two unsigned short values.
antbig 0:ad97421fb1fb 110
antbig 0:ad97421fb1fb 111 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 112 \return Reversed value
antbig 0:ad97421fb1fb 113 */
antbig 0:ad97421fb1fb 114 static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
antbig 0:ad97421fb1fb 115 {
antbig 0:ad97421fb1fb 116 rev16 r0, r0
antbig 0:ad97421fb1fb 117 bx lr
antbig 0:ad97421fb1fb 118 }
antbig 0:ad97421fb1fb 119
antbig 0:ad97421fb1fb 120
antbig 0:ad97421fb1fb 121 /** \brief Reverse byte order in signed short value
antbig 0:ad97421fb1fb 122
antbig 0:ad97421fb1fb 123 This function reverses the byte order in a signed short value with sign extension to integer.
antbig 0:ad97421fb1fb 124
antbig 0:ad97421fb1fb 125 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 126 \return Reversed value
antbig 0:ad97421fb1fb 127 */
antbig 0:ad97421fb1fb 128 static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
antbig 0:ad97421fb1fb 129 {
antbig 0:ad97421fb1fb 130 revsh r0, r0
antbig 0:ad97421fb1fb 131 bx lr
antbig 0:ad97421fb1fb 132 }
antbig 0:ad97421fb1fb 133
antbig 0:ad97421fb1fb 134
antbig 0:ad97421fb1fb 135 #if (__CORTEX_M >= 0x03)
antbig 0:ad97421fb1fb 136
antbig 0:ad97421fb1fb 137 /** \brief Reverse bit order of value
antbig 0:ad97421fb1fb 138
antbig 0:ad97421fb1fb 139 This function reverses the bit order of the given value.
antbig 0:ad97421fb1fb 140
antbig 0:ad97421fb1fb 141 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 142 \return Reversed value
antbig 0:ad97421fb1fb 143 */
antbig 0:ad97421fb1fb 144 #define __RBIT __rbit
antbig 0:ad97421fb1fb 145
antbig 0:ad97421fb1fb 146
antbig 0:ad97421fb1fb 147 /** \brief LDR Exclusive (8 bit)
antbig 0:ad97421fb1fb 148
antbig 0:ad97421fb1fb 149 This function performs a exclusive LDR command for 8 bit value.
antbig 0:ad97421fb1fb 150
antbig 0:ad97421fb1fb 151 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 152 \return value of type uint8_t at (*ptr)
antbig 0:ad97421fb1fb 153 */
antbig 0:ad97421fb1fb 154 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
antbig 0:ad97421fb1fb 155
antbig 0:ad97421fb1fb 156
antbig 0:ad97421fb1fb 157 /** \brief LDR Exclusive (16 bit)
antbig 0:ad97421fb1fb 158
antbig 0:ad97421fb1fb 159 This function performs a exclusive LDR command for 16 bit values.
antbig 0:ad97421fb1fb 160
antbig 0:ad97421fb1fb 161 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 162 \return value of type uint16_t at (*ptr)
antbig 0:ad97421fb1fb 163 */
antbig 0:ad97421fb1fb 164 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
antbig 0:ad97421fb1fb 165
antbig 0:ad97421fb1fb 166
antbig 0:ad97421fb1fb 167 /** \brief LDR Exclusive (32 bit)
antbig 0:ad97421fb1fb 168
antbig 0:ad97421fb1fb 169 This function performs a exclusive LDR command for 32 bit values.
antbig 0:ad97421fb1fb 170
antbig 0:ad97421fb1fb 171 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 172 \return value of type uint32_t at (*ptr)
antbig 0:ad97421fb1fb 173 */
antbig 0:ad97421fb1fb 174 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
antbig 0:ad97421fb1fb 175
antbig 0:ad97421fb1fb 176
antbig 0:ad97421fb1fb 177 /** \brief STR Exclusive (8 bit)
antbig 0:ad97421fb1fb 178
antbig 0:ad97421fb1fb 179 This function performs a exclusive STR command for 8 bit values.
antbig 0:ad97421fb1fb 180
antbig 0:ad97421fb1fb 181 \param [in] value Value to store
antbig 0:ad97421fb1fb 182 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 183 \return 0 Function succeeded
antbig 0:ad97421fb1fb 184 \return 1 Function failed
antbig 0:ad97421fb1fb 185 */
antbig 0:ad97421fb1fb 186 #define __STREXB(value, ptr) __strex(value, ptr)
antbig 0:ad97421fb1fb 187
antbig 0:ad97421fb1fb 188
antbig 0:ad97421fb1fb 189 /** \brief STR Exclusive (16 bit)
antbig 0:ad97421fb1fb 190
antbig 0:ad97421fb1fb 191 This function performs a exclusive STR command for 16 bit values.
antbig 0:ad97421fb1fb 192
antbig 0:ad97421fb1fb 193 \param [in] value Value to store
antbig 0:ad97421fb1fb 194 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 195 \return 0 Function succeeded
antbig 0:ad97421fb1fb 196 \return 1 Function failed
antbig 0:ad97421fb1fb 197 */
antbig 0:ad97421fb1fb 198 #define __STREXH(value, ptr) __strex(value, ptr)
antbig 0:ad97421fb1fb 199
antbig 0:ad97421fb1fb 200
antbig 0:ad97421fb1fb 201 /** \brief STR Exclusive (32 bit)
antbig 0:ad97421fb1fb 202
antbig 0:ad97421fb1fb 203 This function performs a exclusive STR command for 32 bit values.
antbig 0:ad97421fb1fb 204
antbig 0:ad97421fb1fb 205 \param [in] value Value to store
antbig 0:ad97421fb1fb 206 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 207 \return 0 Function succeeded
antbig 0:ad97421fb1fb 208 \return 1 Function failed
antbig 0:ad97421fb1fb 209 */
antbig 0:ad97421fb1fb 210 #define __STREXW(value, ptr) __strex(value, ptr)
antbig 0:ad97421fb1fb 211
antbig 0:ad97421fb1fb 212
antbig 0:ad97421fb1fb 213 /** \brief Remove the exclusive lock
antbig 0:ad97421fb1fb 214
antbig 0:ad97421fb1fb 215 This function removes the exclusive lock which is created by LDREX.
antbig 0:ad97421fb1fb 216
antbig 0:ad97421fb1fb 217 */
antbig 0:ad97421fb1fb 218 #define __CLREX __clrex
antbig 0:ad97421fb1fb 219
antbig 0:ad97421fb1fb 220
antbig 0:ad97421fb1fb 221 /** \brief Signed Saturate
antbig 0:ad97421fb1fb 222
antbig 0:ad97421fb1fb 223 This function saturates a signed value.
antbig 0:ad97421fb1fb 224
antbig 0:ad97421fb1fb 225 \param [in] value Value to be saturated
antbig 0:ad97421fb1fb 226 \param [in] sat Bit position to saturate to (1..32)
antbig 0:ad97421fb1fb 227 \return Saturated value
antbig 0:ad97421fb1fb 228 */
antbig 0:ad97421fb1fb 229 #define __SSAT __ssat
antbig 0:ad97421fb1fb 230
antbig 0:ad97421fb1fb 231
antbig 0:ad97421fb1fb 232 /** \brief Unsigned Saturate
antbig 0:ad97421fb1fb 233
antbig 0:ad97421fb1fb 234 This function saturates an unsigned value.
antbig 0:ad97421fb1fb 235
antbig 0:ad97421fb1fb 236 \param [in] value Value to be saturated
antbig 0:ad97421fb1fb 237 \param [in] sat Bit position to saturate to (0..31)
antbig 0:ad97421fb1fb 238 \return Saturated value
antbig 0:ad97421fb1fb 239 */
antbig 0:ad97421fb1fb 240 #define __USAT __usat
antbig 0:ad97421fb1fb 241
antbig 0:ad97421fb1fb 242
antbig 0:ad97421fb1fb 243 /** \brief Count leading zeros
antbig 0:ad97421fb1fb 244
antbig 0:ad97421fb1fb 245 This function counts the number of leading zeros of a data value.
antbig 0:ad97421fb1fb 246
antbig 0:ad97421fb1fb 247 \param [in] value Value to count the leading zeros
antbig 0:ad97421fb1fb 248 \return number of leading zeros in value
antbig 0:ad97421fb1fb 249 */
antbig 0:ad97421fb1fb 250 #define __CLZ __clz
antbig 0:ad97421fb1fb 251
antbig 0:ad97421fb1fb 252 #endif /* (__CORTEX_M >= 0x03) */
antbig 0:ad97421fb1fb 253
antbig 0:ad97421fb1fb 254
antbig 0:ad97421fb1fb 255
antbig 0:ad97421fb1fb 256 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
antbig 0:ad97421fb1fb 257 /* IAR iccarm specific functions */
antbig 0:ad97421fb1fb 258
antbig 0:ad97421fb1fb 259 #include <cmsis_iar.h>
antbig 0:ad97421fb1fb 260
antbig 0:ad97421fb1fb 261
antbig 0:ad97421fb1fb 262 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
antbig 0:ad97421fb1fb 263 /* GNU gcc specific functions */
antbig 0:ad97421fb1fb 264
antbig 0:ad97421fb1fb 265 /** \brief No Operation
antbig 0:ad97421fb1fb 266
antbig 0:ad97421fb1fb 267 No Operation does nothing. This instruction can be used for code alignment purposes.
antbig 0:ad97421fb1fb 268 */
antbig 0:ad97421fb1fb 269 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
antbig 0:ad97421fb1fb 270 {
antbig 0:ad97421fb1fb 271 __ASM volatile ("nop");
antbig 0:ad97421fb1fb 272 }
antbig 0:ad97421fb1fb 273
antbig 0:ad97421fb1fb 274
antbig 0:ad97421fb1fb 275 /** \brief Wait For Interrupt
antbig 0:ad97421fb1fb 276
antbig 0:ad97421fb1fb 277 Wait For Interrupt is a hint instruction that suspends execution
antbig 0:ad97421fb1fb 278 until one of a number of events occurs.
antbig 0:ad97421fb1fb 279 */
antbig 0:ad97421fb1fb 280 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
antbig 0:ad97421fb1fb 281 {
antbig 0:ad97421fb1fb 282 __ASM volatile ("wfi");
antbig 0:ad97421fb1fb 283 }
antbig 0:ad97421fb1fb 284
antbig 0:ad97421fb1fb 285
antbig 0:ad97421fb1fb 286 /** \brief Wait For Event
antbig 0:ad97421fb1fb 287
antbig 0:ad97421fb1fb 288 Wait For Event is a hint instruction that permits the processor to enter
antbig 0:ad97421fb1fb 289 a low-power state until one of a number of events occurs.
antbig 0:ad97421fb1fb 290 */
antbig 0:ad97421fb1fb 291 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
antbig 0:ad97421fb1fb 292 {
antbig 0:ad97421fb1fb 293 __ASM volatile ("wfe");
antbig 0:ad97421fb1fb 294 }
antbig 0:ad97421fb1fb 295
antbig 0:ad97421fb1fb 296
antbig 0:ad97421fb1fb 297 /** \brief Send Event
antbig 0:ad97421fb1fb 298
antbig 0:ad97421fb1fb 299 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
antbig 0:ad97421fb1fb 300 */
antbig 0:ad97421fb1fb 301 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
antbig 0:ad97421fb1fb 302 {
antbig 0:ad97421fb1fb 303 __ASM volatile ("sev");
antbig 0:ad97421fb1fb 304 }
antbig 0:ad97421fb1fb 305
antbig 0:ad97421fb1fb 306
antbig 0:ad97421fb1fb 307 /** \brief Instruction Synchronization Barrier
antbig 0:ad97421fb1fb 308
antbig 0:ad97421fb1fb 309 Instruction Synchronization Barrier flushes the pipeline in the processor,
antbig 0:ad97421fb1fb 310 so that all instructions following the ISB are fetched from cache or
antbig 0:ad97421fb1fb 311 memory, after the instruction has been completed.
antbig 0:ad97421fb1fb 312 */
antbig 0:ad97421fb1fb 313 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
antbig 0:ad97421fb1fb 314 {
antbig 0:ad97421fb1fb 315 __ASM volatile ("isb");
antbig 0:ad97421fb1fb 316 }
antbig 0:ad97421fb1fb 317
antbig 0:ad97421fb1fb 318
antbig 0:ad97421fb1fb 319 /** \brief Data Synchronization Barrier
antbig 0:ad97421fb1fb 320
antbig 0:ad97421fb1fb 321 This function acts as a special kind of Data Memory Barrier.
antbig 0:ad97421fb1fb 322 It completes when all explicit memory accesses before this instruction complete.
antbig 0:ad97421fb1fb 323 */
antbig 0:ad97421fb1fb 324 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
antbig 0:ad97421fb1fb 325 {
antbig 0:ad97421fb1fb 326 __ASM volatile ("dsb");
antbig 0:ad97421fb1fb 327 }
antbig 0:ad97421fb1fb 328
antbig 0:ad97421fb1fb 329
antbig 0:ad97421fb1fb 330 /** \brief Data Memory Barrier
antbig 0:ad97421fb1fb 331
antbig 0:ad97421fb1fb 332 This function ensures the apparent order of the explicit memory operations before
antbig 0:ad97421fb1fb 333 and after the instruction, without ensuring their completion.
antbig 0:ad97421fb1fb 334 */
antbig 0:ad97421fb1fb 335 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
antbig 0:ad97421fb1fb 336 {
antbig 0:ad97421fb1fb 337 __ASM volatile ("dmb");
antbig 0:ad97421fb1fb 338 }
antbig 0:ad97421fb1fb 339
antbig 0:ad97421fb1fb 340
antbig 0:ad97421fb1fb 341 /** \brief Reverse byte order (32 bit)
antbig 0:ad97421fb1fb 342
antbig 0:ad97421fb1fb 343 This function reverses the byte order in integer value.
antbig 0:ad97421fb1fb 344
antbig 0:ad97421fb1fb 345 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 346 \return Reversed value
antbig 0:ad97421fb1fb 347 */
antbig 0:ad97421fb1fb 348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
antbig 0:ad97421fb1fb 349 {
antbig 0:ad97421fb1fb 350 uint32_t result;
antbig 0:ad97421fb1fb 351
antbig 0:ad97421fb1fb 352 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
antbig 0:ad97421fb1fb 353 return(result);
antbig 0:ad97421fb1fb 354 }
antbig 0:ad97421fb1fb 355
antbig 0:ad97421fb1fb 356
antbig 0:ad97421fb1fb 357 /** \brief Reverse byte order (16 bit)
antbig 0:ad97421fb1fb 358
antbig 0:ad97421fb1fb 359 This function reverses the byte order in two unsigned short values.
antbig 0:ad97421fb1fb 360
antbig 0:ad97421fb1fb 361 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 362 \return Reversed value
antbig 0:ad97421fb1fb 363 */
antbig 0:ad97421fb1fb 364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
antbig 0:ad97421fb1fb 365 {
antbig 0:ad97421fb1fb 366 uint32_t result;
antbig 0:ad97421fb1fb 367
antbig 0:ad97421fb1fb 368 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
antbig 0:ad97421fb1fb 369 return(result);
antbig 0:ad97421fb1fb 370 }
antbig 0:ad97421fb1fb 371
antbig 0:ad97421fb1fb 372
antbig 0:ad97421fb1fb 373 /** \brief Reverse byte order in signed short value
antbig 0:ad97421fb1fb 374
antbig 0:ad97421fb1fb 375 This function reverses the byte order in a signed short value with sign extension to integer.
antbig 0:ad97421fb1fb 376
antbig 0:ad97421fb1fb 377 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 378 \return Reversed value
antbig 0:ad97421fb1fb 379 */
antbig 0:ad97421fb1fb 380 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
antbig 0:ad97421fb1fb 381 {
antbig 0:ad97421fb1fb 382 uint32_t result;
antbig 0:ad97421fb1fb 383
antbig 0:ad97421fb1fb 384 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
antbig 0:ad97421fb1fb 385 return(result);
antbig 0:ad97421fb1fb 386 }
antbig 0:ad97421fb1fb 387
antbig 0:ad97421fb1fb 388
antbig 0:ad97421fb1fb 389 #if (__CORTEX_M >= 0x03)
antbig 0:ad97421fb1fb 390
antbig 0:ad97421fb1fb 391 /** \brief Reverse bit order of value
antbig 0:ad97421fb1fb 392
antbig 0:ad97421fb1fb 393 This function reverses the bit order of the given value.
antbig 0:ad97421fb1fb 394
antbig 0:ad97421fb1fb 395 \param [in] value Value to reverse
antbig 0:ad97421fb1fb 396 \return Reversed value
antbig 0:ad97421fb1fb 397 */
antbig 0:ad97421fb1fb 398 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
antbig 0:ad97421fb1fb 399 {
antbig 0:ad97421fb1fb 400 uint32_t result;
antbig 0:ad97421fb1fb 401
antbig 0:ad97421fb1fb 402 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
antbig 0:ad97421fb1fb 403 return(result);
antbig 0:ad97421fb1fb 404 }
antbig 0:ad97421fb1fb 405
antbig 0:ad97421fb1fb 406
antbig 0:ad97421fb1fb 407 /** \brief LDR Exclusive (8 bit)
antbig 0:ad97421fb1fb 408
antbig 0:ad97421fb1fb 409 This function performs a exclusive LDR command for 8 bit value.
antbig 0:ad97421fb1fb 410
antbig 0:ad97421fb1fb 411 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 412 \return value of type uint8_t at (*ptr)
antbig 0:ad97421fb1fb 413 */
antbig 0:ad97421fb1fb 414 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
antbig 0:ad97421fb1fb 415 {
antbig 0:ad97421fb1fb 416 uint8_t result;
antbig 0:ad97421fb1fb 417
antbig 0:ad97421fb1fb 418 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
antbig 0:ad97421fb1fb 419 return(result);
antbig 0:ad97421fb1fb 420 }
antbig 0:ad97421fb1fb 421
antbig 0:ad97421fb1fb 422
antbig 0:ad97421fb1fb 423 /** \brief LDR Exclusive (16 bit)
antbig 0:ad97421fb1fb 424
antbig 0:ad97421fb1fb 425 This function performs a exclusive LDR command for 16 bit values.
antbig 0:ad97421fb1fb 426
antbig 0:ad97421fb1fb 427 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 428 \return value of type uint16_t at (*ptr)
antbig 0:ad97421fb1fb 429 */
antbig 0:ad97421fb1fb 430 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
antbig 0:ad97421fb1fb 431 {
antbig 0:ad97421fb1fb 432 uint16_t result;
antbig 0:ad97421fb1fb 433
antbig 0:ad97421fb1fb 434 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
antbig 0:ad97421fb1fb 435 return(result);
antbig 0:ad97421fb1fb 436 }
antbig 0:ad97421fb1fb 437
antbig 0:ad97421fb1fb 438
antbig 0:ad97421fb1fb 439 /** \brief LDR Exclusive (32 bit)
antbig 0:ad97421fb1fb 440
antbig 0:ad97421fb1fb 441 This function performs a exclusive LDR command for 32 bit values.
antbig 0:ad97421fb1fb 442
antbig 0:ad97421fb1fb 443 \param [in] ptr Pointer to data
antbig 0:ad97421fb1fb 444 \return value of type uint32_t at (*ptr)
antbig 0:ad97421fb1fb 445 */
antbig 0:ad97421fb1fb 446 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
antbig 0:ad97421fb1fb 447 {
antbig 0:ad97421fb1fb 448 uint32_t result;
antbig 0:ad97421fb1fb 449
antbig 0:ad97421fb1fb 450 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
antbig 0:ad97421fb1fb 451 return(result);
antbig 0:ad97421fb1fb 452 }
antbig 0:ad97421fb1fb 453
antbig 0:ad97421fb1fb 454
antbig 0:ad97421fb1fb 455 /** \brief STR Exclusive (8 bit)
antbig 0:ad97421fb1fb 456
antbig 0:ad97421fb1fb 457 This function performs a exclusive STR command for 8 bit values.
antbig 0:ad97421fb1fb 458
antbig 0:ad97421fb1fb 459 \param [in] value Value to store
antbig 0:ad97421fb1fb 460 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 461 \return 0 Function succeeded
antbig 0:ad97421fb1fb 462 \return 1 Function failed
antbig 0:ad97421fb1fb 463 */
antbig 0:ad97421fb1fb 464 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
antbig 0:ad97421fb1fb 465 {
antbig 0:ad97421fb1fb 466 uint32_t result;
antbig 0:ad97421fb1fb 467
antbig 0:ad97421fb1fb 468 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
antbig 0:ad97421fb1fb 469 return(result);
antbig 0:ad97421fb1fb 470 }
antbig 0:ad97421fb1fb 471
antbig 0:ad97421fb1fb 472
antbig 0:ad97421fb1fb 473 /** \brief STR Exclusive (16 bit)
antbig 0:ad97421fb1fb 474
antbig 0:ad97421fb1fb 475 This function performs a exclusive STR command for 16 bit values.
antbig 0:ad97421fb1fb 476
antbig 0:ad97421fb1fb 477 \param [in] value Value to store
antbig 0:ad97421fb1fb 478 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 479 \return 0 Function succeeded
antbig 0:ad97421fb1fb 480 \return 1 Function failed
antbig 0:ad97421fb1fb 481 */
antbig 0:ad97421fb1fb 482 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
antbig 0:ad97421fb1fb 483 {
antbig 0:ad97421fb1fb 484 uint32_t result;
antbig 0:ad97421fb1fb 485
antbig 0:ad97421fb1fb 486 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
antbig 0:ad97421fb1fb 487 return(result);
antbig 0:ad97421fb1fb 488 }
antbig 0:ad97421fb1fb 489
antbig 0:ad97421fb1fb 490
antbig 0:ad97421fb1fb 491 /** \brief STR Exclusive (32 bit)
antbig 0:ad97421fb1fb 492
antbig 0:ad97421fb1fb 493 This function performs a exclusive STR command for 32 bit values.
antbig 0:ad97421fb1fb 494
antbig 0:ad97421fb1fb 495 \param [in] value Value to store
antbig 0:ad97421fb1fb 496 \param [in] ptr Pointer to location
antbig 0:ad97421fb1fb 497 \return 0 Function succeeded
antbig 0:ad97421fb1fb 498 \return 1 Function failed
antbig 0:ad97421fb1fb 499 */
antbig 0:ad97421fb1fb 500 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
antbig 0:ad97421fb1fb 501 {
antbig 0:ad97421fb1fb 502 uint32_t result;
antbig 0:ad97421fb1fb 503
antbig 0:ad97421fb1fb 504 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
antbig 0:ad97421fb1fb 505 return(result);
antbig 0:ad97421fb1fb 506 }
antbig 0:ad97421fb1fb 507
antbig 0:ad97421fb1fb 508
antbig 0:ad97421fb1fb 509 /** \brief Remove the exclusive lock
antbig 0:ad97421fb1fb 510
antbig 0:ad97421fb1fb 511 This function removes the exclusive lock which is created by LDREX.
antbig 0:ad97421fb1fb 512
antbig 0:ad97421fb1fb 513 */
antbig 0:ad97421fb1fb 514 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
antbig 0:ad97421fb1fb 515 {
antbig 0:ad97421fb1fb 516 __ASM volatile ("clrex");
antbig 0:ad97421fb1fb 517 }
antbig 0:ad97421fb1fb 518
antbig 0:ad97421fb1fb 519
antbig 0:ad97421fb1fb 520 /** \brief Signed Saturate
antbig 0:ad97421fb1fb 521
antbig 0:ad97421fb1fb 522 This function saturates a signed value.
antbig 0:ad97421fb1fb 523
antbig 0:ad97421fb1fb 524 \param [in] value Value to be saturated
antbig 0:ad97421fb1fb 525 \param [in] sat Bit position to saturate to (1..32)
antbig 0:ad97421fb1fb 526 \return Saturated value
antbig 0:ad97421fb1fb 527 */
antbig 0:ad97421fb1fb 528 #define __SSAT(ARG1,ARG2) \
antbig 0:ad97421fb1fb 529 ({ \
antbig 0:ad97421fb1fb 530 uint32_t __RES, __ARG1 = (ARG1); \
antbig 0:ad97421fb1fb 531 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
antbig 0:ad97421fb1fb 532 __RES; \
antbig 0:ad97421fb1fb 533 })
antbig 0:ad97421fb1fb 534
antbig 0:ad97421fb1fb 535
antbig 0:ad97421fb1fb 536 /** \brief Unsigned Saturate
antbig 0:ad97421fb1fb 537
antbig 0:ad97421fb1fb 538 This function saturates an unsigned value.
antbig 0:ad97421fb1fb 539
antbig 0:ad97421fb1fb 540 \param [in] value Value to be saturated
antbig 0:ad97421fb1fb 541 \param [in] sat Bit position to saturate to (0..31)
antbig 0:ad97421fb1fb 542 \return Saturated value
antbig 0:ad97421fb1fb 543 */
antbig 0:ad97421fb1fb 544 #define __USAT(ARG1,ARG2) \
antbig 0:ad97421fb1fb 545 ({ \
antbig 0:ad97421fb1fb 546 uint32_t __RES, __ARG1 = (ARG1); \
antbig 0:ad97421fb1fb 547 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
antbig 0:ad97421fb1fb 548 __RES; \
antbig 0:ad97421fb1fb 549 })
antbig 0:ad97421fb1fb 550
antbig 0:ad97421fb1fb 551
antbig 0:ad97421fb1fb 552 /** \brief Count leading zeros
antbig 0:ad97421fb1fb 553
antbig 0:ad97421fb1fb 554 This function counts the number of leading zeros of a data value.
antbig 0:ad97421fb1fb 555
antbig 0:ad97421fb1fb 556 \param [in] value Value to count the leading zeros
antbig 0:ad97421fb1fb 557 \return number of leading zeros in value
antbig 0:ad97421fb1fb 558 */
antbig 0:ad97421fb1fb 559 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
antbig 0:ad97421fb1fb 560 {
antbig 0:ad97421fb1fb 561 uint8_t result;
antbig 0:ad97421fb1fb 562
antbig 0:ad97421fb1fb 563 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
antbig 0:ad97421fb1fb 564 return(result);
antbig 0:ad97421fb1fb 565 }
antbig 0:ad97421fb1fb 566
antbig 0:ad97421fb1fb 567 #endif /* (__CORTEX_M >= 0x03) */
antbig 0:ad97421fb1fb 568
antbig 0:ad97421fb1fb 569
antbig 0:ad97421fb1fb 570
antbig 0:ad97421fb1fb 571
antbig 0:ad97421fb1fb 572 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
antbig 0:ad97421fb1fb 573 /* TASKING carm specific functions */
antbig 0:ad97421fb1fb 574
antbig 0:ad97421fb1fb 575 /*
antbig 0:ad97421fb1fb 576 * The CMSIS functions have been implemented as intrinsics in the compiler.
antbig 0:ad97421fb1fb 577 * Please use "carm -?i" to get an up to date list of all intrinsics,
antbig 0:ad97421fb1fb 578 * Including the CMSIS ones.
antbig 0:ad97421fb1fb 579 */
antbig 0:ad97421fb1fb 580
antbig 0:ad97421fb1fb 581 #endif
antbig 0:ad97421fb1fb 582
antbig 0:ad97421fb1fb 583 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
antbig 0:ad97421fb1fb 584
antbig 0:ad97421fb1fb 585 #endif /* __CORE_CMINSTR_H */