code de start qui marche a la fin du premier match, base pour la suite
Fork of CRAC-Strat_2017_homologation_petit_rob by
mbed/LPC1768/core_cm3.h@22:a466d08ac42b, 2017-05-25 (annotated)
- Committer:
- clementlignie
- Date:
- Thu May 25 14:40:49 2017 +0000
- Revision:
- 22:a466d08ac42b
- Parent:
- 0:ad97421fb1fb
code de strart qui marche, le 25-05, a 16h40, apres le premier match
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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antbig | 0:ad97421fb1fb | 1 | /**************************************************************************//** |
antbig | 0:ad97421fb1fb | 2 | * @file core_cm3.h |
antbig | 0:ad97421fb1fb | 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
antbig | 0:ad97421fb1fb | 4 | * @version V3.01 |
antbig | 0:ad97421fb1fb | 5 | * @date 06. March 2012 |
antbig | 0:ad97421fb1fb | 6 | * |
antbig | 0:ad97421fb1fb | 7 | * @note |
antbig | 0:ad97421fb1fb | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
antbig | 0:ad97421fb1fb | 9 | * |
antbig | 0:ad97421fb1fb | 10 | * @par |
antbig | 0:ad97421fb1fb | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
antbig | 0:ad97421fb1fb | 12 | * processor based microcontrollers. This file can be freely distributed |
antbig | 0:ad97421fb1fb | 13 | * within development tools that are supporting such ARM based processors. |
antbig | 0:ad97421fb1fb | 14 | * |
antbig | 0:ad97421fb1fb | 15 | * @par |
antbig | 0:ad97421fb1fb | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
antbig | 0:ad97421fb1fb | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
antbig | 0:ad97421fb1fb | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
antbig | 0:ad97421fb1fb | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
antbig | 0:ad97421fb1fb | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
antbig | 0:ad97421fb1fb | 21 | * |
antbig | 0:ad97421fb1fb | 22 | ******************************************************************************/ |
antbig | 0:ad97421fb1fb | 23 | #if defined ( __ICCARM__ ) |
antbig | 0:ad97421fb1fb | 24 | #pragma system_include /* treat file as system include file for MISRA check */ |
antbig | 0:ad97421fb1fb | 25 | #endif |
antbig | 0:ad97421fb1fb | 26 | |
antbig | 0:ad97421fb1fb | 27 | #ifdef __cplusplus |
antbig | 0:ad97421fb1fb | 28 | extern "C" { |
antbig | 0:ad97421fb1fb | 29 | #endif |
antbig | 0:ad97421fb1fb | 30 | |
antbig | 0:ad97421fb1fb | 31 | #ifndef __CORE_CM3_H_GENERIC |
antbig | 0:ad97421fb1fb | 32 | #define __CORE_CM3_H_GENERIC |
antbig | 0:ad97421fb1fb | 33 | |
antbig | 0:ad97421fb1fb | 34 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
antbig | 0:ad97421fb1fb | 35 | CMSIS violates the following MISRA-C:2004 rules: |
antbig | 0:ad97421fb1fb | 36 | |
antbig | 0:ad97421fb1fb | 37 | \li Required Rule 8.5, object/function definition in header file.<br> |
antbig | 0:ad97421fb1fb | 38 | Function definitions in header files are used to allow 'inlining'. |
antbig | 0:ad97421fb1fb | 39 | |
antbig | 0:ad97421fb1fb | 40 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
antbig | 0:ad97421fb1fb | 41 | Unions are used for effective representation of core registers. |
antbig | 0:ad97421fb1fb | 42 | |
antbig | 0:ad97421fb1fb | 43 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
antbig | 0:ad97421fb1fb | 44 | Function-like macros are used to allow more efficient code. |
antbig | 0:ad97421fb1fb | 45 | */ |
antbig | 0:ad97421fb1fb | 46 | |
antbig | 0:ad97421fb1fb | 47 | |
antbig | 0:ad97421fb1fb | 48 | /******************************************************************************* |
antbig | 0:ad97421fb1fb | 49 | * CMSIS definitions |
antbig | 0:ad97421fb1fb | 50 | ******************************************************************************/ |
antbig | 0:ad97421fb1fb | 51 | /** \ingroup Cortex_M3 |
antbig | 0:ad97421fb1fb | 52 | @{ |
antbig | 0:ad97421fb1fb | 53 | */ |
antbig | 0:ad97421fb1fb | 54 | |
antbig | 0:ad97421fb1fb | 55 | /* CMSIS CM3 definitions */ |
antbig | 0:ad97421fb1fb | 56 | #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
antbig | 0:ad97421fb1fb | 57 | #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ |
antbig | 0:ad97421fb1fb | 58 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ |
antbig | 0:ad97421fb1fb | 59 | __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
antbig | 0:ad97421fb1fb | 60 | |
antbig | 0:ad97421fb1fb | 61 | #define __CORTEX_M (0x03) /*!< Cortex-M Core */ |
antbig | 0:ad97421fb1fb | 62 | |
antbig | 0:ad97421fb1fb | 63 | |
antbig | 0:ad97421fb1fb | 64 | #if defined ( __CC_ARM ) |
antbig | 0:ad97421fb1fb | 65 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
antbig | 0:ad97421fb1fb | 66 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
antbig | 0:ad97421fb1fb | 67 | #define __STATIC_INLINE static __inline |
antbig | 0:ad97421fb1fb | 68 | |
antbig | 0:ad97421fb1fb | 69 | #elif defined ( __ICCARM__ ) |
antbig | 0:ad97421fb1fb | 70 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
antbig | 0:ad97421fb1fb | 71 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
antbig | 0:ad97421fb1fb | 72 | #define __STATIC_INLINE static inline |
antbig | 0:ad97421fb1fb | 73 | |
antbig | 0:ad97421fb1fb | 74 | #elif defined ( __TMS470__ ) |
antbig | 0:ad97421fb1fb | 75 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
antbig | 0:ad97421fb1fb | 76 | #define __STATIC_INLINE static inline |
antbig | 0:ad97421fb1fb | 77 | |
antbig | 0:ad97421fb1fb | 78 | #elif defined ( __GNUC__ ) |
antbig | 0:ad97421fb1fb | 79 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
antbig | 0:ad97421fb1fb | 80 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
antbig | 0:ad97421fb1fb | 81 | #define __STATIC_INLINE static inline |
antbig | 0:ad97421fb1fb | 82 | |
antbig | 0:ad97421fb1fb | 83 | #elif defined ( __TASKING__ ) |
antbig | 0:ad97421fb1fb | 84 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
antbig | 0:ad97421fb1fb | 85 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
antbig | 0:ad97421fb1fb | 86 | #define __STATIC_INLINE static inline |
antbig | 0:ad97421fb1fb | 87 | |
antbig | 0:ad97421fb1fb | 88 | #endif |
antbig | 0:ad97421fb1fb | 89 | |
antbig | 0:ad97421fb1fb | 90 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
antbig | 0:ad97421fb1fb | 91 | */ |
antbig | 0:ad97421fb1fb | 92 | #define __FPU_USED 0 |
antbig | 0:ad97421fb1fb | 93 | |
antbig | 0:ad97421fb1fb | 94 | #if defined ( __CC_ARM ) |
antbig | 0:ad97421fb1fb | 95 | #if defined __TARGET_FPU_VFP |
antbig | 0:ad97421fb1fb | 96 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
antbig | 0:ad97421fb1fb | 97 | #endif |
antbig | 0:ad97421fb1fb | 98 | |
antbig | 0:ad97421fb1fb | 99 | #elif defined ( __ICCARM__ ) |
antbig | 0:ad97421fb1fb | 100 | #if defined __ARMVFP__ |
antbig | 0:ad97421fb1fb | 101 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
antbig | 0:ad97421fb1fb | 102 | #endif |
antbig | 0:ad97421fb1fb | 103 | |
antbig | 0:ad97421fb1fb | 104 | #elif defined ( __TMS470__ ) |
antbig | 0:ad97421fb1fb | 105 | #if defined __TI__VFP_SUPPORT____ |
antbig | 0:ad97421fb1fb | 106 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
antbig | 0:ad97421fb1fb | 107 | #endif |
antbig | 0:ad97421fb1fb | 108 | |
antbig | 0:ad97421fb1fb | 109 | #elif defined ( __GNUC__ ) |
antbig | 0:ad97421fb1fb | 110 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
antbig | 0:ad97421fb1fb | 111 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
antbig | 0:ad97421fb1fb | 112 | #endif |
antbig | 0:ad97421fb1fb | 113 | |
antbig | 0:ad97421fb1fb | 114 | #elif defined ( __TASKING__ ) |
antbig | 0:ad97421fb1fb | 115 | /* add preprocessor checks */ |
antbig | 0:ad97421fb1fb | 116 | #endif |
antbig | 0:ad97421fb1fb | 117 | |
antbig | 0:ad97421fb1fb | 118 | #include <stdint.h> /* standard types definitions */ |
antbig | 0:ad97421fb1fb | 119 | #include <core_cmInstr.h> /* Core Instruction Access */ |
antbig | 0:ad97421fb1fb | 120 | #include <core_cmFunc.h> /* Core Function Access */ |
antbig | 0:ad97421fb1fb | 121 | |
antbig | 0:ad97421fb1fb | 122 | #endif /* __CORE_CM3_H_GENERIC */ |
antbig | 0:ad97421fb1fb | 123 | |
antbig | 0:ad97421fb1fb | 124 | #ifndef __CMSIS_GENERIC |
antbig | 0:ad97421fb1fb | 125 | |
antbig | 0:ad97421fb1fb | 126 | #ifndef __CORE_CM3_H_DEPENDANT |
antbig | 0:ad97421fb1fb | 127 | #define __CORE_CM3_H_DEPENDANT |
antbig | 0:ad97421fb1fb | 128 | |
antbig | 0:ad97421fb1fb | 129 | /* check device defines and use defaults */ |
antbig | 0:ad97421fb1fb | 130 | #if defined __CHECK_DEVICE_DEFINES |
antbig | 0:ad97421fb1fb | 131 | #ifndef __CM3_REV |
antbig | 0:ad97421fb1fb | 132 | #define __CM3_REV 0x0200 |
antbig | 0:ad97421fb1fb | 133 | #warning "__CM3_REV not defined in device header file; using default!" |
antbig | 0:ad97421fb1fb | 134 | #endif |
antbig | 0:ad97421fb1fb | 135 | |
antbig | 0:ad97421fb1fb | 136 | #ifndef __MPU_PRESENT |
antbig | 0:ad97421fb1fb | 137 | #define __MPU_PRESENT 0 |
antbig | 0:ad97421fb1fb | 138 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
antbig | 0:ad97421fb1fb | 139 | #endif |
antbig | 0:ad97421fb1fb | 140 | |
antbig | 0:ad97421fb1fb | 141 | #ifndef __NVIC_PRIO_BITS |
antbig | 0:ad97421fb1fb | 142 | #define __NVIC_PRIO_BITS 4 |
antbig | 0:ad97421fb1fb | 143 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
antbig | 0:ad97421fb1fb | 144 | #endif |
antbig | 0:ad97421fb1fb | 145 | |
antbig | 0:ad97421fb1fb | 146 | #ifndef __Vendor_SysTickConfig |
antbig | 0:ad97421fb1fb | 147 | #define __Vendor_SysTickConfig 0 |
antbig | 0:ad97421fb1fb | 148 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
antbig | 0:ad97421fb1fb | 149 | #endif |
antbig | 0:ad97421fb1fb | 150 | #endif |
antbig | 0:ad97421fb1fb | 151 | |
antbig | 0:ad97421fb1fb | 152 | /* IO definitions (access restrictions to peripheral registers) */ |
antbig | 0:ad97421fb1fb | 153 | /** |
antbig | 0:ad97421fb1fb | 154 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
antbig | 0:ad97421fb1fb | 155 | |
antbig | 0:ad97421fb1fb | 156 | <strong>IO Type Qualifiers</strong> are used |
antbig | 0:ad97421fb1fb | 157 | \li to specify the access to peripheral variables. |
antbig | 0:ad97421fb1fb | 158 | \li for automatic generation of peripheral register debug information. |
antbig | 0:ad97421fb1fb | 159 | */ |
antbig | 0:ad97421fb1fb | 160 | #ifdef __cplusplus |
antbig | 0:ad97421fb1fb | 161 | #define __I volatile /*!< Defines 'read only' permissions */ |
antbig | 0:ad97421fb1fb | 162 | #else |
antbig | 0:ad97421fb1fb | 163 | #define __I volatile const /*!< Defines 'read only' permissions */ |
antbig | 0:ad97421fb1fb | 164 | #endif |
antbig | 0:ad97421fb1fb | 165 | #define __O volatile /*!< Defines 'write only' permissions */ |
antbig | 0:ad97421fb1fb | 166 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
antbig | 0:ad97421fb1fb | 167 | |
antbig | 0:ad97421fb1fb | 168 | /*@} end of group Cortex_M3 */ |
antbig | 0:ad97421fb1fb | 169 | |
antbig | 0:ad97421fb1fb | 170 | |
antbig | 0:ad97421fb1fb | 171 | |
antbig | 0:ad97421fb1fb | 172 | /******************************************************************************* |
antbig | 0:ad97421fb1fb | 173 | * Register Abstraction |
antbig | 0:ad97421fb1fb | 174 | Core Register contain: |
antbig | 0:ad97421fb1fb | 175 | - Core Register |
antbig | 0:ad97421fb1fb | 176 | - Core NVIC Register |
antbig | 0:ad97421fb1fb | 177 | - Core SCB Register |
antbig | 0:ad97421fb1fb | 178 | - Core SysTick Register |
antbig | 0:ad97421fb1fb | 179 | - Core Debug Register |
antbig | 0:ad97421fb1fb | 180 | - Core MPU Register |
antbig | 0:ad97421fb1fb | 181 | ******************************************************************************/ |
antbig | 0:ad97421fb1fb | 182 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
antbig | 0:ad97421fb1fb | 183 | \brief Type definitions and defines for Cortex-M processor based devices. |
antbig | 0:ad97421fb1fb | 184 | */ |
antbig | 0:ad97421fb1fb | 185 | |
antbig | 0:ad97421fb1fb | 186 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 187 | \defgroup CMSIS_CORE Status and Control Registers |
antbig | 0:ad97421fb1fb | 188 | \brief Core Register type definitions. |
antbig | 0:ad97421fb1fb | 189 | @{ |
antbig | 0:ad97421fb1fb | 190 | */ |
antbig | 0:ad97421fb1fb | 191 | |
antbig | 0:ad97421fb1fb | 192 | /** \brief Union type to access the Application Program Status Register (APSR). |
antbig | 0:ad97421fb1fb | 193 | */ |
antbig | 0:ad97421fb1fb | 194 | typedef union |
antbig | 0:ad97421fb1fb | 195 | { |
antbig | 0:ad97421fb1fb | 196 | struct |
antbig | 0:ad97421fb1fb | 197 | { |
antbig | 0:ad97421fb1fb | 198 | #if (__CORTEX_M != 0x04) |
antbig | 0:ad97421fb1fb | 199 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
antbig | 0:ad97421fb1fb | 200 | #else |
antbig | 0:ad97421fb1fb | 201 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
antbig | 0:ad97421fb1fb | 202 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
antbig | 0:ad97421fb1fb | 203 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
antbig | 0:ad97421fb1fb | 204 | #endif |
antbig | 0:ad97421fb1fb | 205 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
antbig | 0:ad97421fb1fb | 206 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
antbig | 0:ad97421fb1fb | 207 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
antbig | 0:ad97421fb1fb | 208 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
antbig | 0:ad97421fb1fb | 209 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
antbig | 0:ad97421fb1fb | 210 | } b; /*!< Structure used for bit access */ |
antbig | 0:ad97421fb1fb | 211 | uint32_t w; /*!< Type used for word access */ |
antbig | 0:ad97421fb1fb | 212 | } APSR_Type; |
antbig | 0:ad97421fb1fb | 213 | |
antbig | 0:ad97421fb1fb | 214 | |
antbig | 0:ad97421fb1fb | 215 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
antbig | 0:ad97421fb1fb | 216 | */ |
antbig | 0:ad97421fb1fb | 217 | typedef union |
antbig | 0:ad97421fb1fb | 218 | { |
antbig | 0:ad97421fb1fb | 219 | struct |
antbig | 0:ad97421fb1fb | 220 | { |
antbig | 0:ad97421fb1fb | 221 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
antbig | 0:ad97421fb1fb | 222 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
antbig | 0:ad97421fb1fb | 223 | } b; /*!< Structure used for bit access */ |
antbig | 0:ad97421fb1fb | 224 | uint32_t w; /*!< Type used for word access */ |
antbig | 0:ad97421fb1fb | 225 | } IPSR_Type; |
antbig | 0:ad97421fb1fb | 226 | |
antbig | 0:ad97421fb1fb | 227 | |
antbig | 0:ad97421fb1fb | 228 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
antbig | 0:ad97421fb1fb | 229 | */ |
antbig | 0:ad97421fb1fb | 230 | typedef union |
antbig | 0:ad97421fb1fb | 231 | { |
antbig | 0:ad97421fb1fb | 232 | struct |
antbig | 0:ad97421fb1fb | 233 | { |
antbig | 0:ad97421fb1fb | 234 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
antbig | 0:ad97421fb1fb | 235 | #if (__CORTEX_M != 0x04) |
antbig | 0:ad97421fb1fb | 236 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
antbig | 0:ad97421fb1fb | 237 | #else |
antbig | 0:ad97421fb1fb | 238 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
antbig | 0:ad97421fb1fb | 239 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
antbig | 0:ad97421fb1fb | 240 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
antbig | 0:ad97421fb1fb | 241 | #endif |
antbig | 0:ad97421fb1fb | 242 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
antbig | 0:ad97421fb1fb | 243 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
antbig | 0:ad97421fb1fb | 244 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
antbig | 0:ad97421fb1fb | 245 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
antbig | 0:ad97421fb1fb | 246 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
antbig | 0:ad97421fb1fb | 247 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
antbig | 0:ad97421fb1fb | 248 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
antbig | 0:ad97421fb1fb | 249 | } b; /*!< Structure used for bit access */ |
antbig | 0:ad97421fb1fb | 250 | uint32_t w; /*!< Type used for word access */ |
antbig | 0:ad97421fb1fb | 251 | } xPSR_Type; |
antbig | 0:ad97421fb1fb | 252 | |
antbig | 0:ad97421fb1fb | 253 | |
antbig | 0:ad97421fb1fb | 254 | /** \brief Union type to access the Control Registers (CONTROL). |
antbig | 0:ad97421fb1fb | 255 | */ |
antbig | 0:ad97421fb1fb | 256 | typedef union |
antbig | 0:ad97421fb1fb | 257 | { |
antbig | 0:ad97421fb1fb | 258 | struct |
antbig | 0:ad97421fb1fb | 259 | { |
antbig | 0:ad97421fb1fb | 260 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
antbig | 0:ad97421fb1fb | 261 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
antbig | 0:ad97421fb1fb | 262 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
antbig | 0:ad97421fb1fb | 263 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
antbig | 0:ad97421fb1fb | 264 | } b; /*!< Structure used for bit access */ |
antbig | 0:ad97421fb1fb | 265 | uint32_t w; /*!< Type used for word access */ |
antbig | 0:ad97421fb1fb | 266 | } CONTROL_Type; |
antbig | 0:ad97421fb1fb | 267 | |
antbig | 0:ad97421fb1fb | 268 | /*@} end of group CMSIS_CORE */ |
antbig | 0:ad97421fb1fb | 269 | |
antbig | 0:ad97421fb1fb | 270 | |
antbig | 0:ad97421fb1fb | 271 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 272 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
antbig | 0:ad97421fb1fb | 273 | \brief Type definitions for the NVIC Registers |
antbig | 0:ad97421fb1fb | 274 | @{ |
antbig | 0:ad97421fb1fb | 275 | */ |
antbig | 0:ad97421fb1fb | 276 | |
antbig | 0:ad97421fb1fb | 277 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
antbig | 0:ad97421fb1fb | 278 | */ |
antbig | 0:ad97421fb1fb | 279 | typedef struct |
antbig | 0:ad97421fb1fb | 280 | { |
antbig | 0:ad97421fb1fb | 281 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
antbig | 0:ad97421fb1fb | 282 | uint32_t RESERVED0[24]; |
antbig | 0:ad97421fb1fb | 283 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
antbig | 0:ad97421fb1fb | 284 | uint32_t RSERVED1[24]; |
antbig | 0:ad97421fb1fb | 285 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
antbig | 0:ad97421fb1fb | 286 | uint32_t RESERVED2[24]; |
antbig | 0:ad97421fb1fb | 287 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
antbig | 0:ad97421fb1fb | 288 | uint32_t RESERVED3[24]; |
antbig | 0:ad97421fb1fb | 289 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
antbig | 0:ad97421fb1fb | 290 | uint32_t RESERVED4[56]; |
antbig | 0:ad97421fb1fb | 291 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
antbig | 0:ad97421fb1fb | 292 | uint32_t RESERVED5[644]; |
antbig | 0:ad97421fb1fb | 293 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
antbig | 0:ad97421fb1fb | 294 | } NVIC_Type; |
antbig | 0:ad97421fb1fb | 295 | |
antbig | 0:ad97421fb1fb | 296 | /* Software Triggered Interrupt Register Definitions */ |
antbig | 0:ad97421fb1fb | 297 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ |
antbig | 0:ad97421fb1fb | 298 | #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ |
antbig | 0:ad97421fb1fb | 299 | |
antbig | 0:ad97421fb1fb | 300 | /*@} end of group CMSIS_NVIC */ |
antbig | 0:ad97421fb1fb | 301 | |
antbig | 0:ad97421fb1fb | 302 | |
antbig | 0:ad97421fb1fb | 303 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 304 | \defgroup CMSIS_SCB System Control Block (SCB) |
antbig | 0:ad97421fb1fb | 305 | \brief Type definitions for the System Control Block Registers |
antbig | 0:ad97421fb1fb | 306 | @{ |
antbig | 0:ad97421fb1fb | 307 | */ |
antbig | 0:ad97421fb1fb | 308 | |
antbig | 0:ad97421fb1fb | 309 | /** \brief Structure type to access the System Control Block (SCB). |
antbig | 0:ad97421fb1fb | 310 | */ |
antbig | 0:ad97421fb1fb | 311 | typedef struct |
antbig | 0:ad97421fb1fb | 312 | { |
antbig | 0:ad97421fb1fb | 313 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
antbig | 0:ad97421fb1fb | 314 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
antbig | 0:ad97421fb1fb | 315 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
antbig | 0:ad97421fb1fb | 316 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
antbig | 0:ad97421fb1fb | 317 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
antbig | 0:ad97421fb1fb | 318 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
antbig | 0:ad97421fb1fb | 319 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
antbig | 0:ad97421fb1fb | 320 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
antbig | 0:ad97421fb1fb | 321 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
antbig | 0:ad97421fb1fb | 322 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
antbig | 0:ad97421fb1fb | 323 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
antbig | 0:ad97421fb1fb | 324 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
antbig | 0:ad97421fb1fb | 325 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
antbig | 0:ad97421fb1fb | 326 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
antbig | 0:ad97421fb1fb | 327 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
antbig | 0:ad97421fb1fb | 328 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
antbig | 0:ad97421fb1fb | 329 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
antbig | 0:ad97421fb1fb | 330 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
antbig | 0:ad97421fb1fb | 331 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
antbig | 0:ad97421fb1fb | 332 | uint32_t RESERVED0[5]; |
antbig | 0:ad97421fb1fb | 333 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
antbig | 0:ad97421fb1fb | 334 | } SCB_Type; |
antbig | 0:ad97421fb1fb | 335 | |
antbig | 0:ad97421fb1fb | 336 | /* SCB CPUID Register Definitions */ |
antbig | 0:ad97421fb1fb | 337 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
antbig | 0:ad97421fb1fb | 338 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
antbig | 0:ad97421fb1fb | 339 | |
antbig | 0:ad97421fb1fb | 340 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
antbig | 0:ad97421fb1fb | 341 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
antbig | 0:ad97421fb1fb | 342 | |
antbig | 0:ad97421fb1fb | 343 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
antbig | 0:ad97421fb1fb | 344 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
antbig | 0:ad97421fb1fb | 345 | |
antbig | 0:ad97421fb1fb | 346 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
antbig | 0:ad97421fb1fb | 347 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
antbig | 0:ad97421fb1fb | 348 | |
antbig | 0:ad97421fb1fb | 349 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
antbig | 0:ad97421fb1fb | 350 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
antbig | 0:ad97421fb1fb | 351 | |
antbig | 0:ad97421fb1fb | 352 | /* SCB Interrupt Control State Register Definitions */ |
antbig | 0:ad97421fb1fb | 353 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
antbig | 0:ad97421fb1fb | 354 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
antbig | 0:ad97421fb1fb | 355 | |
antbig | 0:ad97421fb1fb | 356 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
antbig | 0:ad97421fb1fb | 357 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
antbig | 0:ad97421fb1fb | 358 | |
antbig | 0:ad97421fb1fb | 359 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
antbig | 0:ad97421fb1fb | 360 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
antbig | 0:ad97421fb1fb | 361 | |
antbig | 0:ad97421fb1fb | 362 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
antbig | 0:ad97421fb1fb | 363 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
antbig | 0:ad97421fb1fb | 364 | |
antbig | 0:ad97421fb1fb | 365 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
antbig | 0:ad97421fb1fb | 366 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
antbig | 0:ad97421fb1fb | 367 | |
antbig | 0:ad97421fb1fb | 368 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
antbig | 0:ad97421fb1fb | 369 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
antbig | 0:ad97421fb1fb | 370 | |
antbig | 0:ad97421fb1fb | 371 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
antbig | 0:ad97421fb1fb | 372 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
antbig | 0:ad97421fb1fb | 373 | |
antbig | 0:ad97421fb1fb | 374 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
antbig | 0:ad97421fb1fb | 375 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
antbig | 0:ad97421fb1fb | 376 | |
antbig | 0:ad97421fb1fb | 377 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
antbig | 0:ad97421fb1fb | 378 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
antbig | 0:ad97421fb1fb | 379 | |
antbig | 0:ad97421fb1fb | 380 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
antbig | 0:ad97421fb1fb | 381 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
antbig | 0:ad97421fb1fb | 382 | |
antbig | 0:ad97421fb1fb | 383 | /* SCB Vector Table Offset Register Definitions */ |
antbig | 0:ad97421fb1fb | 384 | #if (__CM3_REV < 0x0201) /* core r2p1 */ |
antbig | 0:ad97421fb1fb | 385 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
antbig | 0:ad97421fb1fb | 386 | #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
antbig | 0:ad97421fb1fb | 387 | |
antbig | 0:ad97421fb1fb | 388 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
antbig | 0:ad97421fb1fb | 389 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
antbig | 0:ad97421fb1fb | 390 | #else |
antbig | 0:ad97421fb1fb | 391 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
antbig | 0:ad97421fb1fb | 392 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
antbig | 0:ad97421fb1fb | 393 | #endif |
antbig | 0:ad97421fb1fb | 394 | |
antbig | 0:ad97421fb1fb | 395 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 396 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
antbig | 0:ad97421fb1fb | 397 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
antbig | 0:ad97421fb1fb | 398 | |
antbig | 0:ad97421fb1fb | 399 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
antbig | 0:ad97421fb1fb | 400 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
antbig | 0:ad97421fb1fb | 401 | |
antbig | 0:ad97421fb1fb | 402 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
antbig | 0:ad97421fb1fb | 403 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
antbig | 0:ad97421fb1fb | 404 | |
antbig | 0:ad97421fb1fb | 405 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
antbig | 0:ad97421fb1fb | 406 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
antbig | 0:ad97421fb1fb | 407 | |
antbig | 0:ad97421fb1fb | 408 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
antbig | 0:ad97421fb1fb | 409 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
antbig | 0:ad97421fb1fb | 410 | |
antbig | 0:ad97421fb1fb | 411 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
antbig | 0:ad97421fb1fb | 412 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
antbig | 0:ad97421fb1fb | 413 | |
antbig | 0:ad97421fb1fb | 414 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
antbig | 0:ad97421fb1fb | 415 | #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
antbig | 0:ad97421fb1fb | 416 | |
antbig | 0:ad97421fb1fb | 417 | /* SCB System Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 418 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
antbig | 0:ad97421fb1fb | 419 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
antbig | 0:ad97421fb1fb | 420 | |
antbig | 0:ad97421fb1fb | 421 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
antbig | 0:ad97421fb1fb | 422 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
antbig | 0:ad97421fb1fb | 423 | |
antbig | 0:ad97421fb1fb | 424 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
antbig | 0:ad97421fb1fb | 425 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
antbig | 0:ad97421fb1fb | 426 | |
antbig | 0:ad97421fb1fb | 427 | /* SCB Configuration Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 428 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
antbig | 0:ad97421fb1fb | 429 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
antbig | 0:ad97421fb1fb | 430 | |
antbig | 0:ad97421fb1fb | 431 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
antbig | 0:ad97421fb1fb | 432 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
antbig | 0:ad97421fb1fb | 433 | |
antbig | 0:ad97421fb1fb | 434 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
antbig | 0:ad97421fb1fb | 435 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
antbig | 0:ad97421fb1fb | 436 | |
antbig | 0:ad97421fb1fb | 437 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
antbig | 0:ad97421fb1fb | 438 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
antbig | 0:ad97421fb1fb | 439 | |
antbig | 0:ad97421fb1fb | 440 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
antbig | 0:ad97421fb1fb | 441 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
antbig | 0:ad97421fb1fb | 442 | |
antbig | 0:ad97421fb1fb | 443 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
antbig | 0:ad97421fb1fb | 444 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
antbig | 0:ad97421fb1fb | 445 | |
antbig | 0:ad97421fb1fb | 446 | /* SCB System Handler Control and State Register Definitions */ |
antbig | 0:ad97421fb1fb | 447 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
antbig | 0:ad97421fb1fb | 448 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
antbig | 0:ad97421fb1fb | 449 | |
antbig | 0:ad97421fb1fb | 450 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
antbig | 0:ad97421fb1fb | 451 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
antbig | 0:ad97421fb1fb | 452 | |
antbig | 0:ad97421fb1fb | 453 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
antbig | 0:ad97421fb1fb | 454 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
antbig | 0:ad97421fb1fb | 455 | |
antbig | 0:ad97421fb1fb | 456 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
antbig | 0:ad97421fb1fb | 457 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
antbig | 0:ad97421fb1fb | 458 | |
antbig | 0:ad97421fb1fb | 459 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
antbig | 0:ad97421fb1fb | 460 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
antbig | 0:ad97421fb1fb | 461 | |
antbig | 0:ad97421fb1fb | 462 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
antbig | 0:ad97421fb1fb | 463 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
antbig | 0:ad97421fb1fb | 464 | |
antbig | 0:ad97421fb1fb | 465 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
antbig | 0:ad97421fb1fb | 466 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
antbig | 0:ad97421fb1fb | 467 | |
antbig | 0:ad97421fb1fb | 468 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
antbig | 0:ad97421fb1fb | 469 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
antbig | 0:ad97421fb1fb | 470 | |
antbig | 0:ad97421fb1fb | 471 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
antbig | 0:ad97421fb1fb | 472 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
antbig | 0:ad97421fb1fb | 473 | |
antbig | 0:ad97421fb1fb | 474 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
antbig | 0:ad97421fb1fb | 475 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
antbig | 0:ad97421fb1fb | 476 | |
antbig | 0:ad97421fb1fb | 477 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
antbig | 0:ad97421fb1fb | 478 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
antbig | 0:ad97421fb1fb | 479 | |
antbig | 0:ad97421fb1fb | 480 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
antbig | 0:ad97421fb1fb | 481 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
antbig | 0:ad97421fb1fb | 482 | |
antbig | 0:ad97421fb1fb | 483 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
antbig | 0:ad97421fb1fb | 484 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
antbig | 0:ad97421fb1fb | 485 | |
antbig | 0:ad97421fb1fb | 486 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
antbig | 0:ad97421fb1fb | 487 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
antbig | 0:ad97421fb1fb | 488 | |
antbig | 0:ad97421fb1fb | 489 | /* SCB Configurable Fault Status Registers Definitions */ |
antbig | 0:ad97421fb1fb | 490 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
antbig | 0:ad97421fb1fb | 491 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
antbig | 0:ad97421fb1fb | 492 | |
antbig | 0:ad97421fb1fb | 493 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
antbig | 0:ad97421fb1fb | 494 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
antbig | 0:ad97421fb1fb | 495 | |
antbig | 0:ad97421fb1fb | 496 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
antbig | 0:ad97421fb1fb | 497 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
antbig | 0:ad97421fb1fb | 498 | |
antbig | 0:ad97421fb1fb | 499 | /* SCB Hard Fault Status Registers Definitions */ |
antbig | 0:ad97421fb1fb | 500 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
antbig | 0:ad97421fb1fb | 501 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
antbig | 0:ad97421fb1fb | 502 | |
antbig | 0:ad97421fb1fb | 503 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
antbig | 0:ad97421fb1fb | 504 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
antbig | 0:ad97421fb1fb | 505 | |
antbig | 0:ad97421fb1fb | 506 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
antbig | 0:ad97421fb1fb | 507 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
antbig | 0:ad97421fb1fb | 508 | |
antbig | 0:ad97421fb1fb | 509 | /* SCB Debug Fault Status Register Definitions */ |
antbig | 0:ad97421fb1fb | 510 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
antbig | 0:ad97421fb1fb | 511 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
antbig | 0:ad97421fb1fb | 512 | |
antbig | 0:ad97421fb1fb | 513 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
antbig | 0:ad97421fb1fb | 514 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
antbig | 0:ad97421fb1fb | 515 | |
antbig | 0:ad97421fb1fb | 516 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
antbig | 0:ad97421fb1fb | 517 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
antbig | 0:ad97421fb1fb | 518 | |
antbig | 0:ad97421fb1fb | 519 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
antbig | 0:ad97421fb1fb | 520 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
antbig | 0:ad97421fb1fb | 521 | |
antbig | 0:ad97421fb1fb | 522 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
antbig | 0:ad97421fb1fb | 523 | #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
antbig | 0:ad97421fb1fb | 524 | |
antbig | 0:ad97421fb1fb | 525 | /*@} end of group CMSIS_SCB */ |
antbig | 0:ad97421fb1fb | 526 | |
antbig | 0:ad97421fb1fb | 527 | |
antbig | 0:ad97421fb1fb | 528 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 529 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
antbig | 0:ad97421fb1fb | 530 | \brief Type definitions for the System Control and ID Register not in the SCB |
antbig | 0:ad97421fb1fb | 531 | @{ |
antbig | 0:ad97421fb1fb | 532 | */ |
antbig | 0:ad97421fb1fb | 533 | |
antbig | 0:ad97421fb1fb | 534 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
antbig | 0:ad97421fb1fb | 535 | */ |
antbig | 0:ad97421fb1fb | 536 | typedef struct |
antbig | 0:ad97421fb1fb | 537 | { |
antbig | 0:ad97421fb1fb | 538 | uint32_t RESERVED0[1]; |
antbig | 0:ad97421fb1fb | 539 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
antbig | 0:ad97421fb1fb | 540 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
antbig | 0:ad97421fb1fb | 541 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
antbig | 0:ad97421fb1fb | 542 | #else |
antbig | 0:ad97421fb1fb | 543 | uint32_t RESERVED1[1]; |
antbig | 0:ad97421fb1fb | 544 | #endif |
antbig | 0:ad97421fb1fb | 545 | } SCnSCB_Type; |
antbig | 0:ad97421fb1fb | 546 | |
antbig | 0:ad97421fb1fb | 547 | /* Interrupt Controller Type Register Definitions */ |
antbig | 0:ad97421fb1fb | 548 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ |
antbig | 0:ad97421fb1fb | 549 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ |
antbig | 0:ad97421fb1fb | 550 | |
antbig | 0:ad97421fb1fb | 551 | /* Auxiliary Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 552 | |
antbig | 0:ad97421fb1fb | 553 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ |
antbig | 0:ad97421fb1fb | 554 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
antbig | 0:ad97421fb1fb | 555 | |
antbig | 0:ad97421fb1fb | 556 | #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ |
antbig | 0:ad97421fb1fb | 557 | #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ |
antbig | 0:ad97421fb1fb | 558 | |
antbig | 0:ad97421fb1fb | 559 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
antbig | 0:ad97421fb1fb | 560 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ |
antbig | 0:ad97421fb1fb | 561 | |
antbig | 0:ad97421fb1fb | 562 | /*@} end of group CMSIS_SCnotSCB */ |
antbig | 0:ad97421fb1fb | 563 | |
antbig | 0:ad97421fb1fb | 564 | |
antbig | 0:ad97421fb1fb | 565 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 566 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
antbig | 0:ad97421fb1fb | 567 | \brief Type definitions for the System Timer Registers. |
antbig | 0:ad97421fb1fb | 568 | @{ |
antbig | 0:ad97421fb1fb | 569 | */ |
antbig | 0:ad97421fb1fb | 570 | |
antbig | 0:ad97421fb1fb | 571 | /** \brief Structure type to access the System Timer (SysTick). |
antbig | 0:ad97421fb1fb | 572 | */ |
antbig | 0:ad97421fb1fb | 573 | typedef struct |
antbig | 0:ad97421fb1fb | 574 | { |
antbig | 0:ad97421fb1fb | 575 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
antbig | 0:ad97421fb1fb | 576 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
antbig | 0:ad97421fb1fb | 577 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
antbig | 0:ad97421fb1fb | 578 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
antbig | 0:ad97421fb1fb | 579 | } SysTick_Type; |
antbig | 0:ad97421fb1fb | 580 | |
antbig | 0:ad97421fb1fb | 581 | /* SysTick Control / Status Register Definitions */ |
antbig | 0:ad97421fb1fb | 582 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
antbig | 0:ad97421fb1fb | 583 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
antbig | 0:ad97421fb1fb | 584 | |
antbig | 0:ad97421fb1fb | 585 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
antbig | 0:ad97421fb1fb | 586 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
antbig | 0:ad97421fb1fb | 587 | |
antbig | 0:ad97421fb1fb | 588 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
antbig | 0:ad97421fb1fb | 589 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
antbig | 0:ad97421fb1fb | 590 | |
antbig | 0:ad97421fb1fb | 591 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
antbig | 0:ad97421fb1fb | 592 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
antbig | 0:ad97421fb1fb | 593 | |
antbig | 0:ad97421fb1fb | 594 | /* SysTick Reload Register Definitions */ |
antbig | 0:ad97421fb1fb | 595 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
antbig | 0:ad97421fb1fb | 596 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
antbig | 0:ad97421fb1fb | 597 | |
antbig | 0:ad97421fb1fb | 598 | /* SysTick Current Register Definitions */ |
antbig | 0:ad97421fb1fb | 599 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
antbig | 0:ad97421fb1fb | 600 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
antbig | 0:ad97421fb1fb | 601 | |
antbig | 0:ad97421fb1fb | 602 | /* SysTick Calibration Register Definitions */ |
antbig | 0:ad97421fb1fb | 603 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
antbig | 0:ad97421fb1fb | 604 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
antbig | 0:ad97421fb1fb | 605 | |
antbig | 0:ad97421fb1fb | 606 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
antbig | 0:ad97421fb1fb | 607 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
antbig | 0:ad97421fb1fb | 608 | |
antbig | 0:ad97421fb1fb | 609 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
antbig | 0:ad97421fb1fb | 610 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
antbig | 0:ad97421fb1fb | 611 | |
antbig | 0:ad97421fb1fb | 612 | /*@} end of group CMSIS_SysTick */ |
antbig | 0:ad97421fb1fb | 613 | |
antbig | 0:ad97421fb1fb | 614 | |
antbig | 0:ad97421fb1fb | 615 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 616 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
antbig | 0:ad97421fb1fb | 617 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
antbig | 0:ad97421fb1fb | 618 | @{ |
antbig | 0:ad97421fb1fb | 619 | */ |
antbig | 0:ad97421fb1fb | 620 | |
antbig | 0:ad97421fb1fb | 621 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
antbig | 0:ad97421fb1fb | 622 | */ |
antbig | 0:ad97421fb1fb | 623 | typedef struct |
antbig | 0:ad97421fb1fb | 624 | { |
antbig | 0:ad97421fb1fb | 625 | __O union |
antbig | 0:ad97421fb1fb | 626 | { |
antbig | 0:ad97421fb1fb | 627 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
antbig | 0:ad97421fb1fb | 628 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
antbig | 0:ad97421fb1fb | 629 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
antbig | 0:ad97421fb1fb | 630 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
antbig | 0:ad97421fb1fb | 631 | uint32_t RESERVED0[864]; |
antbig | 0:ad97421fb1fb | 632 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
antbig | 0:ad97421fb1fb | 633 | uint32_t RESERVED1[15]; |
antbig | 0:ad97421fb1fb | 634 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
antbig | 0:ad97421fb1fb | 635 | uint32_t RESERVED2[15]; |
antbig | 0:ad97421fb1fb | 636 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
antbig | 0:ad97421fb1fb | 637 | } ITM_Type; |
antbig | 0:ad97421fb1fb | 638 | |
antbig | 0:ad97421fb1fb | 639 | /* ITM Trace Privilege Register Definitions */ |
antbig | 0:ad97421fb1fb | 640 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
antbig | 0:ad97421fb1fb | 641 | #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
antbig | 0:ad97421fb1fb | 642 | |
antbig | 0:ad97421fb1fb | 643 | /* ITM Trace Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 644 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
antbig | 0:ad97421fb1fb | 645 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
antbig | 0:ad97421fb1fb | 646 | |
antbig | 0:ad97421fb1fb | 647 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ |
antbig | 0:ad97421fb1fb | 648 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
antbig | 0:ad97421fb1fb | 649 | |
antbig | 0:ad97421fb1fb | 650 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ |
antbig | 0:ad97421fb1fb | 651 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
antbig | 0:ad97421fb1fb | 652 | |
antbig | 0:ad97421fb1fb | 653 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
antbig | 0:ad97421fb1fb | 654 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
antbig | 0:ad97421fb1fb | 655 | |
antbig | 0:ad97421fb1fb | 656 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
antbig | 0:ad97421fb1fb | 657 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
antbig | 0:ad97421fb1fb | 658 | |
antbig | 0:ad97421fb1fb | 659 | #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ |
antbig | 0:ad97421fb1fb | 660 | #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ |
antbig | 0:ad97421fb1fb | 661 | |
antbig | 0:ad97421fb1fb | 662 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
antbig | 0:ad97421fb1fb | 663 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
antbig | 0:ad97421fb1fb | 664 | |
antbig | 0:ad97421fb1fb | 665 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
antbig | 0:ad97421fb1fb | 666 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
antbig | 0:ad97421fb1fb | 667 | |
antbig | 0:ad97421fb1fb | 668 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
antbig | 0:ad97421fb1fb | 669 | #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
antbig | 0:ad97421fb1fb | 670 | |
antbig | 0:ad97421fb1fb | 671 | /*@}*/ /* end of group CMSIS_ITM */ |
antbig | 0:ad97421fb1fb | 672 | |
antbig | 0:ad97421fb1fb | 673 | |
antbig | 0:ad97421fb1fb | 674 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 675 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
antbig | 0:ad97421fb1fb | 676 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
antbig | 0:ad97421fb1fb | 677 | @{ |
antbig | 0:ad97421fb1fb | 678 | */ |
antbig | 0:ad97421fb1fb | 679 | |
antbig | 0:ad97421fb1fb | 680 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
antbig | 0:ad97421fb1fb | 681 | */ |
antbig | 0:ad97421fb1fb | 682 | typedef struct |
antbig | 0:ad97421fb1fb | 683 | { |
antbig | 0:ad97421fb1fb | 684 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
antbig | 0:ad97421fb1fb | 685 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
antbig | 0:ad97421fb1fb | 686 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
antbig | 0:ad97421fb1fb | 687 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
antbig | 0:ad97421fb1fb | 688 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
antbig | 0:ad97421fb1fb | 689 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
antbig | 0:ad97421fb1fb | 690 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
antbig | 0:ad97421fb1fb | 691 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
antbig | 0:ad97421fb1fb | 692 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
antbig | 0:ad97421fb1fb | 693 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
antbig | 0:ad97421fb1fb | 694 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
antbig | 0:ad97421fb1fb | 695 | uint32_t RESERVED0[1]; |
antbig | 0:ad97421fb1fb | 696 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
antbig | 0:ad97421fb1fb | 697 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
antbig | 0:ad97421fb1fb | 698 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
antbig | 0:ad97421fb1fb | 699 | uint32_t RESERVED1[1]; |
antbig | 0:ad97421fb1fb | 700 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
antbig | 0:ad97421fb1fb | 701 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
antbig | 0:ad97421fb1fb | 702 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
antbig | 0:ad97421fb1fb | 703 | uint32_t RESERVED2[1]; |
antbig | 0:ad97421fb1fb | 704 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
antbig | 0:ad97421fb1fb | 705 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
antbig | 0:ad97421fb1fb | 706 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
antbig | 0:ad97421fb1fb | 707 | } DWT_Type; |
antbig | 0:ad97421fb1fb | 708 | |
antbig | 0:ad97421fb1fb | 709 | /* DWT Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 710 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ |
antbig | 0:ad97421fb1fb | 711 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
antbig | 0:ad97421fb1fb | 712 | |
antbig | 0:ad97421fb1fb | 713 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ |
antbig | 0:ad97421fb1fb | 714 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
antbig | 0:ad97421fb1fb | 715 | |
antbig | 0:ad97421fb1fb | 716 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ |
antbig | 0:ad97421fb1fb | 717 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
antbig | 0:ad97421fb1fb | 718 | |
antbig | 0:ad97421fb1fb | 719 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ |
antbig | 0:ad97421fb1fb | 720 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
antbig | 0:ad97421fb1fb | 721 | |
antbig | 0:ad97421fb1fb | 722 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ |
antbig | 0:ad97421fb1fb | 723 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
antbig | 0:ad97421fb1fb | 724 | |
antbig | 0:ad97421fb1fb | 725 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ |
antbig | 0:ad97421fb1fb | 726 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 727 | |
antbig | 0:ad97421fb1fb | 728 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ |
antbig | 0:ad97421fb1fb | 729 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 730 | |
antbig | 0:ad97421fb1fb | 731 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ |
antbig | 0:ad97421fb1fb | 732 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 733 | |
antbig | 0:ad97421fb1fb | 734 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ |
antbig | 0:ad97421fb1fb | 735 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 736 | |
antbig | 0:ad97421fb1fb | 737 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ |
antbig | 0:ad97421fb1fb | 738 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 739 | |
antbig | 0:ad97421fb1fb | 740 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ |
antbig | 0:ad97421fb1fb | 741 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
antbig | 0:ad97421fb1fb | 742 | |
antbig | 0:ad97421fb1fb | 743 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ |
antbig | 0:ad97421fb1fb | 744 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
antbig | 0:ad97421fb1fb | 745 | |
antbig | 0:ad97421fb1fb | 746 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ |
antbig | 0:ad97421fb1fb | 747 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
antbig | 0:ad97421fb1fb | 748 | |
antbig | 0:ad97421fb1fb | 749 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ |
antbig | 0:ad97421fb1fb | 750 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
antbig | 0:ad97421fb1fb | 751 | |
antbig | 0:ad97421fb1fb | 752 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ |
antbig | 0:ad97421fb1fb | 753 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
antbig | 0:ad97421fb1fb | 754 | |
antbig | 0:ad97421fb1fb | 755 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ |
antbig | 0:ad97421fb1fb | 756 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
antbig | 0:ad97421fb1fb | 757 | |
antbig | 0:ad97421fb1fb | 758 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ |
antbig | 0:ad97421fb1fb | 759 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
antbig | 0:ad97421fb1fb | 760 | |
antbig | 0:ad97421fb1fb | 761 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ |
antbig | 0:ad97421fb1fb | 762 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ |
antbig | 0:ad97421fb1fb | 763 | |
antbig | 0:ad97421fb1fb | 764 | /* DWT CPI Count Register Definitions */ |
antbig | 0:ad97421fb1fb | 765 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ |
antbig | 0:ad97421fb1fb | 766 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ |
antbig | 0:ad97421fb1fb | 767 | |
antbig | 0:ad97421fb1fb | 768 | /* DWT Exception Overhead Count Register Definitions */ |
antbig | 0:ad97421fb1fb | 769 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ |
antbig | 0:ad97421fb1fb | 770 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ |
antbig | 0:ad97421fb1fb | 771 | |
antbig | 0:ad97421fb1fb | 772 | /* DWT Sleep Count Register Definitions */ |
antbig | 0:ad97421fb1fb | 773 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
antbig | 0:ad97421fb1fb | 774 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
antbig | 0:ad97421fb1fb | 775 | |
antbig | 0:ad97421fb1fb | 776 | /* DWT LSU Count Register Definitions */ |
antbig | 0:ad97421fb1fb | 777 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ |
antbig | 0:ad97421fb1fb | 778 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ |
antbig | 0:ad97421fb1fb | 779 | |
antbig | 0:ad97421fb1fb | 780 | /* DWT Folded-instruction Count Register Definitions */ |
antbig | 0:ad97421fb1fb | 781 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ |
antbig | 0:ad97421fb1fb | 782 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
antbig | 0:ad97421fb1fb | 783 | |
antbig | 0:ad97421fb1fb | 784 | /* DWT Comparator Mask Register Definitions */ |
antbig | 0:ad97421fb1fb | 785 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ |
antbig | 0:ad97421fb1fb | 786 | #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ |
antbig | 0:ad97421fb1fb | 787 | |
antbig | 0:ad97421fb1fb | 788 | /* DWT Comparator Function Register Definitions */ |
antbig | 0:ad97421fb1fb | 789 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ |
antbig | 0:ad97421fb1fb | 790 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
antbig | 0:ad97421fb1fb | 791 | |
antbig | 0:ad97421fb1fb | 792 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ |
antbig | 0:ad97421fb1fb | 793 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
antbig | 0:ad97421fb1fb | 794 | |
antbig | 0:ad97421fb1fb | 795 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ |
antbig | 0:ad97421fb1fb | 796 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
antbig | 0:ad97421fb1fb | 797 | |
antbig | 0:ad97421fb1fb | 798 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ |
antbig | 0:ad97421fb1fb | 799 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
antbig | 0:ad97421fb1fb | 800 | |
antbig | 0:ad97421fb1fb | 801 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ |
antbig | 0:ad97421fb1fb | 802 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
antbig | 0:ad97421fb1fb | 803 | |
antbig | 0:ad97421fb1fb | 804 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ |
antbig | 0:ad97421fb1fb | 805 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
antbig | 0:ad97421fb1fb | 806 | |
antbig | 0:ad97421fb1fb | 807 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ |
antbig | 0:ad97421fb1fb | 808 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
antbig | 0:ad97421fb1fb | 809 | |
antbig | 0:ad97421fb1fb | 810 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ |
antbig | 0:ad97421fb1fb | 811 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
antbig | 0:ad97421fb1fb | 812 | |
antbig | 0:ad97421fb1fb | 813 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ |
antbig | 0:ad97421fb1fb | 814 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ |
antbig | 0:ad97421fb1fb | 815 | |
antbig | 0:ad97421fb1fb | 816 | /*@}*/ /* end of group CMSIS_DWT */ |
antbig | 0:ad97421fb1fb | 817 | |
antbig | 0:ad97421fb1fb | 818 | |
antbig | 0:ad97421fb1fb | 819 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 820 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
antbig | 0:ad97421fb1fb | 821 | \brief Type definitions for the Trace Port Interface (TPI) |
antbig | 0:ad97421fb1fb | 822 | @{ |
antbig | 0:ad97421fb1fb | 823 | */ |
antbig | 0:ad97421fb1fb | 824 | |
antbig | 0:ad97421fb1fb | 825 | /** \brief Structure type to access the Trace Port Interface Register (TPI). |
antbig | 0:ad97421fb1fb | 826 | */ |
antbig | 0:ad97421fb1fb | 827 | typedef struct |
antbig | 0:ad97421fb1fb | 828 | { |
antbig | 0:ad97421fb1fb | 829 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
antbig | 0:ad97421fb1fb | 830 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
antbig | 0:ad97421fb1fb | 831 | uint32_t RESERVED0[2]; |
antbig | 0:ad97421fb1fb | 832 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
antbig | 0:ad97421fb1fb | 833 | uint32_t RESERVED1[55]; |
antbig | 0:ad97421fb1fb | 834 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
antbig | 0:ad97421fb1fb | 835 | uint32_t RESERVED2[131]; |
antbig | 0:ad97421fb1fb | 836 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
antbig | 0:ad97421fb1fb | 837 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
antbig | 0:ad97421fb1fb | 838 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
antbig | 0:ad97421fb1fb | 839 | uint32_t RESERVED3[759]; |
antbig | 0:ad97421fb1fb | 840 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
antbig | 0:ad97421fb1fb | 841 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
antbig | 0:ad97421fb1fb | 842 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
antbig | 0:ad97421fb1fb | 843 | uint32_t RESERVED4[1]; |
antbig | 0:ad97421fb1fb | 844 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
antbig | 0:ad97421fb1fb | 845 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
antbig | 0:ad97421fb1fb | 846 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
antbig | 0:ad97421fb1fb | 847 | uint32_t RESERVED5[39]; |
antbig | 0:ad97421fb1fb | 848 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
antbig | 0:ad97421fb1fb | 849 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
antbig | 0:ad97421fb1fb | 850 | uint32_t RESERVED7[8]; |
antbig | 0:ad97421fb1fb | 851 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
antbig | 0:ad97421fb1fb | 852 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
antbig | 0:ad97421fb1fb | 853 | } TPI_Type; |
antbig | 0:ad97421fb1fb | 854 | |
antbig | 0:ad97421fb1fb | 855 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
antbig | 0:ad97421fb1fb | 856 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ |
antbig | 0:ad97421fb1fb | 857 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ |
antbig | 0:ad97421fb1fb | 858 | |
antbig | 0:ad97421fb1fb | 859 | /* TPI Selected Pin Protocol Register Definitions */ |
antbig | 0:ad97421fb1fb | 860 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ |
antbig | 0:ad97421fb1fb | 861 | #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ |
antbig | 0:ad97421fb1fb | 862 | |
antbig | 0:ad97421fb1fb | 863 | /* TPI Formatter and Flush Status Register Definitions */ |
antbig | 0:ad97421fb1fb | 864 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ |
antbig | 0:ad97421fb1fb | 865 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
antbig | 0:ad97421fb1fb | 866 | |
antbig | 0:ad97421fb1fb | 867 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ |
antbig | 0:ad97421fb1fb | 868 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
antbig | 0:ad97421fb1fb | 869 | |
antbig | 0:ad97421fb1fb | 870 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ |
antbig | 0:ad97421fb1fb | 871 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
antbig | 0:ad97421fb1fb | 872 | |
antbig | 0:ad97421fb1fb | 873 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ |
antbig | 0:ad97421fb1fb | 874 | #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ |
antbig | 0:ad97421fb1fb | 875 | |
antbig | 0:ad97421fb1fb | 876 | /* TPI Formatter and Flush Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 877 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ |
antbig | 0:ad97421fb1fb | 878 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
antbig | 0:ad97421fb1fb | 879 | |
antbig | 0:ad97421fb1fb | 880 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ |
antbig | 0:ad97421fb1fb | 881 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
antbig | 0:ad97421fb1fb | 882 | |
antbig | 0:ad97421fb1fb | 883 | /* TPI TRIGGER Register Definitions */ |
antbig | 0:ad97421fb1fb | 884 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ |
antbig | 0:ad97421fb1fb | 885 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ |
antbig | 0:ad97421fb1fb | 886 | |
antbig | 0:ad97421fb1fb | 887 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
antbig | 0:ad97421fb1fb | 888 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ |
antbig | 0:ad97421fb1fb | 889 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
antbig | 0:ad97421fb1fb | 890 | |
antbig | 0:ad97421fb1fb | 891 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ |
antbig | 0:ad97421fb1fb | 892 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
antbig | 0:ad97421fb1fb | 893 | |
antbig | 0:ad97421fb1fb | 894 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ |
antbig | 0:ad97421fb1fb | 895 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
antbig | 0:ad97421fb1fb | 896 | |
antbig | 0:ad97421fb1fb | 897 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ |
antbig | 0:ad97421fb1fb | 898 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
antbig | 0:ad97421fb1fb | 899 | |
antbig | 0:ad97421fb1fb | 900 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ |
antbig | 0:ad97421fb1fb | 901 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
antbig | 0:ad97421fb1fb | 902 | |
antbig | 0:ad97421fb1fb | 903 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ |
antbig | 0:ad97421fb1fb | 904 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
antbig | 0:ad97421fb1fb | 905 | |
antbig | 0:ad97421fb1fb | 906 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ |
antbig | 0:ad97421fb1fb | 907 | #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ |
antbig | 0:ad97421fb1fb | 908 | |
antbig | 0:ad97421fb1fb | 909 | /* TPI ITATBCTR2 Register Definitions */ |
antbig | 0:ad97421fb1fb | 910 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ |
antbig | 0:ad97421fb1fb | 911 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ |
antbig | 0:ad97421fb1fb | 912 | |
antbig | 0:ad97421fb1fb | 913 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
antbig | 0:ad97421fb1fb | 914 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ |
antbig | 0:ad97421fb1fb | 915 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
antbig | 0:ad97421fb1fb | 916 | |
antbig | 0:ad97421fb1fb | 917 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ |
antbig | 0:ad97421fb1fb | 918 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
antbig | 0:ad97421fb1fb | 919 | |
antbig | 0:ad97421fb1fb | 920 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ |
antbig | 0:ad97421fb1fb | 921 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
antbig | 0:ad97421fb1fb | 922 | |
antbig | 0:ad97421fb1fb | 923 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ |
antbig | 0:ad97421fb1fb | 924 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
antbig | 0:ad97421fb1fb | 925 | |
antbig | 0:ad97421fb1fb | 926 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ |
antbig | 0:ad97421fb1fb | 927 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
antbig | 0:ad97421fb1fb | 928 | |
antbig | 0:ad97421fb1fb | 929 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ |
antbig | 0:ad97421fb1fb | 930 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
antbig | 0:ad97421fb1fb | 931 | |
antbig | 0:ad97421fb1fb | 932 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ |
antbig | 0:ad97421fb1fb | 933 | #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ |
antbig | 0:ad97421fb1fb | 934 | |
antbig | 0:ad97421fb1fb | 935 | /* TPI ITATBCTR0 Register Definitions */ |
antbig | 0:ad97421fb1fb | 936 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ |
antbig | 0:ad97421fb1fb | 937 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ |
antbig | 0:ad97421fb1fb | 938 | |
antbig | 0:ad97421fb1fb | 939 | /* TPI Integration Mode Control Register Definitions */ |
antbig | 0:ad97421fb1fb | 940 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ |
antbig | 0:ad97421fb1fb | 941 | #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ |
antbig | 0:ad97421fb1fb | 942 | |
antbig | 0:ad97421fb1fb | 943 | /* TPI DEVID Register Definitions */ |
antbig | 0:ad97421fb1fb | 944 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ |
antbig | 0:ad97421fb1fb | 945 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
antbig | 0:ad97421fb1fb | 946 | |
antbig | 0:ad97421fb1fb | 947 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ |
antbig | 0:ad97421fb1fb | 948 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
antbig | 0:ad97421fb1fb | 949 | |
antbig | 0:ad97421fb1fb | 950 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ |
antbig | 0:ad97421fb1fb | 951 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
antbig | 0:ad97421fb1fb | 952 | |
antbig | 0:ad97421fb1fb | 953 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ |
antbig | 0:ad97421fb1fb | 954 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
antbig | 0:ad97421fb1fb | 955 | |
antbig | 0:ad97421fb1fb | 956 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ |
antbig | 0:ad97421fb1fb | 957 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
antbig | 0:ad97421fb1fb | 958 | |
antbig | 0:ad97421fb1fb | 959 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ |
antbig | 0:ad97421fb1fb | 960 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ |
antbig | 0:ad97421fb1fb | 961 | |
antbig | 0:ad97421fb1fb | 962 | /* TPI DEVTYPE Register Definitions */ |
antbig | 0:ad97421fb1fb | 963 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ |
antbig | 0:ad97421fb1fb | 964 | #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ |
antbig | 0:ad97421fb1fb | 965 | |
antbig | 0:ad97421fb1fb | 966 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ |
antbig | 0:ad97421fb1fb | 967 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
antbig | 0:ad97421fb1fb | 968 | |
antbig | 0:ad97421fb1fb | 969 | /*@}*/ /* end of group CMSIS_TPI */ |
antbig | 0:ad97421fb1fb | 970 | |
antbig | 0:ad97421fb1fb | 971 | |
antbig | 0:ad97421fb1fb | 972 | #if (__MPU_PRESENT == 1) |
antbig | 0:ad97421fb1fb | 973 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 974 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
antbig | 0:ad97421fb1fb | 975 | \brief Type definitions for the Memory Protection Unit (MPU) |
antbig | 0:ad97421fb1fb | 976 | @{ |
antbig | 0:ad97421fb1fb | 977 | */ |
antbig | 0:ad97421fb1fb | 978 | |
antbig | 0:ad97421fb1fb | 979 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
antbig | 0:ad97421fb1fb | 980 | */ |
antbig | 0:ad97421fb1fb | 981 | typedef struct |
antbig | 0:ad97421fb1fb | 982 | { |
antbig | 0:ad97421fb1fb | 983 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
antbig | 0:ad97421fb1fb | 984 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
antbig | 0:ad97421fb1fb | 985 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
antbig | 0:ad97421fb1fb | 986 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
antbig | 0:ad97421fb1fb | 987 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
antbig | 0:ad97421fb1fb | 988 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
antbig | 0:ad97421fb1fb | 989 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
antbig | 0:ad97421fb1fb | 990 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
antbig | 0:ad97421fb1fb | 991 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
antbig | 0:ad97421fb1fb | 992 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
antbig | 0:ad97421fb1fb | 993 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
antbig | 0:ad97421fb1fb | 994 | } MPU_Type; |
antbig | 0:ad97421fb1fb | 995 | |
antbig | 0:ad97421fb1fb | 996 | /* MPU Type Register */ |
antbig | 0:ad97421fb1fb | 997 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
antbig | 0:ad97421fb1fb | 998 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
antbig | 0:ad97421fb1fb | 999 | |
antbig | 0:ad97421fb1fb | 1000 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
antbig | 0:ad97421fb1fb | 1001 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
antbig | 0:ad97421fb1fb | 1002 | |
antbig | 0:ad97421fb1fb | 1003 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
antbig | 0:ad97421fb1fb | 1004 | #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
antbig | 0:ad97421fb1fb | 1005 | |
antbig | 0:ad97421fb1fb | 1006 | /* MPU Control Register */ |
antbig | 0:ad97421fb1fb | 1007 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
antbig | 0:ad97421fb1fb | 1008 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
antbig | 0:ad97421fb1fb | 1009 | |
antbig | 0:ad97421fb1fb | 1010 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
antbig | 0:ad97421fb1fb | 1011 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
antbig | 0:ad97421fb1fb | 1012 | |
antbig | 0:ad97421fb1fb | 1013 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
antbig | 0:ad97421fb1fb | 1014 | #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
antbig | 0:ad97421fb1fb | 1015 | |
antbig | 0:ad97421fb1fb | 1016 | /* MPU Region Number Register */ |
antbig | 0:ad97421fb1fb | 1017 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
antbig | 0:ad97421fb1fb | 1018 | #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
antbig | 0:ad97421fb1fb | 1019 | |
antbig | 0:ad97421fb1fb | 1020 | /* MPU Region Base Address Register */ |
antbig | 0:ad97421fb1fb | 1021 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
antbig | 0:ad97421fb1fb | 1022 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
antbig | 0:ad97421fb1fb | 1023 | |
antbig | 0:ad97421fb1fb | 1024 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
antbig | 0:ad97421fb1fb | 1025 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
antbig | 0:ad97421fb1fb | 1026 | |
antbig | 0:ad97421fb1fb | 1027 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
antbig | 0:ad97421fb1fb | 1028 | #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
antbig | 0:ad97421fb1fb | 1029 | |
antbig | 0:ad97421fb1fb | 1030 | /* MPU Region Attribute and Size Register */ |
antbig | 0:ad97421fb1fb | 1031 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
antbig | 0:ad97421fb1fb | 1032 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
antbig | 0:ad97421fb1fb | 1033 | |
antbig | 0:ad97421fb1fb | 1034 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
antbig | 0:ad97421fb1fb | 1035 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
antbig | 0:ad97421fb1fb | 1036 | |
antbig | 0:ad97421fb1fb | 1037 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
antbig | 0:ad97421fb1fb | 1038 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
antbig | 0:ad97421fb1fb | 1039 | |
antbig | 0:ad97421fb1fb | 1040 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
antbig | 0:ad97421fb1fb | 1041 | #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
antbig | 0:ad97421fb1fb | 1042 | |
antbig | 0:ad97421fb1fb | 1043 | /*@} end of group CMSIS_MPU */ |
antbig | 0:ad97421fb1fb | 1044 | #endif |
antbig | 0:ad97421fb1fb | 1045 | |
antbig | 0:ad97421fb1fb | 1046 | |
antbig | 0:ad97421fb1fb | 1047 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 1048 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
antbig | 0:ad97421fb1fb | 1049 | \brief Type definitions for the Core Debug Registers |
antbig | 0:ad97421fb1fb | 1050 | @{ |
antbig | 0:ad97421fb1fb | 1051 | */ |
antbig | 0:ad97421fb1fb | 1052 | |
antbig | 0:ad97421fb1fb | 1053 | /** \brief Structure type to access the Core Debug Register (CoreDebug). |
antbig | 0:ad97421fb1fb | 1054 | */ |
antbig | 0:ad97421fb1fb | 1055 | typedef struct |
antbig | 0:ad97421fb1fb | 1056 | { |
antbig | 0:ad97421fb1fb | 1057 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
antbig | 0:ad97421fb1fb | 1058 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
antbig | 0:ad97421fb1fb | 1059 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
antbig | 0:ad97421fb1fb | 1060 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
antbig | 0:ad97421fb1fb | 1061 | } CoreDebug_Type; |
antbig | 0:ad97421fb1fb | 1062 | |
antbig | 0:ad97421fb1fb | 1063 | /* Debug Halting Control and Status Register */ |
antbig | 0:ad97421fb1fb | 1064 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
antbig | 0:ad97421fb1fb | 1065 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
antbig | 0:ad97421fb1fb | 1066 | |
antbig | 0:ad97421fb1fb | 1067 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
antbig | 0:ad97421fb1fb | 1068 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
antbig | 0:ad97421fb1fb | 1069 | |
antbig | 0:ad97421fb1fb | 1070 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
antbig | 0:ad97421fb1fb | 1071 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
antbig | 0:ad97421fb1fb | 1072 | |
antbig | 0:ad97421fb1fb | 1073 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
antbig | 0:ad97421fb1fb | 1074 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
antbig | 0:ad97421fb1fb | 1075 | |
antbig | 0:ad97421fb1fb | 1076 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
antbig | 0:ad97421fb1fb | 1077 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
antbig | 0:ad97421fb1fb | 1078 | |
antbig | 0:ad97421fb1fb | 1079 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
antbig | 0:ad97421fb1fb | 1080 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
antbig | 0:ad97421fb1fb | 1081 | |
antbig | 0:ad97421fb1fb | 1082 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
antbig | 0:ad97421fb1fb | 1083 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
antbig | 0:ad97421fb1fb | 1084 | |
antbig | 0:ad97421fb1fb | 1085 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
antbig | 0:ad97421fb1fb | 1086 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
antbig | 0:ad97421fb1fb | 1087 | |
antbig | 0:ad97421fb1fb | 1088 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
antbig | 0:ad97421fb1fb | 1089 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
antbig | 0:ad97421fb1fb | 1090 | |
antbig | 0:ad97421fb1fb | 1091 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
antbig | 0:ad97421fb1fb | 1092 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
antbig | 0:ad97421fb1fb | 1093 | |
antbig | 0:ad97421fb1fb | 1094 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
antbig | 0:ad97421fb1fb | 1095 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
antbig | 0:ad97421fb1fb | 1096 | |
antbig | 0:ad97421fb1fb | 1097 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
antbig | 0:ad97421fb1fb | 1098 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
antbig | 0:ad97421fb1fb | 1099 | |
antbig | 0:ad97421fb1fb | 1100 | /* Debug Core Register Selector Register */ |
antbig | 0:ad97421fb1fb | 1101 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
antbig | 0:ad97421fb1fb | 1102 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
antbig | 0:ad97421fb1fb | 1103 | |
antbig | 0:ad97421fb1fb | 1104 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
antbig | 0:ad97421fb1fb | 1105 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
antbig | 0:ad97421fb1fb | 1106 | |
antbig | 0:ad97421fb1fb | 1107 | /* Debug Exception and Monitor Control Register */ |
antbig | 0:ad97421fb1fb | 1108 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
antbig | 0:ad97421fb1fb | 1109 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
antbig | 0:ad97421fb1fb | 1110 | |
antbig | 0:ad97421fb1fb | 1111 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
antbig | 0:ad97421fb1fb | 1112 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
antbig | 0:ad97421fb1fb | 1113 | |
antbig | 0:ad97421fb1fb | 1114 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
antbig | 0:ad97421fb1fb | 1115 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
antbig | 0:ad97421fb1fb | 1116 | |
antbig | 0:ad97421fb1fb | 1117 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
antbig | 0:ad97421fb1fb | 1118 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
antbig | 0:ad97421fb1fb | 1119 | |
antbig | 0:ad97421fb1fb | 1120 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
antbig | 0:ad97421fb1fb | 1121 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
antbig | 0:ad97421fb1fb | 1122 | |
antbig | 0:ad97421fb1fb | 1123 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
antbig | 0:ad97421fb1fb | 1124 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
antbig | 0:ad97421fb1fb | 1125 | |
antbig | 0:ad97421fb1fb | 1126 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
antbig | 0:ad97421fb1fb | 1127 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
antbig | 0:ad97421fb1fb | 1128 | |
antbig | 0:ad97421fb1fb | 1129 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
antbig | 0:ad97421fb1fb | 1130 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
antbig | 0:ad97421fb1fb | 1131 | |
antbig | 0:ad97421fb1fb | 1132 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
antbig | 0:ad97421fb1fb | 1133 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
antbig | 0:ad97421fb1fb | 1134 | |
antbig | 0:ad97421fb1fb | 1135 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
antbig | 0:ad97421fb1fb | 1136 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
antbig | 0:ad97421fb1fb | 1137 | |
antbig | 0:ad97421fb1fb | 1138 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
antbig | 0:ad97421fb1fb | 1139 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
antbig | 0:ad97421fb1fb | 1140 | |
antbig | 0:ad97421fb1fb | 1141 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
antbig | 0:ad97421fb1fb | 1142 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
antbig | 0:ad97421fb1fb | 1143 | |
antbig | 0:ad97421fb1fb | 1144 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
antbig | 0:ad97421fb1fb | 1145 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
antbig | 0:ad97421fb1fb | 1146 | |
antbig | 0:ad97421fb1fb | 1147 | /*@} end of group CMSIS_CoreDebug */ |
antbig | 0:ad97421fb1fb | 1148 | |
antbig | 0:ad97421fb1fb | 1149 | |
antbig | 0:ad97421fb1fb | 1150 | /** \ingroup CMSIS_core_register |
antbig | 0:ad97421fb1fb | 1151 | \defgroup CMSIS_core_base Core Definitions |
antbig | 0:ad97421fb1fb | 1152 | \brief Definitions for base addresses, unions, and structures. |
antbig | 0:ad97421fb1fb | 1153 | @{ |
antbig | 0:ad97421fb1fb | 1154 | */ |
antbig | 0:ad97421fb1fb | 1155 | |
antbig | 0:ad97421fb1fb | 1156 | /* Memory mapping of Cortex-M3 Hardware */ |
antbig | 0:ad97421fb1fb | 1157 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
antbig | 0:ad97421fb1fb | 1158 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
antbig | 0:ad97421fb1fb | 1159 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
antbig | 0:ad97421fb1fb | 1160 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
antbig | 0:ad97421fb1fb | 1161 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
antbig | 0:ad97421fb1fb | 1162 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
antbig | 0:ad97421fb1fb | 1163 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
antbig | 0:ad97421fb1fb | 1164 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
antbig | 0:ad97421fb1fb | 1165 | |
antbig | 0:ad97421fb1fb | 1166 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
antbig | 0:ad97421fb1fb | 1167 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
antbig | 0:ad97421fb1fb | 1168 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
antbig | 0:ad97421fb1fb | 1169 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
antbig | 0:ad97421fb1fb | 1170 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
antbig | 0:ad97421fb1fb | 1171 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
antbig | 0:ad97421fb1fb | 1172 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
antbig | 0:ad97421fb1fb | 1173 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
antbig | 0:ad97421fb1fb | 1174 | |
antbig | 0:ad97421fb1fb | 1175 | #if (__MPU_PRESENT == 1) |
antbig | 0:ad97421fb1fb | 1176 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
antbig | 0:ad97421fb1fb | 1177 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
antbig | 0:ad97421fb1fb | 1178 | #endif |
antbig | 0:ad97421fb1fb | 1179 | |
antbig | 0:ad97421fb1fb | 1180 | /*@} */ |
antbig | 0:ad97421fb1fb | 1181 | |
antbig | 0:ad97421fb1fb | 1182 | |
antbig | 0:ad97421fb1fb | 1183 | |
antbig | 0:ad97421fb1fb | 1184 | /******************************************************************************* |
antbig | 0:ad97421fb1fb | 1185 | * Hardware Abstraction Layer |
antbig | 0:ad97421fb1fb | 1186 | Core Function Interface contains: |
antbig | 0:ad97421fb1fb | 1187 | - Core NVIC Functions |
antbig | 0:ad97421fb1fb | 1188 | - Core SysTick Functions |
antbig | 0:ad97421fb1fb | 1189 | - Core Debug Functions |
antbig | 0:ad97421fb1fb | 1190 | - Core Register Access Functions |
antbig | 0:ad97421fb1fb | 1191 | ******************************************************************************/ |
antbig | 0:ad97421fb1fb | 1192 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
antbig | 0:ad97421fb1fb | 1193 | */ |
antbig | 0:ad97421fb1fb | 1194 | |
antbig | 0:ad97421fb1fb | 1195 | |
antbig | 0:ad97421fb1fb | 1196 | |
antbig | 0:ad97421fb1fb | 1197 | /* ########################## NVIC functions #################################### */ |
antbig | 0:ad97421fb1fb | 1198 | /** \ingroup CMSIS_Core_FunctionInterface |
antbig | 0:ad97421fb1fb | 1199 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
antbig | 0:ad97421fb1fb | 1200 | \brief Functions that manage interrupts and exceptions via the NVIC. |
antbig | 0:ad97421fb1fb | 1201 | @{ |
antbig | 0:ad97421fb1fb | 1202 | */ |
antbig | 0:ad97421fb1fb | 1203 | |
antbig | 0:ad97421fb1fb | 1204 | /** \brief Set Priority Grouping |
antbig | 0:ad97421fb1fb | 1205 | |
antbig | 0:ad97421fb1fb | 1206 | The function sets the priority grouping field using the required unlock sequence. |
antbig | 0:ad97421fb1fb | 1207 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
antbig | 0:ad97421fb1fb | 1208 | Only values from 0..7 are used. |
antbig | 0:ad97421fb1fb | 1209 | In case of a conflict between priority grouping and available |
antbig | 0:ad97421fb1fb | 1210 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
antbig | 0:ad97421fb1fb | 1211 | |
antbig | 0:ad97421fb1fb | 1212 | \param [in] PriorityGroup Priority grouping field. |
antbig | 0:ad97421fb1fb | 1213 | */ |
antbig | 0:ad97421fb1fb | 1214 | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
antbig | 0:ad97421fb1fb | 1215 | { |
antbig | 0:ad97421fb1fb | 1216 | uint32_t reg_value; |
antbig | 0:ad97421fb1fb | 1217 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ |
antbig | 0:ad97421fb1fb | 1218 | |
antbig | 0:ad97421fb1fb | 1219 | reg_value = SCB->AIRCR; /* read old register configuration */ |
antbig | 0:ad97421fb1fb | 1220 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ |
antbig | 0:ad97421fb1fb | 1221 | reg_value = (reg_value | |
antbig | 0:ad97421fb1fb | 1222 | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
antbig | 0:ad97421fb1fb | 1223 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
antbig | 0:ad97421fb1fb | 1224 | SCB->AIRCR = reg_value; |
antbig | 0:ad97421fb1fb | 1225 | } |
antbig | 0:ad97421fb1fb | 1226 | |
antbig | 0:ad97421fb1fb | 1227 | |
antbig | 0:ad97421fb1fb | 1228 | /** \brief Get Priority Grouping |
antbig | 0:ad97421fb1fb | 1229 | |
antbig | 0:ad97421fb1fb | 1230 | The function reads the priority grouping field from the NVIC Interrupt Controller. |
antbig | 0:ad97421fb1fb | 1231 | |
antbig | 0:ad97421fb1fb | 1232 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
antbig | 0:ad97421fb1fb | 1233 | */ |
antbig | 0:ad97421fb1fb | 1234 | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) |
antbig | 0:ad97421fb1fb | 1235 | { |
antbig | 0:ad97421fb1fb | 1236 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
antbig | 0:ad97421fb1fb | 1237 | } |
antbig | 0:ad97421fb1fb | 1238 | |
antbig | 0:ad97421fb1fb | 1239 | |
antbig | 0:ad97421fb1fb | 1240 | /** \brief Enable External Interrupt |
antbig | 0:ad97421fb1fb | 1241 | |
antbig | 0:ad97421fb1fb | 1242 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
antbig | 0:ad97421fb1fb | 1243 | |
antbig | 0:ad97421fb1fb | 1244 | \param [in] IRQn External interrupt number. Value cannot be negative. |
antbig | 0:ad97421fb1fb | 1245 | */ |
antbig | 0:ad97421fb1fb | 1246 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1247 | { |
antbig | 0:ad97421fb1fb | 1248 | NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
antbig | 0:ad97421fb1fb | 1249 | } |
antbig | 0:ad97421fb1fb | 1250 | |
antbig | 0:ad97421fb1fb | 1251 | |
antbig | 0:ad97421fb1fb | 1252 | /** \brief Disable External Interrupt |
antbig | 0:ad97421fb1fb | 1253 | |
antbig | 0:ad97421fb1fb | 1254 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
antbig | 0:ad97421fb1fb | 1255 | |
antbig | 0:ad97421fb1fb | 1256 | \param [in] IRQn External interrupt number. Value cannot be negative. |
antbig | 0:ad97421fb1fb | 1257 | */ |
antbig | 0:ad97421fb1fb | 1258 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1259 | { |
antbig | 0:ad97421fb1fb | 1260 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
antbig | 0:ad97421fb1fb | 1261 | } |
antbig | 0:ad97421fb1fb | 1262 | |
antbig | 0:ad97421fb1fb | 1263 | |
antbig | 0:ad97421fb1fb | 1264 | /** \brief Get Pending Interrupt |
antbig | 0:ad97421fb1fb | 1265 | |
antbig | 0:ad97421fb1fb | 1266 | The function reads the pending register in the NVIC and returns the pending bit |
antbig | 0:ad97421fb1fb | 1267 | for the specified interrupt. |
antbig | 0:ad97421fb1fb | 1268 | |
antbig | 0:ad97421fb1fb | 1269 | \param [in] IRQn Interrupt number. |
antbig | 0:ad97421fb1fb | 1270 | |
antbig | 0:ad97421fb1fb | 1271 | \return 0 Interrupt status is not pending. |
antbig | 0:ad97421fb1fb | 1272 | \return 1 Interrupt status is pending. |
antbig | 0:ad97421fb1fb | 1273 | */ |
antbig | 0:ad97421fb1fb | 1274 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1275 | { |
antbig | 0:ad97421fb1fb | 1276 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
antbig | 0:ad97421fb1fb | 1277 | } |
antbig | 0:ad97421fb1fb | 1278 | |
antbig | 0:ad97421fb1fb | 1279 | |
antbig | 0:ad97421fb1fb | 1280 | /** \brief Set Pending Interrupt |
antbig | 0:ad97421fb1fb | 1281 | |
antbig | 0:ad97421fb1fb | 1282 | The function sets the pending bit of an external interrupt. |
antbig | 0:ad97421fb1fb | 1283 | |
antbig | 0:ad97421fb1fb | 1284 | \param [in] IRQn Interrupt number. Value cannot be negative. |
antbig | 0:ad97421fb1fb | 1285 | */ |
antbig | 0:ad97421fb1fb | 1286 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1287 | { |
antbig | 0:ad97421fb1fb | 1288 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
antbig | 0:ad97421fb1fb | 1289 | } |
antbig | 0:ad97421fb1fb | 1290 | |
antbig | 0:ad97421fb1fb | 1291 | |
antbig | 0:ad97421fb1fb | 1292 | /** \brief Clear Pending Interrupt |
antbig | 0:ad97421fb1fb | 1293 | |
antbig | 0:ad97421fb1fb | 1294 | The function clears the pending bit of an external interrupt. |
antbig | 0:ad97421fb1fb | 1295 | |
antbig | 0:ad97421fb1fb | 1296 | \param [in] IRQn External interrupt number. Value cannot be negative. |
antbig | 0:ad97421fb1fb | 1297 | */ |
antbig | 0:ad97421fb1fb | 1298 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1299 | { |
antbig | 0:ad97421fb1fb | 1300 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
antbig | 0:ad97421fb1fb | 1301 | } |
antbig | 0:ad97421fb1fb | 1302 | |
antbig | 0:ad97421fb1fb | 1303 | |
antbig | 0:ad97421fb1fb | 1304 | /** \brief Get Active Interrupt |
antbig | 0:ad97421fb1fb | 1305 | |
antbig | 0:ad97421fb1fb | 1306 | The function reads the active register in NVIC and returns the active bit. |
antbig | 0:ad97421fb1fb | 1307 | |
antbig | 0:ad97421fb1fb | 1308 | \param [in] IRQn Interrupt number. |
antbig | 0:ad97421fb1fb | 1309 | |
antbig | 0:ad97421fb1fb | 1310 | \return 0 Interrupt status is not active. |
antbig | 0:ad97421fb1fb | 1311 | \return 1 Interrupt status is active. |
antbig | 0:ad97421fb1fb | 1312 | */ |
antbig | 0:ad97421fb1fb | 1313 | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1314 | { |
antbig | 0:ad97421fb1fb | 1315 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
antbig | 0:ad97421fb1fb | 1316 | } |
antbig | 0:ad97421fb1fb | 1317 | |
antbig | 0:ad97421fb1fb | 1318 | |
antbig | 0:ad97421fb1fb | 1319 | /** \brief Set Interrupt Priority |
antbig | 0:ad97421fb1fb | 1320 | |
antbig | 0:ad97421fb1fb | 1321 | The function sets the priority of an interrupt. |
antbig | 0:ad97421fb1fb | 1322 | |
antbig | 0:ad97421fb1fb | 1323 | \note The priority cannot be set for every core interrupt. |
antbig | 0:ad97421fb1fb | 1324 | |
antbig | 0:ad97421fb1fb | 1325 | \param [in] IRQn Interrupt number. |
antbig | 0:ad97421fb1fb | 1326 | \param [in] priority Priority to set. |
antbig | 0:ad97421fb1fb | 1327 | */ |
antbig | 0:ad97421fb1fb | 1328 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
antbig | 0:ad97421fb1fb | 1329 | { |
antbig | 0:ad97421fb1fb | 1330 | if(IRQn < 0) { |
antbig | 0:ad97421fb1fb | 1331 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ |
antbig | 0:ad97421fb1fb | 1332 | else { |
antbig | 0:ad97421fb1fb | 1333 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
antbig | 0:ad97421fb1fb | 1334 | } |
antbig | 0:ad97421fb1fb | 1335 | |
antbig | 0:ad97421fb1fb | 1336 | |
antbig | 0:ad97421fb1fb | 1337 | /** \brief Get Interrupt Priority |
antbig | 0:ad97421fb1fb | 1338 | |
antbig | 0:ad97421fb1fb | 1339 | The function reads the priority of an interrupt. The interrupt |
antbig | 0:ad97421fb1fb | 1340 | number can be positive to specify an external (device specific) |
antbig | 0:ad97421fb1fb | 1341 | interrupt, or negative to specify an internal (core) interrupt. |
antbig | 0:ad97421fb1fb | 1342 | |
antbig | 0:ad97421fb1fb | 1343 | |
antbig | 0:ad97421fb1fb | 1344 | \param [in] IRQn Interrupt number. |
antbig | 0:ad97421fb1fb | 1345 | \return Interrupt Priority. Value is aligned automatically to the implemented |
antbig | 0:ad97421fb1fb | 1346 | priority bits of the microcontroller. |
antbig | 0:ad97421fb1fb | 1347 | */ |
antbig | 0:ad97421fb1fb | 1348 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
antbig | 0:ad97421fb1fb | 1349 | { |
antbig | 0:ad97421fb1fb | 1350 | |
antbig | 0:ad97421fb1fb | 1351 | if(IRQn < 0) { |
antbig | 0:ad97421fb1fb | 1352 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ |
antbig | 0:ad97421fb1fb | 1353 | else { |
antbig | 0:ad97421fb1fb | 1354 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
antbig | 0:ad97421fb1fb | 1355 | } |
antbig | 0:ad97421fb1fb | 1356 | |
antbig | 0:ad97421fb1fb | 1357 | |
antbig | 0:ad97421fb1fb | 1358 | /** \brief Encode Priority |
antbig | 0:ad97421fb1fb | 1359 | |
antbig | 0:ad97421fb1fb | 1360 | The function encodes the priority for an interrupt with the given priority group, |
antbig | 0:ad97421fb1fb | 1361 | preemptive priority value, and subpriority value. |
antbig | 0:ad97421fb1fb | 1362 | In case of a conflict between priority grouping and available |
antbig | 0:ad97421fb1fb | 1363 | priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. |
antbig | 0:ad97421fb1fb | 1364 | |
antbig | 0:ad97421fb1fb | 1365 | \param [in] PriorityGroup Used priority group. |
antbig | 0:ad97421fb1fb | 1366 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
antbig | 0:ad97421fb1fb | 1367 | \param [in] SubPriority Subpriority value (starting from 0). |
antbig | 0:ad97421fb1fb | 1368 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
antbig | 0:ad97421fb1fb | 1369 | */ |
antbig | 0:ad97421fb1fb | 1370 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
antbig | 0:ad97421fb1fb | 1371 | { |
antbig | 0:ad97421fb1fb | 1372 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
antbig | 0:ad97421fb1fb | 1373 | uint32_t PreemptPriorityBits; |
antbig | 0:ad97421fb1fb | 1374 | uint32_t SubPriorityBits; |
antbig | 0:ad97421fb1fb | 1375 | |
antbig | 0:ad97421fb1fb | 1376 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
antbig | 0:ad97421fb1fb | 1377 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
antbig | 0:ad97421fb1fb | 1378 | |
antbig | 0:ad97421fb1fb | 1379 | return ( |
antbig | 0:ad97421fb1fb | 1380 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
antbig | 0:ad97421fb1fb | 1381 | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
antbig | 0:ad97421fb1fb | 1382 | ); |
antbig | 0:ad97421fb1fb | 1383 | } |
antbig | 0:ad97421fb1fb | 1384 | |
antbig | 0:ad97421fb1fb | 1385 | |
antbig | 0:ad97421fb1fb | 1386 | /** \brief Decode Priority |
antbig | 0:ad97421fb1fb | 1387 | |
antbig | 0:ad97421fb1fb | 1388 | The function decodes an interrupt priority value with a given priority group to |
antbig | 0:ad97421fb1fb | 1389 | preemptive priority value and subpriority value. |
antbig | 0:ad97421fb1fb | 1390 | In case of a conflict between priority grouping and available |
antbig | 0:ad97421fb1fb | 1391 | priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
antbig | 0:ad97421fb1fb | 1392 | |
antbig | 0:ad97421fb1fb | 1393 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
antbig | 0:ad97421fb1fb | 1394 | \param [in] PriorityGroup Used priority group. |
antbig | 0:ad97421fb1fb | 1395 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
antbig | 0:ad97421fb1fb | 1396 | \param [out] pSubPriority Subpriority value (starting from 0). |
antbig | 0:ad97421fb1fb | 1397 | */ |
antbig | 0:ad97421fb1fb | 1398 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
antbig | 0:ad97421fb1fb | 1399 | { |
antbig | 0:ad97421fb1fb | 1400 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
antbig | 0:ad97421fb1fb | 1401 | uint32_t PreemptPriorityBits; |
antbig | 0:ad97421fb1fb | 1402 | uint32_t SubPriorityBits; |
antbig | 0:ad97421fb1fb | 1403 | |
antbig | 0:ad97421fb1fb | 1404 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
antbig | 0:ad97421fb1fb | 1405 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
antbig | 0:ad97421fb1fb | 1406 | |
antbig | 0:ad97421fb1fb | 1407 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
antbig | 0:ad97421fb1fb | 1408 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
antbig | 0:ad97421fb1fb | 1409 | } |
antbig | 0:ad97421fb1fb | 1410 | |
antbig | 0:ad97421fb1fb | 1411 | |
antbig | 0:ad97421fb1fb | 1412 | /** \brief System Reset |
antbig | 0:ad97421fb1fb | 1413 | |
antbig | 0:ad97421fb1fb | 1414 | The function initiates a system reset request to reset the MCU. |
antbig | 0:ad97421fb1fb | 1415 | */ |
antbig | 0:ad97421fb1fb | 1416 | __STATIC_INLINE void NVIC_SystemReset(void) |
antbig | 0:ad97421fb1fb | 1417 | { |
antbig | 0:ad97421fb1fb | 1418 | __DSB(); /* Ensure all outstanding memory accesses included |
antbig | 0:ad97421fb1fb | 1419 | buffered write are completed before reset */ |
antbig | 0:ad97421fb1fb | 1420 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
antbig | 0:ad97421fb1fb | 1421 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
antbig | 0:ad97421fb1fb | 1422 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ |
antbig | 0:ad97421fb1fb | 1423 | __DSB(); /* Ensure completion of memory access */ |
antbig | 0:ad97421fb1fb | 1424 | while(1); /* wait until reset */ |
antbig | 0:ad97421fb1fb | 1425 | } |
antbig | 0:ad97421fb1fb | 1426 | |
antbig | 0:ad97421fb1fb | 1427 | /*@} end of CMSIS_Core_NVICFunctions */ |
antbig | 0:ad97421fb1fb | 1428 | |
antbig | 0:ad97421fb1fb | 1429 | |
antbig | 0:ad97421fb1fb | 1430 | |
antbig | 0:ad97421fb1fb | 1431 | /* ################################## SysTick function ############################################ */ |
antbig | 0:ad97421fb1fb | 1432 | /** \ingroup CMSIS_Core_FunctionInterface |
antbig | 0:ad97421fb1fb | 1433 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
antbig | 0:ad97421fb1fb | 1434 | \brief Functions that configure the System. |
antbig | 0:ad97421fb1fb | 1435 | @{ |
antbig | 0:ad97421fb1fb | 1436 | */ |
antbig | 0:ad97421fb1fb | 1437 | |
antbig | 0:ad97421fb1fb | 1438 | #if (__Vendor_SysTickConfig == 0) |
antbig | 0:ad97421fb1fb | 1439 | |
antbig | 0:ad97421fb1fb | 1440 | /** \brief System Tick Configuration |
antbig | 0:ad97421fb1fb | 1441 | |
antbig | 0:ad97421fb1fb | 1442 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
antbig | 0:ad97421fb1fb | 1443 | Counter is in free running mode to generate periodic interrupts. |
antbig | 0:ad97421fb1fb | 1444 | |
antbig | 0:ad97421fb1fb | 1445 | \param [in] ticks Number of ticks between two interrupts. |
antbig | 0:ad97421fb1fb | 1446 | |
antbig | 0:ad97421fb1fb | 1447 | \return 0 Function succeeded. |
antbig | 0:ad97421fb1fb | 1448 | \return 1 Function failed. |
antbig | 0:ad97421fb1fb | 1449 | |
antbig | 0:ad97421fb1fb | 1450 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
antbig | 0:ad97421fb1fb | 1451 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
antbig | 0:ad97421fb1fb | 1452 | must contain a vendor-specific implementation of this function. |
antbig | 0:ad97421fb1fb | 1453 | |
antbig | 0:ad97421fb1fb | 1454 | */ |
antbig | 0:ad97421fb1fb | 1455 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
antbig | 0:ad97421fb1fb | 1456 | { |
antbig | 0:ad97421fb1fb | 1457 | if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
antbig | 0:ad97421fb1fb | 1458 | |
antbig | 0:ad97421fb1fb | 1459 | SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ |
antbig | 0:ad97421fb1fb | 1460 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
antbig | 0:ad97421fb1fb | 1461 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
antbig | 0:ad97421fb1fb | 1462 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
antbig | 0:ad97421fb1fb | 1463 | SysTick_CTRL_TICKINT_Msk | |
antbig | 0:ad97421fb1fb | 1464 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
antbig | 0:ad97421fb1fb | 1465 | return (0); /* Function successful */ |
antbig | 0:ad97421fb1fb | 1466 | } |
antbig | 0:ad97421fb1fb | 1467 | |
antbig | 0:ad97421fb1fb | 1468 | #endif |
antbig | 0:ad97421fb1fb | 1469 | |
antbig | 0:ad97421fb1fb | 1470 | /*@} end of CMSIS_Core_SysTickFunctions */ |
antbig | 0:ad97421fb1fb | 1471 | |
antbig | 0:ad97421fb1fb | 1472 | |
antbig | 0:ad97421fb1fb | 1473 | |
antbig | 0:ad97421fb1fb | 1474 | /* ##################################### Debug In/Output function ########################################### */ |
antbig | 0:ad97421fb1fb | 1475 | /** \ingroup CMSIS_Core_FunctionInterface |
antbig | 0:ad97421fb1fb | 1476 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
antbig | 0:ad97421fb1fb | 1477 | \brief Functions that access the ITM debug interface. |
antbig | 0:ad97421fb1fb | 1478 | @{ |
antbig | 0:ad97421fb1fb | 1479 | */ |
antbig | 0:ad97421fb1fb | 1480 | |
antbig | 0:ad97421fb1fb | 1481 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
antbig | 0:ad97421fb1fb | 1482 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
antbig | 0:ad97421fb1fb | 1483 | |
antbig | 0:ad97421fb1fb | 1484 | |
antbig | 0:ad97421fb1fb | 1485 | /** \brief ITM Send Character |
antbig | 0:ad97421fb1fb | 1486 | |
antbig | 0:ad97421fb1fb | 1487 | The function transmits a character via the ITM channel 0, and |
antbig | 0:ad97421fb1fb | 1488 | \li Just returns when no debugger is connected that has booked the output. |
antbig | 0:ad97421fb1fb | 1489 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
antbig | 0:ad97421fb1fb | 1490 | |
antbig | 0:ad97421fb1fb | 1491 | \param [in] ch Character to transmit. |
antbig | 0:ad97421fb1fb | 1492 | |
antbig | 0:ad97421fb1fb | 1493 | \returns Character to transmit. |
antbig | 0:ad97421fb1fb | 1494 | */ |
antbig | 0:ad97421fb1fb | 1495 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
antbig | 0:ad97421fb1fb | 1496 | { |
antbig | 0:ad97421fb1fb | 1497 | if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ |
antbig | 0:ad97421fb1fb | 1498 | (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ |
antbig | 0:ad97421fb1fb | 1499 | { |
antbig | 0:ad97421fb1fb | 1500 | while (ITM->PORT[0].u32 == 0); |
antbig | 0:ad97421fb1fb | 1501 | ITM->PORT[0].u8 = (uint8_t) ch; |
antbig | 0:ad97421fb1fb | 1502 | } |
antbig | 0:ad97421fb1fb | 1503 | return (ch); |
antbig | 0:ad97421fb1fb | 1504 | } |
antbig | 0:ad97421fb1fb | 1505 | |
antbig | 0:ad97421fb1fb | 1506 | |
antbig | 0:ad97421fb1fb | 1507 | /** \brief ITM Receive Character |
antbig | 0:ad97421fb1fb | 1508 | |
antbig | 0:ad97421fb1fb | 1509 | The function inputs a character via the external variable \ref ITM_RxBuffer. |
antbig | 0:ad97421fb1fb | 1510 | |
antbig | 0:ad97421fb1fb | 1511 | \return Received character. |
antbig | 0:ad97421fb1fb | 1512 | \return -1 No character pending. |
antbig | 0:ad97421fb1fb | 1513 | */ |
antbig | 0:ad97421fb1fb | 1514 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) { |
antbig | 0:ad97421fb1fb | 1515 | int32_t ch = -1; /* no character available */ |
antbig | 0:ad97421fb1fb | 1516 | |
antbig | 0:ad97421fb1fb | 1517 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
antbig | 0:ad97421fb1fb | 1518 | ch = ITM_RxBuffer; |
antbig | 0:ad97421fb1fb | 1519 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
antbig | 0:ad97421fb1fb | 1520 | } |
antbig | 0:ad97421fb1fb | 1521 | |
antbig | 0:ad97421fb1fb | 1522 | return (ch); |
antbig | 0:ad97421fb1fb | 1523 | } |
antbig | 0:ad97421fb1fb | 1524 | |
antbig | 0:ad97421fb1fb | 1525 | |
antbig | 0:ad97421fb1fb | 1526 | /** \brief ITM Check Character |
antbig | 0:ad97421fb1fb | 1527 | |
antbig | 0:ad97421fb1fb | 1528 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
antbig | 0:ad97421fb1fb | 1529 | |
antbig | 0:ad97421fb1fb | 1530 | \return 0 No character available. |
antbig | 0:ad97421fb1fb | 1531 | \return 1 Character available. |
antbig | 0:ad97421fb1fb | 1532 | */ |
antbig | 0:ad97421fb1fb | 1533 | __STATIC_INLINE int32_t ITM_CheckChar (void) { |
antbig | 0:ad97421fb1fb | 1534 | |
antbig | 0:ad97421fb1fb | 1535 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
antbig | 0:ad97421fb1fb | 1536 | return (0); /* no character available */ |
antbig | 0:ad97421fb1fb | 1537 | } else { |
antbig | 0:ad97421fb1fb | 1538 | return (1); /* character available */ |
antbig | 0:ad97421fb1fb | 1539 | } |
antbig | 0:ad97421fb1fb | 1540 | } |
antbig | 0:ad97421fb1fb | 1541 | |
antbig | 0:ad97421fb1fb | 1542 | /*@} end of CMSIS_core_DebugFunctions */ |
antbig | 0:ad97421fb1fb | 1543 | |
antbig | 0:ad97421fb1fb | 1544 | #endif /* __CORE_CM3_H_DEPENDANT */ |
antbig | 0:ad97421fb1fb | 1545 | |
antbig | 0:ad97421fb1fb | 1546 | #endif /* __CMSIS_GENERIC */ |
antbig | 0:ad97421fb1fb | 1547 | |
antbig | 0:ad97421fb1fb | 1548 | #ifdef __cplusplus |
antbig | 0:ad97421fb1fb | 1549 | } |
antbig | 0:ad97421fb1fb | 1550 | #endif |