lab 6

Dependencies:   ADXL362 mbed MPL3115A2

Revision:
20:8d93acd1f8cd
Parent:
19:51b2b42a82f1
Child:
21:b85d1a4f0373
--- a/main.cpp	Fri Feb 23 17:02:55 2018 +0000
+++ b/main.cpp	Fri Feb 23 17:46:12 2018 +0000
@@ -6,79 +6,179 @@
 DigitalOut led3(LED3);
 
 //map of register values and names for the adxl
-int regids[34];
-char* regnames[34];
+int aregids[34];
+char* aregnames[34];
+//populating the map
+void initmap() {
+    aregids[0] = 0x00;
+    aregids[1] = 0x01;
+    aregids[2] = 0x02;
+    aregids[3] = 0x03;
+    aregids[4] = 0x08;
+    aregids[5] = 0x09;
+    aregids[6] = 0x0A;
+    aregids[7] = 0x0B;
+    aregids[8] = 0x0c;
+    aregids[9] = 0x0D;
+    aregids[10] = 0x0E;
+    aregids[11] = 0x0F;
+    aregids[12] = 0x10;
+    aregids[13] = 0x11;
+    aregids[14] = 0x12;
+    aregids[15] = 0x13;
+    aregids[16] = 0x14;
+    aregids[17] = 0x15;
+    aregids[18] = 0x1F;
+    aregids[19] = 0x20;
+    aregids[20] = 0x21;
+    aregids[21] = 0x22;
+    aregids[22] = 0x23;
+    aregids[23] = 0x24;
+    aregids[24] = 0x25;
+    aregids[25] = 0x26;
+    aregids[26] = 0x27;
+    aregids[27] = 0x28;
+    aregids[28] = 0x29;
+    aregids[29] = 0x2A;
+    aregids[30] = 0x2B;
+    aregids[31] = 0x2C;
+    aregids[32] = 0x2D;
+    aregids[33] = 0x2E;
+    
+    aregnames[0] = "DEVID_AD";
+    aregnames[1] = "DEVID_MST";
+    aregnames[2] = "PARTID";
+    aregnames[3] = "REVID";
+    aregnames[4] = "XDATA";
+    aregnames[5] = "YDATA";
+    aregnames[6] = "ZDATA";
+    aregnames[7] = "STATUS";
+    aregnames[8] = "FIFO_ENTRIES_L";
+    aregnames[9] = "FIFO_ENTRIES_H";
+    aregnames[10] = "XDATA_L";
+    aregnames[11] = "XDATA_H";
+    aregnames[12] = "YDATA_L";
+    aregnames[13] = "YDATA_H";
+    aregnames[14] = "ZDATA_L";
+    aregnames[15] = "ZDATA_H";
+    aregnames[16] = "TEMP_L";
+    aregnames[17] = "TEMP_H";
+    aregnames[18] = "SOFT_RESET";
+    aregnames[19] = "THRESH_ACT_L";
+    aregnames[20] = "THRESH_ACT_H";
+    aregnames[21] = "TIME_ACT";
+    aregnames[22] = "THRESH_INACT_L";
+    aregnames[23] = "THRESH_INACT_H";
+    aregnames[24] = "TIME_INACT_L";
+    aregnames[25] = "TIME_INACT_H";
+    aregnames[26] = "ACT_INACT_CTL";
+    aregnames[27] = "FIFO_CONTROL";
+    aregnames[28] = "FIFO_SAMPLES";
+    aregnames[29] = "INTMAP1";
+    aregnames[30] = "INTMAP2";
+    aregnames[31] = "FILTER_CTL";
+    aregnames[32] = "POWER_CTL";
+    aregnames[33] = "SELF_TEST";
+}
+
+//map of register values and names for the adxl
+int mregids[34];
+char* mregnames[34];
 //populating the map
 void initmap() {
-    regids[0] = 0x00;
-    regids[1] = 0x01;
-    regids[2] = 0x02;
-    regids[3] = 0x03;
-    regids[4] = 0x08;
-    regids[5] = 0x09;
-    regids[6] = 0x0A;
-    regids[7] = 0x0B;
-    regids[8] = 0x0c;
-    regids[9] = 0x0D;
-    regids[10] = 0x0E;
-    regids[11] = 0x0F;
-    regids[12] = 0x10;
-    regids[13] = 0x11;
-    regids[14] = 0x12;
-    regids[15] = 0x13;
-    regids[16] = 0x14;
-    regids[17] = 0x15;
-    regids[18] = 0x1F;
-    regids[19] = 0x20;
-    regids[20] = 0x21;
-    regids[21] = 0x22;
-    regids[22] = 0x23;
-    regids[23] = 0x24;
-    regids[24] = 0x25;
-    regids[25] = 0x26;
-    regids[26] = 0x27;
-    regids[27] = 0x28;
-    regids[28] = 0x29;
-    regids[29] = 0x2A;
-    regids[30] = 0x2B;
-    regids[31] = 0x2C;
-    regids[32] = 0x2D;
-    regids[33] = 0x2E;
+    mregids[0] = 0x00;
+    mregids[1] = 0x01;
+    mregids[2] = 0x02;
+    mregids[3] = 0x03;
+    mregids[4] = 0x04;
+    mregids[5] = 0x05;
+    mregids[6] = 0x06;
+    mregids[7] = 0x07;
+    mregids[8] = 0x08;
+    mregids[9] = 0x09;
+    mregids[10] = 0x0A;
+    mregids[11] = 0x0B;
+    mregids[12] = 0x0C;
+    mregids[13] = 0x0D;
+    mregids[14] = 0x0E;
+    mregids[15] = 0x0F;
+    mregids[16] = 0x10;
+    mregids[17] = 0x11;
+    mregids[18] = 0x12;
+    mregids[19] = 0x13;
+    mregids[20] = 0x14;
+    mregids[21] = 0x15;
+    mregids[22] = 0x16;
+    mregids[23] = 0x17;
+    mregids[24] = 0x18;
+    mregids[25] = 0x19;
+    mregids[26] = 0x1A;
+    mregids[27] = 0x1B;
+    mregids[28] = 0x1C;
+    mregids[29] = 0x1D;
+    mregids[30] = 0x1E;
+    mregids[31] = 0x1F;
+    mregids[32] = 0x20;
+    mregids[33] = 0x21;
+    mregids[34] = 0x22;
+    mregids[35] = 0x23;
+    mregids[36] = 0x24;
+    mregids[37] = 0x25;
+    mregids[38] = 0x26;
+    mregids[39] = 0x27;
+    mregids[40] = 0x28;
+    mregids[41] = 0x29;
+    mregids[42] = 0x2A;
+    mregids[43] = 0x2B;
+    mregids[44] = 0x2C;
+    mregids[45] = 0x2D;
     
-    regnames[0] = "DEVID_AD";
-    regnames[1] = "DEVID_MST";
-    regnames[2] = "PARTID";
-    regnames[3] = "REVID";
-    regnames[4] = "XDATA";
-    regnames[5] = "YDATA";
-    regnames[6] = "ZDATA";
-    regnames[7] = "STATUS";
-    regnames[8] = "FIFO_ENTRIES_L";
-    regnames[9] = "FIFO_ENTRIES_H";
-    regnames[10] = "XDATA_L";
-    regnames[11] = "XDATA_H";
-    regnames[12] = "YDATA_L";
-    regnames[13] = "YDATA_H";
-    regnames[14] = "ZDATA_L";
-    regnames[15] = "ZDATA_H";
-    regnames[16] = "TEMP_L";
-    regnames[17] = "TEMP_H";
-    regnames[18] = "SOFT_RESET";
-    regnames[19] = "THRESH_ACT_L";
-    regnames[20] = "THRESH_ACT_H";
-    regnames[21] = "TIME_ACT";
-    regnames[22] = "THRESH_INACT_L";
-    regnames[23] = "THRESH_INACT_H";
-    regnames[24] = "TIME_INACT_L";
-    regnames[25] = "TIME_INACT_H";
-    regnames[26] = "ACT_INACT_CTL";
-    regnames[27] = "FIFO_CONTROL";
-    regnames[28] = "FIFO_SAMPLES";
-    regnames[29] = "INTMAP1";
-    regnames[30] = "INTMAP2";
-    regnames[31] = "FILTER_CTL";
-    regnames[32] = "POWER_CTL";
-    regnames[33] = "SELF_TEST";
+    mregnames[0] = "STATUS";
+    mregnames[1] = "OUT_P_MSB";
+    mregnames[2] = "OUT_P_CSB";
+    mregnames[3] = "OUT_P_LSB";
+    mregnames[4] = "OUT_T_MSB";
+    mregnames[5] = "OUT_T_LSB";
+    mregnames[6] = "DR_STATUS";
+    mregnames[7] = "OUT_P_DELTA_MSB";
+    mregnames[8] = "OUT_P_DELTA_CSB";
+    mregnames[9] = "OUT_T_DELTA_MSB";
+    mregnames[10] = "OUT_T_DELTA_LSB";
+    mregnames[11] = "WHO_AM_I";
+    mregnames[12] = "F_STATUS";
+    mregnames[13] = "F_DATA";
+    mregnames[14] = "F_SETUP";
+    mregnames[15] = "TIME_DLY";
+    mregnames[16] = "SYSMOD";
+    mregnames[17] = "INT_SOURCE";
+    mregnames[18] = "SOFT_RESET";
+    mregnames[19] = "PT_DATA_CFG";
+    mregnames[20] = "BAR_IN_MSB";
+    mregnames[21] = "BAR_IN_LSB";
+    mregnames[22] = "P_TGT_MSB";
+    mregnames[23] = "P_TGT_LSB";
+    mregnames[24] = "T_TGT";
+    mregnames[25] = "P_WND_MSB";
+    mregnames[26] = "P_WND_LSB";
+    mregnames[27] = "T_WND";
+    mregnames[28] = "P_MIN_MSB";
+    mregnames[29] = "P_MIN_CSB";
+    mregnames[30] = "P_MIN_LSB";
+    mregnames[31] = "T_MIN_MSB";
+    mregnames[32] = "T_MIN_LSB";
+    mregnames[33] = "P_MAX_MSB";
+    mregnames[34] = "P_MAX_CSB";
+    mregnames[35] = "P_MAX_LSB";
+    mregnames[36] = "T_MAX_MSB";
+    mregnames[37] = "T_MAX_LSB";
+    mregnames[38] = "CTRL_REG1";
+    mregnames[39] = "CTRL_REG2";
+    mregnames[40] = "CTRL_REG3";
+    mregnames[41] = "CTRL_REG4";
+    mregnames[42] = "CTRL_REG5";
+    mregnames[43] = "OFF_P";
+    mregnames[44] = "OFF_T";
+    mregnames[45] = "OFF_H";
 }
 
 // Interface pulled from ADXL362.cpp
@@ -158,6 +258,26 @@
     }
 }
 
+int mpl3115_reg_print(int s, int l){
+    if(s > 0x2D || s < 0x00){
+        printf("mpl: requires start between 0x00 and 0x20; given %d (0x%01x)\n\r", s,s);
+        return -1;
+    }else if(l < 0){
+        //check length > 0
+        printf("mpl: requires length >= 0, given %d\n\r", l);
+        return -1;
+    }else{
+        //else do stuff
+        if(WHOAMI IS NOT 0xC4){
+            //return error
+            printf("error: WHO_AM_I is not 0xC4; exiting\n\r");
+            return -1;
+        }else{
+            //else do stuff again
+        }
+    }
+}
+
 int main() {
     initmap();
     adxl362.reset();