CAC_smartcushion
(Working) Code to interface 3 LoadCells to ADISense1000 and display values using the Labview code.
Fork of
4Bridge_ADISense1000_Example_copy
by 
CAC_smartcushion
src/adi_sense_1000/ADISENSE1000_REGISTERS.h@0:76fed7dd9235, 2018-01-25 (annotated)
- Committer:
- seanwilson10
- Date:
- Thu Jan 25 16:00:23 2018 +0000
- Revision:
- 0:76fed7dd9235
initial;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| seanwilson10 | 0:76fed7dd9235 | 1 | /* ================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 2 | |
| seanwilson10 | 0:76fed7dd9235 | 3 | Created by : sherry |
| seanwilson10 | 0:76fed7dd9235 | 4 | Created on : 2017 Nov 14, 10:55 GMT |
| seanwilson10 | 0:76fed7dd9235 | 5 | |
| seanwilson10 | 0:76fed7dd9235 | 6 | Project : ADISENSE1000_REGISTERS |
| seanwilson10 | 0:76fed7dd9235 | 7 | File : ADISENSE1000_REGISTERS.h |
| seanwilson10 | 0:76fed7dd9235 | 8 | Description : Register Definitions |
| seanwilson10 | 0:76fed7dd9235 | 9 | |
| seanwilson10 | 0:76fed7dd9235 | 10 | !! ADI Confidential !! |
| seanwilson10 | 0:76fed7dd9235 | 11 | INTERNAL USE ONLY |
| seanwilson10 | 0:76fed7dd9235 | 12 | |
| seanwilson10 | 0:76fed7dd9235 | 13 | Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. |
| seanwilson10 | 0:76fed7dd9235 | 14 | This software is proprietary and confidential to Analog Devices, Inc. and |
| seanwilson10 | 0:76fed7dd9235 | 15 | its licensors. |
| seanwilson10 | 0:76fed7dd9235 | 16 | |
| seanwilson10 | 0:76fed7dd9235 | 17 | This file was auto-generated. Do not make local changes to this file. |
| seanwilson10 | 0:76fed7dd9235 | 18 | |
| seanwilson10 | 0:76fed7dd9235 | 19 | Auto generation script information: |
| seanwilson10 | 0:76fed7dd9235 | 20 | Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders |
| seanwilson10 | 0:76fed7dd9235 | 21 | Last modified: 26-SEP-2017 |
| seanwilson10 | 0:76fed7dd9235 | 22 | |
| seanwilson10 | 0:76fed7dd9235 | 23 | ================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 24 | |
| seanwilson10 | 0:76fed7dd9235 | 25 | #ifndef _DEF_ADISENSE1000_REGISTERS_H |
| seanwilson10 | 0:76fed7dd9235 | 26 | #define _DEF_ADISENSE1000_REGISTERS_H |
| seanwilson10 | 0:76fed7dd9235 | 27 | |
| seanwilson10 | 0:76fed7dd9235 | 28 | #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) |
| seanwilson10 | 0:76fed7dd9235 | 29 | #include <stdint.h> |
| seanwilson10 | 0:76fed7dd9235 | 30 | #endif /* _LANGUAGE_C */ |
| seanwilson10 | 0:76fed7dd9235 | 31 | |
| seanwilson10 | 0:76fed7dd9235 | 32 | #ifndef __ADI_GENERATED_DEF_HEADERS__ |
| seanwilson10 | 0:76fed7dd9235 | 33 | #define __ADI_GENERATED_DEF_HEADERS__ 1 |
| seanwilson10 | 0:76fed7dd9235 | 34 | #endif |
| seanwilson10 | 0:76fed7dd9235 | 35 | |
| seanwilson10 | 0:76fed7dd9235 | 36 | #define __ADI_HAS_ADISENSE_CORE__ 1 |
| seanwilson10 | 0:76fed7dd9235 | 37 | #define __ADI_HAS_ADISENSE_SPI__ 1 |
| seanwilson10 | 0:76fed7dd9235 | 38 | #define __ADI_HAS_ADISENSE_TEST__ 1 |
| seanwilson10 | 0:76fed7dd9235 | 39 | |
| seanwilson10 | 0:76fed7dd9235 | 40 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 41 | |
| seanwilson10 | 0:76fed7dd9235 | 42 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 43 | |
| seanwilson10 | 0:76fed7dd9235 | 44 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 45 | ADISENSE_SPI |
| seanwilson10 | 0:76fed7dd9235 | 46 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 47 | #define MOD_ADISENSE_SPI_BASE 0x00000000 /* */ |
| seanwilson10 | 0:76fed7dd9235 | 48 | #define MOD_ADISENSE_SPI_MASK 0x00007FFF /* */ |
| seanwilson10 | 0:76fed7dd9235 | 49 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */ |
| seanwilson10 | 0:76fed7dd9235 | 50 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_A 0x00000000 /* ADISENSE_SPI Interface Configuration A */ |
| seanwilson10 | 0:76fed7dd9235 | 51 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */ |
| seanwilson10 | 0:76fed7dd9235 | 52 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_B 0x00000001 /* ADISENSE_SPI Interface Configuration B */ |
| seanwilson10 | 0:76fed7dd9235 | 53 | #define REG_ADISENSE_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */ |
| seanwilson10 | 0:76fed7dd9235 | 54 | #define REG_ADISENSE_SPI_DEVICE_CONFIG 0x00000002 /* ADISENSE_SPI Device Configuration */ |
| seanwilson10 | 0:76fed7dd9235 | 55 | #define REG_ADISENSE_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */ |
| seanwilson10 | 0:76fed7dd9235 | 56 | #define REG_ADISENSE_SPI_CHIP_TYPE 0x00000003 /* ADISENSE_SPI Chip Type */ |
| seanwilson10 | 0:76fed7dd9235 | 57 | #define REG_ADISENSE_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */ |
| seanwilson10 | 0:76fed7dd9235 | 58 | #define REG_ADISENSE_SPI_PRODUCT_ID_L 0x00000004 /* ADISENSE_SPI Product ID Low */ |
| seanwilson10 | 0:76fed7dd9235 | 59 | #define REG_ADISENSE_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */ |
| seanwilson10 | 0:76fed7dd9235 | 60 | #define REG_ADISENSE_SPI_PRODUCT_ID_H 0x00000005 /* ADISENSE_SPI Product ID High */ |
| seanwilson10 | 0:76fed7dd9235 | 61 | #define REG_ADISENSE_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */ |
| seanwilson10 | 0:76fed7dd9235 | 62 | #define REG_ADISENSE_SPI_CHIP_GRADE 0x00000006 /* ADISENSE_SPI Chip Grade */ |
| seanwilson10 | 0:76fed7dd9235 | 63 | #define REG_ADISENSE_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */ |
| seanwilson10 | 0:76fed7dd9235 | 64 | #define REG_ADISENSE_SPI_SCRATCH_PAD 0x0000000A /* ADISENSE_SPI Scratch Pad */ |
| seanwilson10 | 0:76fed7dd9235 | 65 | #define REG_ADISENSE_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 66 | #define REG_ADISENSE_SPI_SPI_REVISION 0x0000000B /* ADISENSE_SPI SPI Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 67 | #define REG_ADISENSE_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */ |
| seanwilson10 | 0:76fed7dd9235 | 68 | #define REG_ADISENSE_SPI_VENDOR_L 0x0000000C /* ADISENSE_SPI Vendor ID Low */ |
| seanwilson10 | 0:76fed7dd9235 | 69 | #define REG_ADISENSE_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */ |
| seanwilson10 | 0:76fed7dd9235 | 70 | #define REG_ADISENSE_SPI_VENDOR_H 0x0000000D /* ADISENSE_SPI Vendor ID High */ |
| seanwilson10 | 0:76fed7dd9235 | 71 | #define REG_ADISENSE_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 72 | #define REG_ADISENSE_SPI_STREAM_MODE 0x0000000E /* ADISENSE_SPI Stream Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 73 | #define REG_ADISENSE_SPI_TRANSFER_CONFIG_RESET 0x00000000 /* Reset Value for Transfer_Config */ |
| seanwilson10 | 0:76fed7dd9235 | 74 | #define REG_ADISENSE_SPI_TRANSFER_CONFIG 0x0000000F /* ADISENSE_SPI Transfer Config */ |
| seanwilson10 | 0:76fed7dd9235 | 75 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_C_RESET 0x00000033 /* Reset Value for Interface_Config_C */ |
| seanwilson10 | 0:76fed7dd9235 | 76 | #define REG_ADISENSE_SPI_INTERFACE_CONFIG_C 0x00000010 /* ADISENSE_SPI Interface Configuration C */ |
| seanwilson10 | 0:76fed7dd9235 | 77 | #define REG_ADISENSE_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */ |
| seanwilson10 | 0:76fed7dd9235 | 78 | #define REG_ADISENSE_SPI_INTERFACE_STATUS_A 0x00000011 /* ADISENSE_SPI Interface Status A */ |
| seanwilson10 | 0:76fed7dd9235 | 79 | |
| seanwilson10 | 0:76fed7dd9235 | 80 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 81 | ADISENSE_SPI Register BitMasks, Positions & Enumerations |
| seanwilson10 | 0:76fed7dd9235 | 82 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 83 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 84 | ADISENSE_SPI_INTERFACE_CONFIG_A Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 85 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 86 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of SW_RESET Bits. */ |
| seanwilson10 | 0:76fed7dd9235 | 87 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */ |
| seanwilson10 | 0:76fed7dd9235 | 88 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* SDO Pin Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 89 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of SW_RESET Bits. */ |
| seanwilson10 | 0:76fed7dd9235 | 90 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of SW_RESET Bits. */ |
| seanwilson10 | 0:76fed7dd9235 | 91 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */ |
| seanwilson10 | 0:76fed7dd9235 | 92 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* SDO Pin Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 93 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of SW_RESET Bits. */ |
| seanwilson10 | 0:76fed7dd9235 | 94 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */ |
| seanwilson10 | 0:76fed7dd9235 | 95 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */ |
| seanwilson10 | 0:76fed7dd9235 | 96 | |
| seanwilson10 | 0:76fed7dd9235 | 97 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 98 | ADISENSE_SPI_INTERFACE_CONFIG_B Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 99 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 100 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 /* Select Streaming or Single Instruction Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 101 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 /* Select Streaming or Single Instruction Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 102 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_B_STREAMING_MODE 0x00000000 /* Single_Inst: Streaming mode is enabled */ |
| seanwilson10 | 0:76fed7dd9235 | 103 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */ |
| seanwilson10 | 0:76fed7dd9235 | 104 | |
| seanwilson10 | 0:76fed7dd9235 | 105 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 106 | ADISENSE_SPI_DEVICE_CONFIG Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 107 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 108 | #define BITP_ADISENSE_SPI_DEVICE_CONFIG_OPERATING_MODES 0 /* Power Modes */ |
| seanwilson10 | 0:76fed7dd9235 | 109 | #define BITM_ADISENSE_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 /* Power Modes */ |
| seanwilson10 | 0:76fed7dd9235 | 110 | #define ENUM_ADISENSE_SPI_DEVICE_CONFIG_NORMAL 0x00000000 /* Operating_Modes: Normal Operating Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 111 | #define ENUM_ADISENSE_SPI_DEVICE_CONFIG_SLEEP 0x00000003 /* Operating_Modes: Low Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 112 | |
| seanwilson10 | 0:76fed7dd9235 | 113 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 114 | ADISENSE_SPI_CHIP_TYPE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 115 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 116 | #define BITP_ADISENSE_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */ |
| seanwilson10 | 0:76fed7dd9235 | 117 | #define BITM_ADISENSE_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F /* Precision ADC */ |
| seanwilson10 | 0:76fed7dd9235 | 118 | |
| seanwilson10 | 0:76fed7dd9235 | 119 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 120 | ADISENSE_SPI_PRODUCT_ID_L Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 121 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 122 | #define BITP_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 123 | #define BITP_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 /* These Bits Vary on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 124 | #define BITM_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 125 | #define BITM_ADISENSE_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F /* These Bits Vary on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 126 | |
| seanwilson10 | 0:76fed7dd9235 | 127 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 128 | ADISENSE_SPI_PRODUCT_ID_H Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 129 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 130 | #define BITP_ADISENSE_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 131 | #define BITM_ADISENSE_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| seanwilson10 | 0:76fed7dd9235 | 132 | |
| seanwilson10 | 0:76fed7dd9235 | 133 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 134 | ADISENSE_SPI_CHIP_GRADE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 135 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 136 | #define BITP_ADISENSE_SPI_CHIP_GRADE_GRADE 4 /* This is the Device Performance Grade */ |
| seanwilson10 | 0:76fed7dd9235 | 137 | #define BITP_ADISENSE_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* This is the Device Hardware Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 138 | #define BITM_ADISENSE_SPI_CHIP_GRADE_GRADE 0x000000F0 /* This is the Device Performance Grade */ |
| seanwilson10 | 0:76fed7dd9235 | 139 | #define BITM_ADISENSE_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* This is the Device Hardware Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 140 | |
| seanwilson10 | 0:76fed7dd9235 | 141 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 142 | ADISENSE_SPI_SCRATCH_PAD Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 143 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 144 | #define BITP_ADISENSE_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 /* Software Scratchpad */ |
| seanwilson10 | 0:76fed7dd9235 | 145 | #define BITM_ADISENSE_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF /* Software Scratchpad */ |
| seanwilson10 | 0:76fed7dd9235 | 146 | |
| seanwilson10 | 0:76fed7dd9235 | 147 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 148 | ADISENSE_SPI_SPI_REVISION Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 149 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 150 | #define BITP_ADISENSE_SPI_SPI_REVISION_SPI_TYPE 6 /* Always Reads as 0x2 */ |
| seanwilson10 | 0:76fed7dd9235 | 151 | #define BITP_ADISENSE_SPI_SPI_REVISION_VERSION 0 /* SPI Version */ |
| seanwilson10 | 0:76fed7dd9235 | 152 | #define BITM_ADISENSE_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */ |
| seanwilson10 | 0:76fed7dd9235 | 153 | #define BITM_ADISENSE_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */ |
| seanwilson10 | 0:76fed7dd9235 | 154 | #define ENUM_ADISENSE_SPI_SPI_REVISION_ADI_SPI 0x00000000 |
| seanwilson10 | 0:76fed7dd9235 | 155 | #define ENUM_ADISENSE_SPI_SPI_REVISION_LPT_SPI 0x00000080 |
| seanwilson10 | 0:76fed7dd9235 | 156 | #define ENUM_ADISENSE_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */ |
| seanwilson10 | 0:76fed7dd9235 | 157 | |
| seanwilson10 | 0:76fed7dd9235 | 158 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 159 | ADISENSE_SPI_VENDOR_L Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 160 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 161 | #define BITP_ADISENSE_SPI_VENDOR_L_VID 0 /* Analog Devices Vendor ID */ |
| seanwilson10 | 0:76fed7dd9235 | 162 | #define BITM_ADISENSE_SPI_VENDOR_L_VID 0x000000FF /* Analog Devices Vendor ID */ |
| seanwilson10 | 0:76fed7dd9235 | 163 | |
| seanwilson10 | 0:76fed7dd9235 | 164 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 165 | ADISENSE_SPI_VENDOR_H Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 166 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 167 | #define BITP_ADISENSE_SPI_VENDOR_H_VID 0 /* Analog Devices Vendor ID */ |
| seanwilson10 | 0:76fed7dd9235 | 168 | #define BITM_ADISENSE_SPI_VENDOR_H_VID 0x000000FF /* Analog Devices Vendor ID */ |
| seanwilson10 | 0:76fed7dd9235 | 169 | |
| seanwilson10 | 0:76fed7dd9235 | 170 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 171 | ADISENSE_SPI_STREAM_MODE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 172 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 173 | #define BITP_ADISENSE_SPI_STREAM_MODE_LOOP_COUNT 0 /* Sets the Data Byte Count Before Looping to Start Address */ |
| seanwilson10 | 0:76fed7dd9235 | 174 | #define BITM_ADISENSE_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Sets the Data Byte Count Before Looping to Start Address */ |
| seanwilson10 | 0:76fed7dd9235 | 175 | |
| seanwilson10 | 0:76fed7dd9235 | 176 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 177 | ADISENSE_SPI_TRANSFER_CONFIG Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 178 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 179 | #define BITP_ADISENSE_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Controls Master-Slave Transfer */ |
| seanwilson10 | 0:76fed7dd9235 | 180 | #define BITM_ADISENSE_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Controls Master-Slave Transfer */ |
| seanwilson10 | 0:76fed7dd9235 | 181 | #define ENUM_ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */ |
| seanwilson10 | 0:76fed7dd9235 | 182 | #define ENUM_ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */ |
| seanwilson10 | 0:76fed7dd9235 | 183 | |
| seanwilson10 | 0:76fed7dd9235 | 184 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 185 | ADISENSE_SPI_INTERFACE_CONFIG_C Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 186 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 187 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 188 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multi-byte Registers Must Be Read/Written in Full */ |
| seanwilson10 | 0:76fed7dd9235 | 189 | #define BITP_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 190 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 191 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multi-byte Registers Must Be Read/Written in Full */ |
| seanwilson10 | 0:76fed7dd9235 | 192 | #define BITM_ADISENSE_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 193 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */ |
| seanwilson10 | 0:76fed7dd9235 | 194 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */ |
| seanwilson10 | 0:76fed7dd9235 | 195 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS 0x00000000 /* Strict_Register_Access: Normal mode, no access restrictions */ |
| seanwilson10 | 0:76fed7dd9235 | 196 | #define ENUM_ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS 0x00000020 /* Strict_Register_Access: Strict mode, multi-byte registers require all bytes read/written */ |
| seanwilson10 | 0:76fed7dd9235 | 197 | |
| seanwilson10 | 0:76fed7dd9235 | 198 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 199 | ADISENSE_SPI_INTERFACE_STATUS_A Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 200 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 201 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */ |
| seanwilson10 | 0:76fed7dd9235 | 202 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */ |
| seanwilson10 | 0:76fed7dd9235 | 203 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */ |
| seanwilson10 | 0:76fed7dd9235 | 204 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read-Only Register Attempted */ |
| seanwilson10 | 0:76fed7dd9235 | 205 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */ |
| seanwilson10 | 0:76fed7dd9235 | 206 | #define BITP_ADISENSE_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Non-existent Register Address */ |
| seanwilson10 | 0:76fed7dd9235 | 207 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */ |
| seanwilson10 | 0:76fed7dd9235 | 208 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */ |
| seanwilson10 | 0:76fed7dd9235 | 209 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */ |
| seanwilson10 | 0:76fed7dd9235 | 210 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read-Only Register Attempted */ |
| seanwilson10 | 0:76fed7dd9235 | 211 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */ |
| seanwilson10 | 0:76fed7dd9235 | 212 | #define BITM_ADISENSE_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Non-existent Register Address */ |
| seanwilson10 | 0:76fed7dd9235 | 213 | |
| seanwilson10 | 0:76fed7dd9235 | 214 | |
| seanwilson10 | 0:76fed7dd9235 | 215 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 216 | ADISENSE1000 Core Registers |
| seanwilson10 | 0:76fed7dd9235 | 217 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 218 | |
| seanwilson10 | 0:76fed7dd9235 | 219 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 220 | ADISENSE_CORE |
| seanwilson10 | 0:76fed7dd9235 | 221 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 222 | #define MOD_ADISENSE_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */ |
| seanwilson10 | 0:76fed7dd9235 | 223 | #define MOD_ADISENSE_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */ |
| seanwilson10 | 0:76fed7dd9235 | 224 | #define REG_ADISENSE_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */ |
| seanwilson10 | 0:76fed7dd9235 | 225 | #define REG_ADISENSE_CORE_COMMAND 0x00000014 /* ADISENSE_CORE Special Command */ |
| seanwilson10 | 0:76fed7dd9235 | 226 | #define REG_ADISENSE_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 227 | #define REG_ADISENSE_CORE_MODE 0x00000016 /* ADISENSE_CORE Operating Mode and DRDY Control */ |
| seanwilson10 | 0:76fed7dd9235 | 228 | #define REG_ADISENSE_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */ |
| seanwilson10 | 0:76fed7dd9235 | 229 | #define REG_ADISENSE_CORE_POWER_CONFIG 0x00000017 /* ADISENSE_CORE General Configuration */ |
| seanwilson10 | 0:76fed7dd9235 | 230 | #define REG_ADISENSE_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */ |
| seanwilson10 | 0:76fed7dd9235 | 231 | #define REG_ADISENSE_CORE_CYCLE_CONTROL 0x00000018 /* ADISENSE_CORE Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 232 | #define REG_ADISENSE_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */ |
| seanwilson10 | 0:76fed7dd9235 | 233 | #define REG_ADISENSE_CORE_FIFO_NUM_CYCLES 0x0000001A /* ADISENSE_CORE Number of Measurement Cycles to Store in FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 234 | #define REG_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_RESET 0x00000000 /* Reset Value for Multi_Cycle_Repeat_Interval */ |
| seanwilson10 | 0:76fed7dd9235 | 235 | #define REG_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL 0x0000001C /* ADISENSE_CORE Time Between Repeats of Multi-Cycle Conversions.... */ |
| seanwilson10 | 0:76fed7dd9235 | 236 | #define REG_ADISENSE_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */ |
| seanwilson10 | 0:76fed7dd9235 | 237 | #define REG_ADISENSE_CORE_STATUS 0x00000020 /* ADISENSE_CORE General Status */ |
| seanwilson10 | 0:76fed7dd9235 | 238 | #define REG_ADISENSE_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */ |
| seanwilson10 | 0:76fed7dd9235 | 239 | #define REG_ADISENSE_CORE_DIAGNOSTICS_STATUS 0x00000024 /* ADISENSE_CORE Diagnostics Status */ |
| seanwilson10 | 0:76fed7dd9235 | 240 | #define REG_ADISENSE_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */ |
| seanwilson10 | 0:76fed7dd9235 | 241 | #define REG_ADISENSE_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* ADISENSE_CORE Alert Status Summary */ |
| seanwilson10 | 0:76fed7dd9235 | 242 | #define REG_ADISENSE_CORE_ALERT_STATUS_2_RESET 0x00000000 /* Reset Value for Alert_Status_2 */ |
| seanwilson10 | 0:76fed7dd9235 | 243 | #define REG_ADISENSE_CORE_ALERT_STATUS_2 0x00000028 /* ADISENSE_CORE Additional Alert Status Information */ |
| seanwilson10 | 0:76fed7dd9235 | 244 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 245 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH0 */ |
| seanwilson10 | 0:76fed7dd9235 | 246 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH1 */ |
| seanwilson10 | 0:76fed7dd9235 | 247 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH2 */ |
| seanwilson10 | 0:76fed7dd9235 | 248 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH3 */ |
| seanwilson10 | 0:76fed7dd9235 | 249 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH4 */ |
| seanwilson10 | 0:76fed7dd9235 | 250 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH5 */ |
| seanwilson10 | 0:76fed7dd9235 | 251 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH6 */ |
| seanwilson10 | 0:76fed7dd9235 | 252 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH7 */ |
| seanwilson10 | 0:76fed7dd9235 | 253 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH8 */ |
| seanwilson10 | 0:76fed7dd9235 | 254 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH9 */ |
| seanwilson10 | 0:76fed7dd9235 | 255 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH10 */ |
| seanwilson10 | 0:76fed7dd9235 | 256 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH11 */ |
| seanwilson10 | 0:76fed7dd9235 | 257 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_DETAIL_CH12 */ |
| seanwilson10 | 0:76fed7dd9235 | 258 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH0 0x0000002A /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 259 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH1 0x0000002C /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 260 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH2 0x0000002E /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 261 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH3 0x00000030 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 262 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH4 0x00000032 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 263 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH5 0x00000034 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 264 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH6 0x00000036 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 265 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH7 0x00000038 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 266 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH8 0x0000003A /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 267 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH9 0x0000003C /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 268 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH10 0x0000003E /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 269 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH11 0x00000040 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 270 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CH12 0x00000042 /* ADISENSE_CORE Detailed Error Information */ |
| seanwilson10 | 0:76fed7dd9235 | 271 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn(i) (REG_ADISENSE_CORE_ALERT_DETAIL_CH0 + ((i) * 2)) |
| seanwilson10 | 0:76fed7dd9235 | 272 | #define REG_ADISENSE_CORE_ALERT_DETAIL_CHn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 273 | #define REG_ADISENSE_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */ |
| seanwilson10 | 0:76fed7dd9235 | 274 | #define REG_ADISENSE_CORE_ERROR_CODE 0x0000004C /* ADISENSE_CORE Code Indicating Source of Error */ |
| seanwilson10 | 0:76fed7dd9235 | 275 | #define REG_ADISENSE_CORE_ALERT_CODE_RESET 0x00000000 /* Reset Value for Alert_Code */ |
| seanwilson10 | 0:76fed7dd9235 | 276 | #define REG_ADISENSE_CORE_ALERT_CODE 0x0000004E /* ADISENSE_CORE Code Indicating Source of Alert */ |
| seanwilson10 | 0:76fed7dd9235 | 277 | #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */ |
| seanwilson10 | 0:76fed7dd9235 | 278 | #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE1 0x00000050 /* ADISENSE_CORE External Reference Information */ |
| seanwilson10 | 0:76fed7dd9235 | 279 | #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */ |
| seanwilson10 | 0:76fed7dd9235 | 280 | #define REG_ADISENSE_CORE_EXTERNAL_REFERENCE2 0x00000054 /* ADISENSE_CORE External Reference Information */ |
| seanwilson10 | 0:76fed7dd9235 | 281 | #define REG_ADISENSE_CORE_AVDD_VOLTAGE_RESET 0x40533333 /* Reset Value for AVDD_Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 282 | #define REG_ADISENSE_CORE_AVDD_VOLTAGE 0x00000058 /* ADISENSE_CORE AVDD Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 283 | #define REG_ADISENSE_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */ |
| seanwilson10 | 0:76fed7dd9235 | 284 | #define REG_ADISENSE_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* ADISENSE_CORE Diagnostic Control */ |
| seanwilson10 | 0:76fed7dd9235 | 285 | #define REG_ADISENSE_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 286 | #define REG_ADISENSE_CORE_DATA_FIFO 0x00000060 /* ADISENSE_CORE FIFO of Sensor Results */ |
| seanwilson10 | 0:76fed7dd9235 | 287 | #define REG_ADISENSE_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */ |
| seanwilson10 | 0:76fed7dd9235 | 288 | #define REG_ADISENSE_CORE_LUT_SELECT 0x00000070 /* ADISENSE_CORE Read/Write Strobe */ |
| seanwilson10 | 0:76fed7dd9235 | 289 | #define REG_ADISENSE_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */ |
| seanwilson10 | 0:76fed7dd9235 | 290 | #define REG_ADISENSE_CORE_LUT_OFFSET 0x00000072 /* ADISENSE_CORE Offset into Selected LUT */ |
| seanwilson10 | 0:76fed7dd9235 | 291 | #define REG_ADISENSE_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */ |
| seanwilson10 | 0:76fed7dd9235 | 292 | #define REG_ADISENSE_CORE_LUT_DATA 0x00000074 /* ADISENSE_CORE Data to Read/Write from Addressed LUT Entry */ |
| seanwilson10 | 0:76fed7dd9235 | 293 | #define REG_ADISENSE_CORE_CAL_OFFSET_RESET 0x00000000 /* Reset Value for CAL_Offset */ |
| seanwilson10 | 0:76fed7dd9235 | 294 | #define REG_ADISENSE_CORE_CAL_OFFSET 0x0000007A /* ADISENSE_CORE Offset into Selected Calibration Values */ |
| seanwilson10 | 0:76fed7dd9235 | 295 | #define REG_ADISENSE_CORE_CAL_DATA_RESET 0x00000000 /* Reset Value for CAL_Data */ |
| seanwilson10 | 0:76fed7dd9235 | 296 | #define REG_ADISENSE_CORE_CAL_DATA 0x0000007C /* ADISENSE_CORE Data to Read/Write from Addressed Calibration Values */ |
| seanwilson10 | 0:76fed7dd9235 | 297 | #define REG_ADISENSE_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 298 | #define REG_ADISENSE_CORE_REVISION 0x0000008C /* ADISENSE_CORE Hardware, Firmware Revision */ |
| seanwilson10 | 0:76fed7dd9235 | 299 | #define REG_ADISENSE_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 300 | #define REG_ADISENSE_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT0 */ |
| seanwilson10 | 0:76fed7dd9235 | 301 | #define REG_ADISENSE_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT1 */ |
| seanwilson10 | 0:76fed7dd9235 | 302 | #define REG_ADISENSE_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT2 */ |
| seanwilson10 | 0:76fed7dd9235 | 303 | #define REG_ADISENSE_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT3 */ |
| seanwilson10 | 0:76fed7dd9235 | 304 | #define REG_ADISENSE_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT4 */ |
| seanwilson10 | 0:76fed7dd9235 | 305 | #define REG_ADISENSE_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT5 */ |
| seanwilson10 | 0:76fed7dd9235 | 306 | #define REG_ADISENSE_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT6 */ |
| seanwilson10 | 0:76fed7dd9235 | 307 | #define REG_ADISENSE_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT7 */ |
| seanwilson10 | 0:76fed7dd9235 | 308 | #define REG_ADISENSE_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT8 */ |
| seanwilson10 | 0:76fed7dd9235 | 309 | #define REG_ADISENSE_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT9 */ |
| seanwilson10 | 0:76fed7dd9235 | 310 | #define REG_ADISENSE_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_COUNT10 */ |
| seanwilson10 | 0:76fed7dd9235 | 311 | #define REG_ADISENSE_CORE_CHANNEL_COUNT0 0x00000090 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 312 | #define REG_ADISENSE_CORE_CHANNEL_COUNT1 0x000000D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 313 | #define REG_ADISENSE_CORE_CHANNEL_COUNT2 0x00000110 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 314 | #define REG_ADISENSE_CORE_CHANNEL_COUNT3 0x00000150 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 315 | #define REG_ADISENSE_CORE_CHANNEL_COUNT4 0x00000190 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 316 | #define REG_ADISENSE_CORE_CHANNEL_COUNT5 0x000001D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 317 | #define REG_ADISENSE_CORE_CHANNEL_COUNT6 0x00000210 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 318 | #define REG_ADISENSE_CORE_CHANNEL_COUNT7 0x00000250 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 319 | #define REG_ADISENSE_CORE_CHANNEL_COUNT8 0x00000290 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 320 | #define REG_ADISENSE_CORE_CHANNEL_COUNT9 0x000002D0 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 321 | #define REG_ADISENSE_CORE_CHANNEL_COUNT10 0x00000310 /* ADISENSE_CORE Number of Channel Occurrences per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 322 | #define REG_ADISENSE_CORE_CHANNEL_COUNTn(i) (REG_ADISENSE_CORE_CHANNEL_COUNT0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 323 | #define REG_ADISENSE_CORE_CHANNEL_COUNTn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 324 | #define REG_ADISENSE_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 325 | #define REG_ADISENSE_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE0 */ |
| seanwilson10 | 0:76fed7dd9235 | 326 | #define REG_ADISENSE_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE1 */ |
| seanwilson10 | 0:76fed7dd9235 | 327 | #define REG_ADISENSE_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE2 */ |
| seanwilson10 | 0:76fed7dd9235 | 328 | #define REG_ADISENSE_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE3 */ |
| seanwilson10 | 0:76fed7dd9235 | 329 | #define REG_ADISENSE_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE4 */ |
| seanwilson10 | 0:76fed7dd9235 | 330 | #define REG_ADISENSE_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE5 */ |
| seanwilson10 | 0:76fed7dd9235 | 331 | #define REG_ADISENSE_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE6 */ |
| seanwilson10 | 0:76fed7dd9235 | 332 | #define REG_ADISENSE_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE7 */ |
| seanwilson10 | 0:76fed7dd9235 | 333 | #define REG_ADISENSE_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE8 */ |
| seanwilson10 | 0:76fed7dd9235 | 334 | #define REG_ADISENSE_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE9 */ |
| seanwilson10 | 0:76fed7dd9235 | 335 | #define REG_ADISENSE_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_TYPE10 */ |
| seanwilson10 | 0:76fed7dd9235 | 336 | #define REG_ADISENSE_CORE_SENSOR_TYPE0 0x00000092 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 337 | #define REG_ADISENSE_CORE_SENSOR_TYPE1 0x000000D2 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 338 | #define REG_ADISENSE_CORE_SENSOR_TYPE2 0x00000112 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 339 | #define REG_ADISENSE_CORE_SENSOR_TYPE3 0x00000152 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 340 | #define REG_ADISENSE_CORE_SENSOR_TYPE4 0x00000192 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 341 | #define REG_ADISENSE_CORE_SENSOR_TYPE5 0x000001D2 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 342 | #define REG_ADISENSE_CORE_SENSOR_TYPE6 0x00000212 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 343 | #define REG_ADISENSE_CORE_SENSOR_TYPE7 0x00000252 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 344 | #define REG_ADISENSE_CORE_SENSOR_TYPE8 0x00000292 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 345 | #define REG_ADISENSE_CORE_SENSOR_TYPE9 0x000002D2 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 346 | #define REG_ADISENSE_CORE_SENSOR_TYPE10 0x00000312 /* ADISENSE_CORE Sensor Select */ |
| seanwilson10 | 0:76fed7dd9235 | 347 | #define REG_ADISENSE_CORE_SENSOR_TYPEn(i) (REG_ADISENSE_CORE_SENSOR_TYPE0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 348 | #define REG_ADISENSE_CORE_SENSOR_TYPEn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 349 | #define REG_ADISENSE_CORE_SENSOR_DETAILSn_RESET 0x0000FFF0 /* Reset Value for Sensor_Details[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 350 | #define REG_ADISENSE_CORE_SENSOR_DETAILS0_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS0 */ |
| seanwilson10 | 0:76fed7dd9235 | 351 | #define REG_ADISENSE_CORE_SENSOR_DETAILS1_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS1 */ |
| seanwilson10 | 0:76fed7dd9235 | 352 | #define REG_ADISENSE_CORE_SENSOR_DETAILS2_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS2 */ |
| seanwilson10 | 0:76fed7dd9235 | 353 | #define REG_ADISENSE_CORE_SENSOR_DETAILS3_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS3 */ |
| seanwilson10 | 0:76fed7dd9235 | 354 | #define REG_ADISENSE_CORE_SENSOR_DETAILS4_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS4 */ |
| seanwilson10 | 0:76fed7dd9235 | 355 | #define REG_ADISENSE_CORE_SENSOR_DETAILS5_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS5 */ |
| seanwilson10 | 0:76fed7dd9235 | 356 | #define REG_ADISENSE_CORE_SENSOR_DETAILS6_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS6 */ |
| seanwilson10 | 0:76fed7dd9235 | 357 | #define REG_ADISENSE_CORE_SENSOR_DETAILS7_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS7 */ |
| seanwilson10 | 0:76fed7dd9235 | 358 | #define REG_ADISENSE_CORE_SENSOR_DETAILS8_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS8 */ |
| seanwilson10 | 0:76fed7dd9235 | 359 | #define REG_ADISENSE_CORE_SENSOR_DETAILS9_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS9 */ |
| seanwilson10 | 0:76fed7dd9235 | 360 | #define REG_ADISENSE_CORE_SENSOR_DETAILS10_RESET 0x0000FFF0 /* Reset Value for REG_ADISENSE_CORE_SENSOR_DETAILS10 */ |
| seanwilson10 | 0:76fed7dd9235 | 361 | #define REG_ADISENSE_CORE_SENSOR_DETAILS0 0x00000094 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 362 | #define REG_ADISENSE_CORE_SENSOR_DETAILS1 0x000000D4 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 363 | #define REG_ADISENSE_CORE_SENSOR_DETAILS2 0x00000114 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 364 | #define REG_ADISENSE_CORE_SENSOR_DETAILS3 0x00000154 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 365 | #define REG_ADISENSE_CORE_SENSOR_DETAILS4 0x00000194 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 366 | #define REG_ADISENSE_CORE_SENSOR_DETAILS5 0x000001D4 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 367 | #define REG_ADISENSE_CORE_SENSOR_DETAILS6 0x00000214 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 368 | #define REG_ADISENSE_CORE_SENSOR_DETAILS7 0x00000254 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 369 | #define REG_ADISENSE_CORE_SENSOR_DETAILS8 0x00000294 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 370 | #define REG_ADISENSE_CORE_SENSOR_DETAILS9 0x000002D4 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 371 | #define REG_ADISENSE_CORE_SENSOR_DETAILS10 0x00000314 /* ADISENSE_CORE Sensor Details */ |
| seanwilson10 | 0:76fed7dd9235 | 372 | #define REG_ADISENSE_CORE_SENSOR_DETAILSn(i) (REG_ADISENSE_CORE_SENSOR_DETAILS0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 373 | #define REG_ADISENSE_CORE_SENSOR_DETAILSn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 374 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 375 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION0 */ |
| seanwilson10 | 0:76fed7dd9235 | 376 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION1 */ |
| seanwilson10 | 0:76fed7dd9235 | 377 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION2 */ |
| seanwilson10 | 0:76fed7dd9235 | 378 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION3 */ |
| seanwilson10 | 0:76fed7dd9235 | 379 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION4 */ |
| seanwilson10 | 0:76fed7dd9235 | 380 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION5 */ |
| seanwilson10 | 0:76fed7dd9235 | 381 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION6 */ |
| seanwilson10 | 0:76fed7dd9235 | 382 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION7 */ |
| seanwilson10 | 0:76fed7dd9235 | 383 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION8 */ |
| seanwilson10 | 0:76fed7dd9235 | 384 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION9 */ |
| seanwilson10 | 0:76fed7dd9235 | 385 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_CHANNEL_EXCITATION10 */ |
| seanwilson10 | 0:76fed7dd9235 | 386 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION0 0x00000098 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 387 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION1 0x000000D8 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 388 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION2 0x00000118 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 389 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION3 0x00000158 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 390 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION4 0x00000198 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 391 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION5 0x000001D8 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 392 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION6 0x00000218 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 393 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION7 0x00000258 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 394 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION8 0x00000298 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 395 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION9 0x000002D8 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 396 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATION10 0x00000318 /* ADISENSE_CORE Excitation Current */ |
| seanwilson10 | 0:76fed7dd9235 | 397 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn(i) (REG_ADISENSE_CORE_CHANNEL_EXCITATION0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 398 | #define REG_ADISENSE_CORE_CHANNEL_EXCITATIONn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 399 | #define REG_ADISENSE_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 400 | #define REG_ADISENSE_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME0 */ |
| seanwilson10 | 0:76fed7dd9235 | 401 | #define REG_ADISENSE_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME1 */ |
| seanwilson10 | 0:76fed7dd9235 | 402 | #define REG_ADISENSE_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME2 */ |
| seanwilson10 | 0:76fed7dd9235 | 403 | #define REG_ADISENSE_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME3 */ |
| seanwilson10 | 0:76fed7dd9235 | 404 | #define REG_ADISENSE_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME4 */ |
| seanwilson10 | 0:76fed7dd9235 | 405 | #define REG_ADISENSE_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME5 */ |
| seanwilson10 | 0:76fed7dd9235 | 406 | #define REG_ADISENSE_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME6 */ |
| seanwilson10 | 0:76fed7dd9235 | 407 | #define REG_ADISENSE_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME7 */ |
| seanwilson10 | 0:76fed7dd9235 | 408 | #define REG_ADISENSE_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME8 */ |
| seanwilson10 | 0:76fed7dd9235 | 409 | #define REG_ADISENSE_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME9 */ |
| seanwilson10 | 0:76fed7dd9235 | 410 | #define REG_ADISENSE_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SETTLING_TIME10 */ |
| seanwilson10 | 0:76fed7dd9235 | 411 | #define REG_ADISENSE_CORE_SETTLING_TIME0 0x0000009A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 412 | #define REG_ADISENSE_CORE_SETTLING_TIME1 0x000000DA /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 413 | #define REG_ADISENSE_CORE_SETTLING_TIME2 0x0000011A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 414 | #define REG_ADISENSE_CORE_SETTLING_TIME3 0x0000015A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 415 | #define REG_ADISENSE_CORE_SETTLING_TIME4 0x0000019A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 416 | #define REG_ADISENSE_CORE_SETTLING_TIME5 0x000001DA /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 417 | #define REG_ADISENSE_CORE_SETTLING_TIME6 0x0000021A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 418 | #define REG_ADISENSE_CORE_SETTLING_TIME7 0x0000025A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 419 | #define REG_ADISENSE_CORE_SETTLING_TIME8 0x0000029A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 420 | #define REG_ADISENSE_CORE_SETTLING_TIME9 0x000002DA /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 421 | #define REG_ADISENSE_CORE_SETTLING_TIME10 0x0000031A /* ADISENSE_CORE Settling Time */ |
| seanwilson10 | 0:76fed7dd9235 | 422 | #define REG_ADISENSE_CORE_SETTLING_TIMEn(i) (REG_ADISENSE_CORE_SETTLING_TIME0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 423 | #define REG_ADISENSE_CORE_SETTLING_TIMEn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 424 | #define REG_ADISENSE_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 425 | #define REG_ADISENSE_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT0 */ |
| seanwilson10 | 0:76fed7dd9235 | 426 | #define REG_ADISENSE_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT1 */ |
| seanwilson10 | 0:76fed7dd9235 | 427 | #define REG_ADISENSE_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT2 */ |
| seanwilson10 | 0:76fed7dd9235 | 428 | #define REG_ADISENSE_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT3 */ |
| seanwilson10 | 0:76fed7dd9235 | 429 | #define REG_ADISENSE_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT4 */ |
| seanwilson10 | 0:76fed7dd9235 | 430 | #define REG_ADISENSE_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT5 */ |
| seanwilson10 | 0:76fed7dd9235 | 431 | #define REG_ADISENSE_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT6 */ |
| seanwilson10 | 0:76fed7dd9235 | 432 | #define REG_ADISENSE_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT7 */ |
| seanwilson10 | 0:76fed7dd9235 | 433 | #define REG_ADISENSE_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT8 */ |
| seanwilson10 | 0:76fed7dd9235 | 434 | #define REG_ADISENSE_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT9 */ |
| seanwilson10 | 0:76fed7dd9235 | 435 | #define REG_ADISENSE_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_FILTER_SELECT10 */ |
| seanwilson10 | 0:76fed7dd9235 | 436 | #define REG_ADISENSE_CORE_FILTER_SELECT0 0x0000009C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 437 | #define REG_ADISENSE_CORE_FILTER_SELECT1 0x000000DC /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 438 | #define REG_ADISENSE_CORE_FILTER_SELECT2 0x0000011C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 439 | #define REG_ADISENSE_CORE_FILTER_SELECT3 0x0000015C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 440 | #define REG_ADISENSE_CORE_FILTER_SELECT4 0x0000019C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 441 | #define REG_ADISENSE_CORE_FILTER_SELECT5 0x000001DC /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 442 | #define REG_ADISENSE_CORE_FILTER_SELECT6 0x0000021C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 443 | #define REG_ADISENSE_CORE_FILTER_SELECT7 0x0000025C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 444 | #define REG_ADISENSE_CORE_FILTER_SELECT8 0x0000029C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 445 | #define REG_ADISENSE_CORE_FILTER_SELECT9 0x000002DC /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 446 | #define REG_ADISENSE_CORE_FILTER_SELECT10 0x0000031C /* ADISENSE_CORE ADC Digital Filter Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 447 | #define REG_ADISENSE_CORE_FILTER_SELECTn(i) (REG_ADISENSE_CORE_FILTER_SELECT0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 448 | #define REG_ADISENSE_CORE_FILTER_SELECTn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 449 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 450 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 */ |
| seanwilson10 | 0:76fed7dd9235 | 451 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1 */ |
| seanwilson10 | 0:76fed7dd9235 | 452 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2 */ |
| seanwilson10 | 0:76fed7dd9235 | 453 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3 */ |
| seanwilson10 | 0:76fed7dd9235 | 454 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4 */ |
| seanwilson10 | 0:76fed7dd9235 | 455 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5 */ |
| seanwilson10 | 0:76fed7dd9235 | 456 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6 */ |
| seanwilson10 | 0:76fed7dd9235 | 457 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7 */ |
| seanwilson10 | 0:76fed7dd9235 | 458 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8 */ |
| seanwilson10 | 0:76fed7dd9235 | 459 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9 */ |
| seanwilson10 | 0:76fed7dd9235 | 460 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10 */ |
| seanwilson10 | 0:76fed7dd9235 | 461 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11 */ |
| seanwilson10 | 0:76fed7dd9235 | 462 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12 */ |
| seanwilson10 | 0:76fed7dd9235 | 463 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 464 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 465 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 466 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT3 0x00000160 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 467 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 468 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 469 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT6 0x00000220 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 470 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT7 0x00000260 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 471 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 472 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 473 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT10 0x00000320 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 474 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT11 0x00000360 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 475 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* ADISENSE_CORE High Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 476 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 477 | #define REG_ADISENSE_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 478 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 479 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 */ |
| seanwilson10 | 0:76fed7dd9235 | 480 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1 */ |
| seanwilson10 | 0:76fed7dd9235 | 481 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2 */ |
| seanwilson10 | 0:76fed7dd9235 | 482 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3 */ |
| seanwilson10 | 0:76fed7dd9235 | 483 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4 */ |
| seanwilson10 | 0:76fed7dd9235 | 484 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5 */ |
| seanwilson10 | 0:76fed7dd9235 | 485 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6 */ |
| seanwilson10 | 0:76fed7dd9235 | 486 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7 */ |
| seanwilson10 | 0:76fed7dd9235 | 487 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8 */ |
| seanwilson10 | 0:76fed7dd9235 | 488 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9 */ |
| seanwilson10 | 0:76fed7dd9235 | 489 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10 */ |
| seanwilson10 | 0:76fed7dd9235 | 490 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11 */ |
| seanwilson10 | 0:76fed7dd9235 | 491 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12 */ |
| seanwilson10 | 0:76fed7dd9235 | 492 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 493 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 494 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 495 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT3 0x00000164 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 496 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT4 0x000001A4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 497 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT5 0x000001E4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 498 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT6 0x00000224 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 499 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT7 0x00000264 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 500 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT8 0x000002A4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 501 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT9 0x000002E4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 502 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT10 0x00000324 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 503 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT11 0x00000364 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 504 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT12 0x000003A4 /* ADISENSE_CORE Low Threshold */ |
| seanwilson10 | 0:76fed7dd9235 | 505 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn(i) (REG_ADISENSE_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 506 | #define REG_ADISENSE_CORE_LOW_THRESHOLD_LIMITn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 507 | #define REG_ADISENSE_CORE_SENSOR_OFFSETn_RESET 0x00000000 /* Reset Value for Sensor_Offset[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 508 | #define REG_ADISENSE_CORE_SENSOR_OFFSET0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET0 */ |
| seanwilson10 | 0:76fed7dd9235 | 509 | #define REG_ADISENSE_CORE_SENSOR_OFFSET1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET1 */ |
| seanwilson10 | 0:76fed7dd9235 | 510 | #define REG_ADISENSE_CORE_SENSOR_OFFSET2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET2 */ |
| seanwilson10 | 0:76fed7dd9235 | 511 | #define REG_ADISENSE_CORE_SENSOR_OFFSET3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET3 */ |
| seanwilson10 | 0:76fed7dd9235 | 512 | #define REG_ADISENSE_CORE_SENSOR_OFFSET4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET4 */ |
| seanwilson10 | 0:76fed7dd9235 | 513 | #define REG_ADISENSE_CORE_SENSOR_OFFSET5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET5 */ |
| seanwilson10 | 0:76fed7dd9235 | 514 | #define REG_ADISENSE_CORE_SENSOR_OFFSET6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET6 */ |
| seanwilson10 | 0:76fed7dd9235 | 515 | #define REG_ADISENSE_CORE_SENSOR_OFFSET7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET7 */ |
| seanwilson10 | 0:76fed7dd9235 | 516 | #define REG_ADISENSE_CORE_SENSOR_OFFSET8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET8 */ |
| seanwilson10 | 0:76fed7dd9235 | 517 | #define REG_ADISENSE_CORE_SENSOR_OFFSET9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET9 */ |
| seanwilson10 | 0:76fed7dd9235 | 518 | #define REG_ADISENSE_CORE_SENSOR_OFFSET10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET10 */ |
| seanwilson10 | 0:76fed7dd9235 | 519 | #define REG_ADISENSE_CORE_SENSOR_OFFSET11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET11 */ |
| seanwilson10 | 0:76fed7dd9235 | 520 | #define REG_ADISENSE_CORE_SENSOR_OFFSET12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_OFFSET12 */ |
| seanwilson10 | 0:76fed7dd9235 | 521 | #define REG_ADISENSE_CORE_SENSOR_OFFSET0 0x000000A8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 522 | #define REG_ADISENSE_CORE_SENSOR_OFFSET1 0x000000E8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 523 | #define REG_ADISENSE_CORE_SENSOR_OFFSET2 0x00000128 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 524 | #define REG_ADISENSE_CORE_SENSOR_OFFSET3 0x00000168 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 525 | #define REG_ADISENSE_CORE_SENSOR_OFFSET4 0x000001A8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 526 | #define REG_ADISENSE_CORE_SENSOR_OFFSET5 0x000001E8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 527 | #define REG_ADISENSE_CORE_SENSOR_OFFSET6 0x00000228 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 528 | #define REG_ADISENSE_CORE_SENSOR_OFFSET7 0x00000268 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 529 | #define REG_ADISENSE_CORE_SENSOR_OFFSET8 0x000002A8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 530 | #define REG_ADISENSE_CORE_SENSOR_OFFSET9 0x000002E8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 531 | #define REG_ADISENSE_CORE_SENSOR_OFFSET10 0x00000328 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 532 | #define REG_ADISENSE_CORE_SENSOR_OFFSET11 0x00000368 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 533 | #define REG_ADISENSE_CORE_SENSOR_OFFSET12 0x000003A8 /* ADISENSE_CORE Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 534 | #define REG_ADISENSE_CORE_SENSOR_OFFSETn(i) (REG_ADISENSE_CORE_SENSOR_OFFSET0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 535 | #define REG_ADISENSE_CORE_SENSOR_OFFSETn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 536 | #define REG_ADISENSE_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 537 | #define REG_ADISENSE_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN0 */ |
| seanwilson10 | 0:76fed7dd9235 | 538 | #define REG_ADISENSE_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN1 */ |
| seanwilson10 | 0:76fed7dd9235 | 539 | #define REG_ADISENSE_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN2 */ |
| seanwilson10 | 0:76fed7dd9235 | 540 | #define REG_ADISENSE_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN3 */ |
| seanwilson10 | 0:76fed7dd9235 | 541 | #define REG_ADISENSE_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN4 */ |
| seanwilson10 | 0:76fed7dd9235 | 542 | #define REG_ADISENSE_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN5 */ |
| seanwilson10 | 0:76fed7dd9235 | 543 | #define REG_ADISENSE_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN6 */ |
| seanwilson10 | 0:76fed7dd9235 | 544 | #define REG_ADISENSE_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN7 */ |
| seanwilson10 | 0:76fed7dd9235 | 545 | #define REG_ADISENSE_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN8 */ |
| seanwilson10 | 0:76fed7dd9235 | 546 | #define REG_ADISENSE_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN9 */ |
| seanwilson10 | 0:76fed7dd9235 | 547 | #define REG_ADISENSE_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN10 */ |
| seanwilson10 | 0:76fed7dd9235 | 548 | #define REG_ADISENSE_CORE_SENSOR_GAIN11_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN11 */ |
| seanwilson10 | 0:76fed7dd9235 | 549 | #define REG_ADISENSE_CORE_SENSOR_GAIN12_RESET 0x3F800000 /* Reset Value for REG_ADISENSE_CORE_SENSOR_GAIN12 */ |
| seanwilson10 | 0:76fed7dd9235 | 550 | #define REG_ADISENSE_CORE_SENSOR_GAIN0 0x000000AC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 551 | #define REG_ADISENSE_CORE_SENSOR_GAIN1 0x000000EC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 552 | #define REG_ADISENSE_CORE_SENSOR_GAIN2 0x0000012C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 553 | #define REG_ADISENSE_CORE_SENSOR_GAIN3 0x0000016C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 554 | #define REG_ADISENSE_CORE_SENSOR_GAIN4 0x000001AC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 555 | #define REG_ADISENSE_CORE_SENSOR_GAIN5 0x000001EC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 556 | #define REG_ADISENSE_CORE_SENSOR_GAIN6 0x0000022C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 557 | #define REG_ADISENSE_CORE_SENSOR_GAIN7 0x0000026C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 558 | #define REG_ADISENSE_CORE_SENSOR_GAIN8 0x000002AC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 559 | #define REG_ADISENSE_CORE_SENSOR_GAIN9 0x000002EC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 560 | #define REG_ADISENSE_CORE_SENSOR_GAIN10 0x0000032C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 561 | #define REG_ADISENSE_CORE_SENSOR_GAIN11 0x0000036C /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 562 | #define REG_ADISENSE_CORE_SENSOR_GAIN12 0x000003AC /* ADISENSE_CORE Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 563 | #define REG_ADISENSE_CORE_SENSOR_GAINn(i) (REG_ADISENSE_CORE_SENSOR_GAIN0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 564 | #define REG_ADISENSE_CORE_SENSOR_GAINn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 565 | #define REG_ADISENSE_CORE_ALERT_CODE_CHn_RESET 0x00000000 /* Reset Value for Alert_Code_Ch[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 566 | #define REG_ADISENSE_CORE_ALERT_CODE_CH0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH0 */ |
| seanwilson10 | 0:76fed7dd9235 | 567 | #define REG_ADISENSE_CORE_ALERT_CODE_CH1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH1 */ |
| seanwilson10 | 0:76fed7dd9235 | 568 | #define REG_ADISENSE_CORE_ALERT_CODE_CH2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH2 */ |
| seanwilson10 | 0:76fed7dd9235 | 569 | #define REG_ADISENSE_CORE_ALERT_CODE_CH3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH3 */ |
| seanwilson10 | 0:76fed7dd9235 | 570 | #define REG_ADISENSE_CORE_ALERT_CODE_CH4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH4 */ |
| seanwilson10 | 0:76fed7dd9235 | 571 | #define REG_ADISENSE_CORE_ALERT_CODE_CH5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH5 */ |
| seanwilson10 | 0:76fed7dd9235 | 572 | #define REG_ADISENSE_CORE_ALERT_CODE_CH6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH6 */ |
| seanwilson10 | 0:76fed7dd9235 | 573 | #define REG_ADISENSE_CORE_ALERT_CODE_CH7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH7 */ |
| seanwilson10 | 0:76fed7dd9235 | 574 | #define REG_ADISENSE_CORE_ALERT_CODE_CH8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH8 */ |
| seanwilson10 | 0:76fed7dd9235 | 575 | #define REG_ADISENSE_CORE_ALERT_CODE_CH9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH9 */ |
| seanwilson10 | 0:76fed7dd9235 | 576 | #define REG_ADISENSE_CORE_ALERT_CODE_CH10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH10 */ |
| seanwilson10 | 0:76fed7dd9235 | 577 | #define REG_ADISENSE_CORE_ALERT_CODE_CH11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH11 */ |
| seanwilson10 | 0:76fed7dd9235 | 578 | #define REG_ADISENSE_CORE_ALERT_CODE_CH12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_ALERT_CODE_CH12 */ |
| seanwilson10 | 0:76fed7dd9235 | 579 | #define REG_ADISENSE_CORE_ALERT_CODE_CH0 0x000000B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 580 | #define REG_ADISENSE_CORE_ALERT_CODE_CH1 0x000000F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 581 | #define REG_ADISENSE_CORE_ALERT_CODE_CH2 0x00000130 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 582 | #define REG_ADISENSE_CORE_ALERT_CODE_CH3 0x00000170 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 583 | #define REG_ADISENSE_CORE_ALERT_CODE_CH4 0x000001B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 584 | #define REG_ADISENSE_CORE_ALERT_CODE_CH5 0x000001F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 585 | #define REG_ADISENSE_CORE_ALERT_CODE_CH6 0x00000230 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 586 | #define REG_ADISENSE_CORE_ALERT_CODE_CH7 0x00000270 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 587 | #define REG_ADISENSE_CORE_ALERT_CODE_CH8 0x000002B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 588 | #define REG_ADISENSE_CORE_ALERT_CODE_CH9 0x000002F0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 589 | #define REG_ADISENSE_CORE_ALERT_CODE_CH10 0x00000330 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 590 | #define REG_ADISENSE_CORE_ALERT_CODE_CH11 0x00000370 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 591 | #define REG_ADISENSE_CORE_ALERT_CODE_CH12 0x000003B0 /* ADISENSE_CORE Per-Channel Detailed Alert-Code Information */ |
| seanwilson10 | 0:76fed7dd9235 | 592 | #define REG_ADISENSE_CORE_ALERT_CODE_CHn(i) (REG_ADISENSE_CORE_ALERT_CODE_CH0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 593 | #define REG_ADISENSE_CORE_ALERT_CODE_CHn_COUNT 13 |
| seanwilson10 | 0:76fed7dd9235 | 594 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 595 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 */ |
| seanwilson10 | 0:76fed7dd9235 | 596 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1 */ |
| seanwilson10 | 0:76fed7dd9235 | 597 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2 */ |
| seanwilson10 | 0:76fed7dd9235 | 598 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3 */ |
| seanwilson10 | 0:76fed7dd9235 | 599 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4 */ |
| seanwilson10 | 0:76fed7dd9235 | 600 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5 */ |
| seanwilson10 | 0:76fed7dd9235 | 601 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6 */ |
| seanwilson10 | 0:76fed7dd9235 | 602 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7 */ |
| seanwilson10 | 0:76fed7dd9235 | 603 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8 */ |
| seanwilson10 | 0:76fed7dd9235 | 604 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9 */ |
| seanwilson10 | 0:76fed7dd9235 | 605 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10 */ |
| seanwilson10 | 0:76fed7dd9235 | 606 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 0x000000B8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 607 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG1 0x000000F8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 608 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG2 0x00000138 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 609 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG3 0x00000178 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 610 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG4 0x000001B8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 611 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG5 0x000001F8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 612 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG6 0x00000238 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 613 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG7 0x00000278 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 614 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG8 0x000002B8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 615 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG9 0x000002F8 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 616 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG10 0x00000338 /* ADISENSE_CORE Digital Sensor Data Coding */ |
| seanwilson10 | 0:76fed7dd9235 | 617 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 618 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_CONFIGn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 619 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 620 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 */ |
| seanwilson10 | 0:76fed7dd9235 | 621 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1 */ |
| seanwilson10 | 0:76fed7dd9235 | 622 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2 */ |
| seanwilson10 | 0:76fed7dd9235 | 623 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3 */ |
| seanwilson10 | 0:76fed7dd9235 | 624 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4 */ |
| seanwilson10 | 0:76fed7dd9235 | 625 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5 */ |
| seanwilson10 | 0:76fed7dd9235 | 626 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6 */ |
| seanwilson10 | 0:76fed7dd9235 | 627 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7 */ |
| seanwilson10 | 0:76fed7dd9235 | 628 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8 */ |
| seanwilson10 | 0:76fed7dd9235 | 629 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9 */ |
| seanwilson10 | 0:76fed7dd9235 | 630 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10 */ |
| seanwilson10 | 0:76fed7dd9235 | 631 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000BA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 632 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000FA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 633 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000013A /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 634 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000017A /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 635 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001BA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 636 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001FA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 637 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000023A /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 638 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000027A /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 639 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002BA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 640 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002FA /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 641 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000033A /* ADISENSE_CORE Sensor Address */ |
| seanwilson10 | 0:76fed7dd9235 | 642 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 643 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 644 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Num_Cmds[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 645 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 */ |
| seanwilson10 | 0:76fed7dd9235 | 646 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1 */ |
| seanwilson10 | 0:76fed7dd9235 | 647 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2 */ |
| seanwilson10 | 0:76fed7dd9235 | 648 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3 */ |
| seanwilson10 | 0:76fed7dd9235 | 649 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4 */ |
| seanwilson10 | 0:76fed7dd9235 | 650 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5 */ |
| seanwilson10 | 0:76fed7dd9235 | 651 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6 */ |
| seanwilson10 | 0:76fed7dd9235 | 652 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7 */ |
| seanwilson10 | 0:76fed7dd9235 | 653 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8 */ |
| seanwilson10 | 0:76fed7dd9235 | 654 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9 */ |
| seanwilson10 | 0:76fed7dd9235 | 655 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10 */ |
| seanwilson10 | 0:76fed7dd9235 | 656 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 0x000000BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 657 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS1 0x000000FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 658 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS2 0x0000013B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 659 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS3 0x0000017B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 660 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS4 0x000001BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 661 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS5 0x000001FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 662 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS6 0x0000023B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 663 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS7 0x0000027B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 664 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS8 0x000002BB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 665 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS9 0x000002FB /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 666 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS10 0x0000033B /* ADISENSE_CORE Number of Configuration, Read Commands for Digital Sensors */ |
| seanwilson10 | 0:76fed7dd9235 | 667 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS0 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 668 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDSn_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 669 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 670 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 */ |
| seanwilson10 | 0:76fed7dd9235 | 671 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11 */ |
| seanwilson10 | 0:76fed7dd9235 | 672 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12 */ |
| seanwilson10 | 0:76fed7dd9235 | 673 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13 */ |
| seanwilson10 | 0:76fed7dd9235 | 674 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14 */ |
| seanwilson10 | 0:76fed7dd9235 | 675 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15 */ |
| seanwilson10 | 0:76fed7dd9235 | 676 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16 */ |
| seanwilson10 | 0:76fed7dd9235 | 677 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17 */ |
| seanwilson10 | 0:76fed7dd9235 | 678 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18 */ |
| seanwilson10 | 0:76fed7dd9235 | 679 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19 */ |
| seanwilson10 | 0:76fed7dd9235 | 680 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110 */ |
| seanwilson10 | 0:76fed7dd9235 | 681 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 0x000000C0 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 682 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND11 0x00000100 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 683 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND12 0x00000140 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 684 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND13 0x00000180 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 685 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND14 0x000001C0 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 686 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND15 0x00000200 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 687 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND16 0x00000240 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 688 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND17 0x00000280 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 689 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND18 0x000002C0 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 690 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND19 0x00000300 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 691 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND110 0x00000340 /* ADISENSE_CORE Sensor Configuration Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 692 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 693 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 694 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 695 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 */ |
| seanwilson10 | 0:76fed7dd9235 | 696 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21 */ |
| seanwilson10 | 0:76fed7dd9235 | 697 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22 */ |
| seanwilson10 | 0:76fed7dd9235 | 698 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23 */ |
| seanwilson10 | 0:76fed7dd9235 | 699 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24 */ |
| seanwilson10 | 0:76fed7dd9235 | 700 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25 */ |
| seanwilson10 | 0:76fed7dd9235 | 701 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26 */ |
| seanwilson10 | 0:76fed7dd9235 | 702 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27 */ |
| seanwilson10 | 0:76fed7dd9235 | 703 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28 */ |
| seanwilson10 | 0:76fed7dd9235 | 704 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29 */ |
| seanwilson10 | 0:76fed7dd9235 | 705 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210 */ |
| seanwilson10 | 0:76fed7dd9235 | 706 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 0x000000C1 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 707 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND21 0x00000101 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 708 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND22 0x00000141 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 709 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND23 0x00000181 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 710 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND24 0x000001C1 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 711 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND25 0x00000201 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 712 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND26 0x00000241 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 713 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND27 0x00000281 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 714 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND28 0x000002C1 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 715 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND29 0x00000301 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 716 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND210 0x00000341 /* ADISENSE_CORE Sensor Configuration Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 717 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 718 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 719 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 720 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 */ |
| seanwilson10 | 0:76fed7dd9235 | 721 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31 */ |
| seanwilson10 | 0:76fed7dd9235 | 722 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32 */ |
| seanwilson10 | 0:76fed7dd9235 | 723 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33 */ |
| seanwilson10 | 0:76fed7dd9235 | 724 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34 */ |
| seanwilson10 | 0:76fed7dd9235 | 725 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35 */ |
| seanwilson10 | 0:76fed7dd9235 | 726 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36 */ |
| seanwilson10 | 0:76fed7dd9235 | 727 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37 */ |
| seanwilson10 | 0:76fed7dd9235 | 728 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38 */ |
| seanwilson10 | 0:76fed7dd9235 | 729 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39 */ |
| seanwilson10 | 0:76fed7dd9235 | 730 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310 */ |
| seanwilson10 | 0:76fed7dd9235 | 731 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 0x000000C2 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 732 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND31 0x00000102 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 733 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND32 0x00000142 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 734 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND33 0x00000182 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 735 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND34 0x000001C2 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 736 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND35 0x00000202 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 737 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND36 0x00000242 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 738 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND37 0x00000282 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 739 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND38 0x000002C2 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 740 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND39 0x00000302 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 741 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND310 0x00000342 /* ADISENSE_CORE Sensor Configuration Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 742 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 743 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 744 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command4[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 745 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 */ |
| seanwilson10 | 0:76fed7dd9235 | 746 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41 */ |
| seanwilson10 | 0:76fed7dd9235 | 747 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42 */ |
| seanwilson10 | 0:76fed7dd9235 | 748 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43 */ |
| seanwilson10 | 0:76fed7dd9235 | 749 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44 */ |
| seanwilson10 | 0:76fed7dd9235 | 750 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45 */ |
| seanwilson10 | 0:76fed7dd9235 | 751 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46 */ |
| seanwilson10 | 0:76fed7dd9235 | 752 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47 */ |
| seanwilson10 | 0:76fed7dd9235 | 753 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48 */ |
| seanwilson10 | 0:76fed7dd9235 | 754 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49 */ |
| seanwilson10 | 0:76fed7dd9235 | 755 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410 */ |
| seanwilson10 | 0:76fed7dd9235 | 756 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 0x000000C3 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 757 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND41 0x00000103 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 758 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND42 0x00000143 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 759 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND43 0x00000183 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 760 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND44 0x000001C3 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 761 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND45 0x00000203 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 762 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND46 0x00000243 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 763 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND47 0x00000283 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 764 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND48 0x000002C3 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 765 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND49 0x00000303 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 766 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND410 0x00000343 /* ADISENSE_CORE Sensor Configuration Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 767 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND40 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 768 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 769 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command5[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 770 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 */ |
| seanwilson10 | 0:76fed7dd9235 | 771 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51 */ |
| seanwilson10 | 0:76fed7dd9235 | 772 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52 */ |
| seanwilson10 | 0:76fed7dd9235 | 773 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53 */ |
| seanwilson10 | 0:76fed7dd9235 | 774 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54 */ |
| seanwilson10 | 0:76fed7dd9235 | 775 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55 */ |
| seanwilson10 | 0:76fed7dd9235 | 776 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56 */ |
| seanwilson10 | 0:76fed7dd9235 | 777 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57 */ |
| seanwilson10 | 0:76fed7dd9235 | 778 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58 */ |
| seanwilson10 | 0:76fed7dd9235 | 779 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59 */ |
| seanwilson10 | 0:76fed7dd9235 | 780 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510 */ |
| seanwilson10 | 0:76fed7dd9235 | 781 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 0x000000C4 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 782 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND51 0x00000104 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 783 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND52 0x00000144 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 784 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND53 0x00000184 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 785 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND54 0x000001C4 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 786 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND55 0x00000204 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 787 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND56 0x00000244 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 788 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND57 0x00000284 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 789 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND58 0x000002C4 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 790 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND59 0x00000304 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 791 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND510 0x00000344 /* ADISENSE_CORE Sensor Configuration Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 792 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND50 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 793 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 794 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command6[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 795 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 */ |
| seanwilson10 | 0:76fed7dd9235 | 796 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61 */ |
| seanwilson10 | 0:76fed7dd9235 | 797 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62 */ |
| seanwilson10 | 0:76fed7dd9235 | 798 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63 */ |
| seanwilson10 | 0:76fed7dd9235 | 799 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64 */ |
| seanwilson10 | 0:76fed7dd9235 | 800 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65 */ |
| seanwilson10 | 0:76fed7dd9235 | 801 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66 */ |
| seanwilson10 | 0:76fed7dd9235 | 802 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67 */ |
| seanwilson10 | 0:76fed7dd9235 | 803 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68 */ |
| seanwilson10 | 0:76fed7dd9235 | 804 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69 */ |
| seanwilson10 | 0:76fed7dd9235 | 805 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610 */ |
| seanwilson10 | 0:76fed7dd9235 | 806 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 0x000000C5 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 807 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND61 0x00000105 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 808 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND62 0x00000145 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 809 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND63 0x00000185 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 810 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND64 0x000001C5 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 811 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND65 0x00000205 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 812 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND66 0x00000245 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 813 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND67 0x00000285 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 814 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND68 0x000002C5 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 815 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND69 0x00000305 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 816 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND610 0x00000345 /* ADISENSE_CORE Sensor Configuration Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 817 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND60 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 818 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 819 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command7[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 820 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 */ |
| seanwilson10 | 0:76fed7dd9235 | 821 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71 */ |
| seanwilson10 | 0:76fed7dd9235 | 822 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72 */ |
| seanwilson10 | 0:76fed7dd9235 | 823 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73 */ |
| seanwilson10 | 0:76fed7dd9235 | 824 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74 */ |
| seanwilson10 | 0:76fed7dd9235 | 825 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75 */ |
| seanwilson10 | 0:76fed7dd9235 | 826 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76 */ |
| seanwilson10 | 0:76fed7dd9235 | 827 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77 */ |
| seanwilson10 | 0:76fed7dd9235 | 828 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78 */ |
| seanwilson10 | 0:76fed7dd9235 | 829 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79 */ |
| seanwilson10 | 0:76fed7dd9235 | 830 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710 */ |
| seanwilson10 | 0:76fed7dd9235 | 831 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 0x000000C6 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 832 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND71 0x00000106 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 833 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND72 0x00000146 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 834 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND73 0x00000186 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 835 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND74 0x000001C6 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 836 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND75 0x00000206 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 837 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND76 0x00000246 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 838 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND77 0x00000286 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 839 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND78 0x000002C6 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 840 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND79 0x00000306 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 841 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND710 0x00000346 /* ADISENSE_CORE Sensor Configuration Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 842 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND70 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 843 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 844 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd1[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 845 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 */ |
| seanwilson10 | 0:76fed7dd9235 | 846 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11 */ |
| seanwilson10 | 0:76fed7dd9235 | 847 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12 */ |
| seanwilson10 | 0:76fed7dd9235 | 848 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13 */ |
| seanwilson10 | 0:76fed7dd9235 | 849 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14 */ |
| seanwilson10 | 0:76fed7dd9235 | 850 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15 */ |
| seanwilson10 | 0:76fed7dd9235 | 851 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16 */ |
| seanwilson10 | 0:76fed7dd9235 | 852 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17 */ |
| seanwilson10 | 0:76fed7dd9235 | 853 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18 */ |
| seanwilson10 | 0:76fed7dd9235 | 854 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19 */ |
| seanwilson10 | 0:76fed7dd9235 | 855 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110 */ |
| seanwilson10 | 0:76fed7dd9235 | 856 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 0x000000C8 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 857 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD11 0x00000108 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 858 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD12 0x00000148 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 859 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD13 0x00000188 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 860 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD14 0x000001C8 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 861 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD15 0x00000208 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 862 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD16 0x00000248 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 863 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD17 0x00000288 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 864 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD18 0x000002C8 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 865 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD19 0x00000308 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 866 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD110 0x00000348 /* ADISENSE_CORE Sensor Read Command1 */ |
| seanwilson10 | 0:76fed7dd9235 | 867 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD10 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 868 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 869 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd2[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 870 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 */ |
| seanwilson10 | 0:76fed7dd9235 | 871 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21 */ |
| seanwilson10 | 0:76fed7dd9235 | 872 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22 */ |
| seanwilson10 | 0:76fed7dd9235 | 873 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23 */ |
| seanwilson10 | 0:76fed7dd9235 | 874 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24 */ |
| seanwilson10 | 0:76fed7dd9235 | 875 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25 */ |
| seanwilson10 | 0:76fed7dd9235 | 876 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26 */ |
| seanwilson10 | 0:76fed7dd9235 | 877 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27 */ |
| seanwilson10 | 0:76fed7dd9235 | 878 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28 */ |
| seanwilson10 | 0:76fed7dd9235 | 879 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29 */ |
| seanwilson10 | 0:76fed7dd9235 | 880 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210 */ |
| seanwilson10 | 0:76fed7dd9235 | 881 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 0x000000C9 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 882 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD21 0x00000109 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 883 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD22 0x00000149 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 884 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD23 0x00000189 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 885 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD24 0x000001C9 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 886 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD25 0x00000209 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 887 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD26 0x00000249 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 888 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD27 0x00000289 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 889 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD28 0x000002C9 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 890 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD29 0x00000309 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 891 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD210 0x00000349 /* ADISENSE_CORE Sensor Read Command2 */ |
| seanwilson10 | 0:76fed7dd9235 | 892 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD20 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 893 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 894 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd3[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 895 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 */ |
| seanwilson10 | 0:76fed7dd9235 | 896 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31 */ |
| seanwilson10 | 0:76fed7dd9235 | 897 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32 */ |
| seanwilson10 | 0:76fed7dd9235 | 898 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33 */ |
| seanwilson10 | 0:76fed7dd9235 | 899 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34 */ |
| seanwilson10 | 0:76fed7dd9235 | 900 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35 */ |
| seanwilson10 | 0:76fed7dd9235 | 901 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36 */ |
| seanwilson10 | 0:76fed7dd9235 | 902 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37 */ |
| seanwilson10 | 0:76fed7dd9235 | 903 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38 */ |
| seanwilson10 | 0:76fed7dd9235 | 904 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39 */ |
| seanwilson10 | 0:76fed7dd9235 | 905 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310 */ |
| seanwilson10 | 0:76fed7dd9235 | 906 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 0x000000CA /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 907 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD31 0x0000010A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 908 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD32 0x0000014A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 909 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD33 0x0000018A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 910 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD34 0x000001CA /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 911 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD35 0x0000020A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 912 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD36 0x0000024A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 913 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD37 0x0000028A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 914 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD38 0x000002CA /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 915 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD39 0x0000030A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 916 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD310 0x0000034A /* ADISENSE_CORE Sensor Read Command3 */ |
| seanwilson10 | 0:76fed7dd9235 | 917 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD30 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 918 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 919 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd4[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 920 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 */ |
| seanwilson10 | 0:76fed7dd9235 | 921 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41 */ |
| seanwilson10 | 0:76fed7dd9235 | 922 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42 */ |
| seanwilson10 | 0:76fed7dd9235 | 923 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43 */ |
| seanwilson10 | 0:76fed7dd9235 | 924 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44 */ |
| seanwilson10 | 0:76fed7dd9235 | 925 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45 */ |
| seanwilson10 | 0:76fed7dd9235 | 926 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46 */ |
| seanwilson10 | 0:76fed7dd9235 | 927 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47 */ |
| seanwilson10 | 0:76fed7dd9235 | 928 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48 */ |
| seanwilson10 | 0:76fed7dd9235 | 929 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49 */ |
| seanwilson10 | 0:76fed7dd9235 | 930 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410 */ |
| seanwilson10 | 0:76fed7dd9235 | 931 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 0x000000CB /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 932 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD41 0x0000010B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 933 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD42 0x0000014B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 934 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD43 0x0000018B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 935 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD44 0x000001CB /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 936 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD45 0x0000020B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 937 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD46 0x0000024B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 938 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD47 0x0000028B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 939 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD48 0x000002CB /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 940 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD49 0x0000030B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 941 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD410 0x0000034B /* ADISENSE_CORE Sensor Read Command4 */ |
| seanwilson10 | 0:76fed7dd9235 | 942 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD40 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 943 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 944 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd5[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 945 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 */ |
| seanwilson10 | 0:76fed7dd9235 | 946 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51 */ |
| seanwilson10 | 0:76fed7dd9235 | 947 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52 */ |
| seanwilson10 | 0:76fed7dd9235 | 948 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53 */ |
| seanwilson10 | 0:76fed7dd9235 | 949 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54 */ |
| seanwilson10 | 0:76fed7dd9235 | 950 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55 */ |
| seanwilson10 | 0:76fed7dd9235 | 951 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56 */ |
| seanwilson10 | 0:76fed7dd9235 | 952 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57 */ |
| seanwilson10 | 0:76fed7dd9235 | 953 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58 */ |
| seanwilson10 | 0:76fed7dd9235 | 954 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59 */ |
| seanwilson10 | 0:76fed7dd9235 | 955 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510 */ |
| seanwilson10 | 0:76fed7dd9235 | 956 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 0x000000CC /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 957 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD51 0x0000010C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 958 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD52 0x0000014C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 959 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD53 0x0000018C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 960 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD54 0x000001CC /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 961 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD55 0x0000020C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 962 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD56 0x0000024C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 963 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD57 0x0000028C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 964 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD58 0x000002CC /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 965 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD59 0x0000030C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 966 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD510 0x0000034C /* ADISENSE_CORE Sensor Read Command5 */ |
| seanwilson10 | 0:76fed7dd9235 | 967 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD50 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 968 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 969 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd6[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 970 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 */ |
| seanwilson10 | 0:76fed7dd9235 | 971 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61 */ |
| seanwilson10 | 0:76fed7dd9235 | 972 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62 */ |
| seanwilson10 | 0:76fed7dd9235 | 973 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63 */ |
| seanwilson10 | 0:76fed7dd9235 | 974 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64 */ |
| seanwilson10 | 0:76fed7dd9235 | 975 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65 */ |
| seanwilson10 | 0:76fed7dd9235 | 976 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66 */ |
| seanwilson10 | 0:76fed7dd9235 | 977 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67 */ |
| seanwilson10 | 0:76fed7dd9235 | 978 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68 */ |
| seanwilson10 | 0:76fed7dd9235 | 979 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69 */ |
| seanwilson10 | 0:76fed7dd9235 | 980 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610 */ |
| seanwilson10 | 0:76fed7dd9235 | 981 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 0x000000CD /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 982 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD61 0x0000010D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 983 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD62 0x0000014D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 984 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD63 0x0000018D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 985 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD64 0x000001CD /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 986 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD65 0x0000020D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 987 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD66 0x0000024D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 988 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD67 0x0000028D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 989 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD68 0x000002CD /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 990 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD69 0x0000030D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 991 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD610 0x0000034D /* ADISENSE_CORE Sensor Read Command6 */ |
| seanwilson10 | 0:76fed7dd9235 | 992 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD60 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 993 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 994 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd7[n] */ |
| seanwilson10 | 0:76fed7dd9235 | 995 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 */ |
| seanwilson10 | 0:76fed7dd9235 | 996 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71 */ |
| seanwilson10 | 0:76fed7dd9235 | 997 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72 */ |
| seanwilson10 | 0:76fed7dd9235 | 998 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73 */ |
| seanwilson10 | 0:76fed7dd9235 | 999 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74 */ |
| seanwilson10 | 0:76fed7dd9235 | 1000 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75 */ |
| seanwilson10 | 0:76fed7dd9235 | 1001 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76 */ |
| seanwilson10 | 0:76fed7dd9235 | 1002 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77 */ |
| seanwilson10 | 0:76fed7dd9235 | 1003 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78 */ |
| seanwilson10 | 0:76fed7dd9235 | 1004 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79 */ |
| seanwilson10 | 0:76fed7dd9235 | 1005 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710_RESET 0x00000000 /* Reset Value for REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710 */ |
| seanwilson10 | 0:76fed7dd9235 | 1006 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 0x000000CE /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1007 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD71 0x0000010E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1008 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD72 0x0000014E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1009 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD73 0x0000018E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1010 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD74 0x000001CE /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1011 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD75 0x0000020E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1012 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD76 0x0000024E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1013 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD77 0x0000028E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1014 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD78 0x000002CE /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1015 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD79 0x0000030E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1016 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD710 0x0000034E /* ADISENSE_CORE Sensor Read Command7 */ |
| seanwilson10 | 0:76fed7dd9235 | 1017 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n(i) (REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD70 + ((i) * 64)) |
| seanwilson10 | 0:76fed7dd9235 | 1018 | #define REG_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7n_COUNT 11 |
| seanwilson10 | 0:76fed7dd9235 | 1019 | |
| seanwilson10 | 0:76fed7dd9235 | 1020 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 1021 | ADISENSE_CORE Register BitMasks, Positions & Enumerations |
| seanwilson10 | 0:76fed7dd9235 | 1022 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 1023 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1024 | ADISENSE_CORE_COMMAND Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1025 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1026 | #define BITP_ADISENSE_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */ |
| seanwilson10 | 0:76fed7dd9235 | 1027 | #define BITM_ADISENSE_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */ |
| seanwilson10 | 0:76fed7dd9235 | 1028 | #define ENUM_ADISENSE_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */ |
| seanwilson10 | 0:76fed7dd9235 | 1029 | #define ENUM_ADISENSE_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */ |
| seanwilson10 | 0:76fed7dd9235 | 1030 | #define ENUM_ADISENSE_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1031 | #define ENUM_ADISENSE_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1032 | #define ENUM_ADISENSE_CORE_COMMAND_SELF_CALIBRATION 0x00000004 /* Special_Command: Initiate a Self-Calibration Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1033 | #define ENUM_ADISENSE_CORE_COMMAND_LOAD_CONFIG 0x00000005 /* Special_Command: Load Registers with Configuration from FLASH */ |
| seanwilson10 | 0:76fed7dd9235 | 1034 | #define ENUM_ADISENSE_CORE_COMMAND_SAVE_CONFIG 0x00000006 /* Special_Command: Store Current Register Configuration to FLASH */ |
| seanwilson10 | 0:76fed7dd9235 | 1035 | #define ENUM_ADISENSE_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch Configuration. */ |
| seanwilson10 | 0:76fed7dd9235 | 1036 | #define ENUM_ADISENSE_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */ |
| seanwilson10 | 0:76fed7dd9235 | 1037 | #define ENUM_ADISENSE_CORE_COMMAND_SAVE_LUT2 0x00000009 /* Special_Command: Save LUT to FLASH */ |
| seanwilson10 | 0:76fed7dd9235 | 1038 | #define ENUM_ADISENSE_CORE_COMMAND_SYSTEM_CHECK 0x0000000A /* Special_Command: Full Suite of Measurement Diagnostics */ |
| seanwilson10 | 0:76fed7dd9235 | 1039 | |
| seanwilson10 | 0:76fed7dd9235 | 1040 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1041 | ADISENSE_CORE_MODE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1042 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1043 | #define BITP_ADISENSE_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */ |
| seanwilson10 | 0:76fed7dd9235 | 1044 | #define BITP_ADISENSE_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1045 | #define BITM_ADISENSE_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */ |
| seanwilson10 | 0:76fed7dd9235 | 1046 | #define BITM_ADISENSE_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1047 | #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */ |
| seanwilson10 | 0:76fed7dd9235 | 1048 | #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1049 | #define ENUM_ADISENSE_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill */ |
| seanwilson10 | 0:76fed7dd9235 | 1050 | #define ENUM_ADISENSE_CORE_MODE_DRDY_MODE3 0x0000000C /* Drdy_Mode: Undefined */ |
| seanwilson10 | 0:76fed7dd9235 | 1051 | #define ENUM_ADISENSE_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1052 | #define ENUM_ADISENSE_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1053 | #define ENUM_ADISENSE_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */ |
| seanwilson10 | 0:76fed7dd9235 | 1054 | #define ENUM_ADISENSE_CORE_MODE_MODE3 0x00000003 /* Conversion_Mode: Undefined */ |
| seanwilson10 | 0:76fed7dd9235 | 1055 | |
| seanwilson10 | 0:76fed7dd9235 | 1056 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1057 | ADISENSE_CORE_POWER_CONFIG Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1058 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1059 | #define BITP_ADISENSE_CORE_POWER_CONFIG_STDBY_EN 4 /* Standby */ |
| seanwilson10 | 0:76fed7dd9235 | 1060 | #define BITP_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_MCU 2 /* MCU Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1061 | #define BITP_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1062 | #define BITM_ADISENSE_CORE_POWER_CONFIG_STDBY_EN 0x00000010 /* Standby */ |
| seanwilson10 | 0:76fed7dd9235 | 1063 | #define BITM_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_MCU 0x0000000C /* MCU Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1064 | #define BITM_ADISENSE_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1065 | #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_LOW_POWER 0x00000000 /* Power_Mode_ADC: ADC Low Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1066 | #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_MID_POWER 0x00000001 /* Power_Mode_ADC: ADC Mid Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1067 | #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER 0x00000002 /* Power_Mode_ADC: ADC Full Power Mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1068 | #define ENUM_ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER2 0x00000003 /* Power_Mode_ADC: ADC Full Power Mode2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1069 | |
| seanwilson10 | 0:76fed7dd9235 | 1070 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1071 | ADISENSE_CORE_CYCLE_CONTROL Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1072 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1073 | #define BITP_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */ |
| seanwilson10 | 0:76fed7dd9235 | 1074 | #define BITP_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1075 | #define BITM_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */ |
| seanwilson10 | 0:76fed7dd9235 | 1076 | #define BITM_ADISENSE_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1077 | #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */ |
| seanwilson10 | 0:76fed7dd9235 | 1078 | #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */ |
| seanwilson10 | 0:76fed7dd9235 | 1079 | #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */ |
| seanwilson10 | 0:76fed7dd9235 | 1080 | #define ENUM_ADISENSE_CORE_CYCLE_CONTROL_UNDEFINED 0x0000C000 /* Cycle_Time_Units: Undefined */ |
| seanwilson10 | 0:76fed7dd9235 | 1081 | |
| seanwilson10 | 0:76fed7dd9235 | 1082 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1083 | ADISENSE_CORE_FIFO_NUM_CYCLES Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1084 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1085 | #define BITP_ADISENSE_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1086 | #define BITM_ADISENSE_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1087 | |
| seanwilson10 | 0:76fed7dd9235 | 1088 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1089 | ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1090 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1091 | #define BITP_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0 /* Defines Time Between Repetitions of Measurement Cycles. */ |
| seanwilson10 | 0:76fed7dd9235 | 1092 | #define BITM_ADISENSE_CORE_MULTI_CYCLE_REPEAT_INTERVAL_MULTI_CYCLE_REPEAT_INTERVAL 0x00FFFFFF /* Defines Time Between Repetitions of Measurement Cycles. */ |
| seanwilson10 | 0:76fed7dd9235 | 1093 | |
| seanwilson10 | 0:76fed7dd9235 | 1094 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1095 | ADISENSE_CORE_STATUS Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1096 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1097 | #define BITP_ADISENSE_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1098 | #define BITP_ADISENSE_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1099 | #define BITP_ADISENSE_CORE_STATUS_DRDY 3 /* Indicates a New Sensor Result is Available to Be Read */ |
| seanwilson10 | 0:76fed7dd9235 | 1100 | #define BITP_ADISENSE_CORE_STATUS_ERROR 2 /* Indicates an Error */ |
| seanwilson10 | 0:76fed7dd9235 | 1101 | #define BITP_ADISENSE_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensors Alerts are Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1102 | #define BITM_ADISENSE_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1103 | #define BITM_ADISENSE_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1104 | #define BITM_ADISENSE_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor Result is Available to Be Read */ |
| seanwilson10 | 0:76fed7dd9235 | 1105 | #define BITM_ADISENSE_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */ |
| seanwilson10 | 0:76fed7dd9235 | 1106 | #define BITM_ADISENSE_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensors Alerts are Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1107 | |
| seanwilson10 | 0:76fed7dd9235 | 1108 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1109 | ADISENSE_CORE_DIAGNOSTICS_STATUS Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1110 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1111 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS_SUNDRY 14 /* Sundry Diagnostics Status */ |
| seanwilson10 | 0:76fed7dd9235 | 1112 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 13 /* Indicates Error During Internal Device Calibrations */ |
| seanwilson10 | 0:76fed7dd9235 | 1113 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 12 /* Indicates Error During Internal ADC Conversions */ |
| seanwilson10 | 0:76fed7dd9235 | 1114 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 11 /* Indicates Over-Voltage Error on Positive Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1115 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 10 /* Indicates Under-Voltage Error on Positive Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1116 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 9 /* Indicates Over-Voltage Error on Negative Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1117 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 8 /* Indicates Under-Voltage Error on Negative Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1118 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 3 /* Indicates Fault on Internal Supply Regulator Capacitor */ |
| seanwilson10 | 0:76fed7dd9235 | 1119 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 2 /* Indicates Low Voltage on Internal Supply Voltages */ |
| seanwilson10 | 0:76fed7dd9235 | 1120 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 1 /* Indicates Error on Internal Device Communications */ |
| seanwilson10 | 0:76fed7dd9235 | 1121 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0 /* Indicates Error on Internal Checksum Calculations */ |
| seanwilson10 | 0:76fed7dd9235 | 1122 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS_SUNDRY 0x0000C000 /* Sundry Diagnostics Status */ |
| seanwilson10 | 0:76fed7dd9235 | 1123 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 0x00002000 /* Indicates Error During Internal Device Calibrations */ |
| seanwilson10 | 0:76fed7dd9235 | 1124 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 0x00001000 /* Indicates Error During Internal ADC Conversions */ |
| seanwilson10 | 0:76fed7dd9235 | 1125 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 0x00000800 /* Indicates Over-Voltage Error on Positive Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1126 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 0x00000400 /* Indicates Under-Voltage Error on Positive Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1127 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 0x00000200 /* Indicates Over-Voltage Error on Negative Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1128 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 0x00000100 /* Indicates Under-Voltage Error on Negative Analog Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1129 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_CAP_ERROR 0x00000008 /* Indicates Fault on Internal Supply Regulator Capacitor */ |
| seanwilson10 | 0:76fed7dd9235 | 1130 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_SUPPLY_MONITOR_ERROR 0x00000004 /* Indicates Low Voltage on Internal Supply Voltages */ |
| seanwilson10 | 0:76fed7dd9235 | 1131 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_COMMS_ERROR 0x00000002 /* Indicates Error on Internal Device Communications */ |
| seanwilson10 | 0:76fed7dd9235 | 1132 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0x00000001 /* Indicates Error on Internal Checksum Calculations */ |
| seanwilson10 | 0:76fed7dd9235 | 1133 | |
| seanwilson10 | 0:76fed7dd9235 | 1134 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1135 | ADISENSE_CORE_CHANNEL_ALERT_STATUS Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1136 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1137 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1138 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1139 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1140 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1141 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1142 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1143 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1144 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1145 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1146 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1147 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1148 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1149 | #define BITP_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1150 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1151 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1152 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1153 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1154 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1155 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1156 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1157 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1158 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1159 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1160 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1161 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1162 | #define BITM_ADISENSE_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel Alert is Active */ |
| seanwilson10 | 0:76fed7dd9235 | 1163 | |
| seanwilson10 | 0:76fed7dd9235 | 1164 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1165 | ADISENSE_CORE_ALERT_STATUS_2 Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1166 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1167 | #define BITP_ADISENSE_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 2 /* Indicates Error with Programmed Configuration */ |
| seanwilson10 | 0:76fed7dd9235 | 1168 | #define BITP_ADISENSE_CORE_ALERT_STATUS_2_LUT_ERROR 1 /* Indicates Error with One or More Look-Up-Tables */ |
| seanwilson10 | 0:76fed7dd9235 | 1169 | #define BITM_ADISENSE_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 0x00000004 /* Indicates Error with Programmed Configuration */ |
| seanwilson10 | 0:76fed7dd9235 | 1170 | #define BITM_ADISENSE_CORE_ALERT_STATUS_2_LUT_ERROR 0x00000002 /* Indicates Error with One or More Look-Up-Tables */ |
| seanwilson10 | 0:76fed7dd9235 | 1171 | |
| seanwilson10 | 0:76fed7dd9235 | 1172 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1173 | ADISENSE_CORE_ALERT_DETAIL_CH[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1174 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1175 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 15 /* Indicates Compensation Channel Not Ready When Required */ |
| seanwilson10 | 0:76fed7dd9235 | 1176 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 14 /* Indicates Digital Sensor Not Ready When Read */ |
| seanwilson10 | 0:76fed7dd9235 | 1177 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 13 /* Indicates Result Larger Than LUT/Equation Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1178 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 12 /* Indicates Result Less Than LUT/Equation Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1179 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 11 /* Indicates Channel Over-Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1180 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 10 /* Indicates Channel Under-Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1181 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 9 /* Indicates Error with Channel Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1182 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_CONFIG_ERR 8 /* Indicates Configuration Error on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1183 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */ |
| seanwilson10 | 0:76fed7dd9235 | 1184 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */ |
| seanwilson10 | 0:76fed7dd9235 | 1185 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */ |
| seanwilson10 | 0:76fed7dd9235 | 1186 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */ |
| seanwilson10 | 0:76fed7dd9235 | 1187 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1188 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1189 | #define BITP_ADISENSE_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1190 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 0x00008000 /* Indicates Compensation Channel Not Ready When Required */ |
| seanwilson10 | 0:76fed7dd9235 | 1191 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 0x00004000 /* Indicates Digital Sensor Not Ready When Read */ |
| seanwilson10 | 0:76fed7dd9235 | 1192 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 0x00002000 /* Indicates Result Larger Than LUT/Equation Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1193 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 0x00001000 /* Indicates Result Less Than LUT/Equation Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1194 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 0x00000800 /* Indicates Channel Over-Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1195 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 0x00000400 /* Indicates Channel Under-Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1196 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 0x00000200 /* Indicates Error with Channel Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1197 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_CONFIG_ERR 0x00000100 /* Indicates Configuration Error on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1198 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */ |
| seanwilson10 | 0:76fed7dd9235 | 1199 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */ |
| seanwilson10 | 0:76fed7dd9235 | 1200 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */ |
| seanwilson10 | 0:76fed7dd9235 | 1201 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */ |
| seanwilson10 | 0:76fed7dd9235 | 1202 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1203 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */ |
| seanwilson10 | 0:76fed7dd9235 | 1204 | #define BITM_ADISENSE_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1205 | |
| seanwilson10 | 0:76fed7dd9235 | 1206 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1207 | ADISENSE_CORE_ERROR_CODE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1208 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1209 | #define BITP_ADISENSE_CORE_ERROR_CODE_ERROR_CODE 0 /* Code Indicating Type of Error */ |
| seanwilson10 | 0:76fed7dd9235 | 1210 | #define BITM_ADISENSE_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */ |
| seanwilson10 | 0:76fed7dd9235 | 1211 | |
| seanwilson10 | 0:76fed7dd9235 | 1212 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1213 | ADISENSE_CORE_ALERT_CODE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1214 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1215 | #define BITP_ADISENSE_CORE_ALERT_CODE_ALERT_CODE 0 /* Code Indicating Type of Alert */ |
| seanwilson10 | 0:76fed7dd9235 | 1216 | #define BITM_ADISENSE_CORE_ALERT_CODE_ALERT_CODE 0x0000FFFF /* Code Indicating Type of Alert */ |
| seanwilson10 | 0:76fed7dd9235 | 1217 | |
| seanwilson10 | 0:76fed7dd9235 | 1218 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1219 | ADISENSE_CORE_EXTERNAL_REFERENCE1 Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1220 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1221 | #define BITP_ADISENSE_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1222 | #define BITM_ADISENSE_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1223 | |
| seanwilson10 | 0:76fed7dd9235 | 1224 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1225 | ADISENSE_CORE_EXTERNAL_REFERENCE2 Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1226 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1227 | #define BITP_ADISENSE_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1228 | #define BITM_ADISENSE_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1229 | |
| seanwilson10 | 0:76fed7dd9235 | 1230 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1231 | ADISENSE_CORE_AVDD_VOLTAGE Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1232 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1233 | #define BITP_ADISENSE_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0 /* AVDD Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1234 | #define BITM_ADISENSE_CORE_AVDD_VOLTAGE_AVDD_VOLTAGE 0xFFFFFFFF /* AVDD Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1235 | |
| seanwilson10 | 0:76fed7dd9235 | 1236 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1237 | ADISENSE_CORE_DIAGNOSTICS_CONTROL Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1238 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1239 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAGNOSTICS_EXTRA 8 /* Additional Diagnostics Control */ |
| seanwilson10 | 0:76fed7dd9235 | 1240 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 2 /* Diagnostics Open Sensor Detect Frequency */ |
| seanwilson10 | 0:76fed7dd9235 | 1241 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 1242 | #define BITP_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 1243 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAGNOSTICS_EXTRA 0x0000FF00 /* Additional Diagnostics Control */ |
| seanwilson10 | 0:76fed7dd9235 | 1244 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x0000000C /* Diagnostics Open Sensor Detect Frequency */ |
| seanwilson10 | 0:76fed7dd9235 | 1245 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 1246 | #define BITM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */ |
| seanwilson10 | 0:76fed7dd9235 | 1247 | #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_OFF 0x00000000 /* Diag_OSD_Freq: No Open-Circuit Detection During Measurement */ |
| seanwilson10 | 0:76fed7dd9235 | 1248 | #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1249 | #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000008 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */ |
| seanwilson10 | 0:76fed7dd9235 | 1250 | #define ENUM_ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES 0x0000000C /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */ |
| seanwilson10 | 0:76fed7dd9235 | 1251 | |
| seanwilson10 | 0:76fed7dd9235 | 1252 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1253 | ADISENSE_CORE_DATA_FIFO Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1254 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1255 | #define BITP_ADISENSE_CORE_DATA_FIFO_RAW_SAMPLE 40 /* ADC Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1256 | #define BITP_ADISENSE_CORE_DATA_FIFO_CH_VALID 39 /* Indicates Whether Valid Data Read from FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1257 | #define BITP_ADISENSE_CORE_DATA_FIFO_CH_RAW 38 /* Indicates If RAW Data is Valid */ |
| seanwilson10 | 0:76fed7dd9235 | 1258 | #define BITP_ADISENSE_CORE_DATA_FIFO_CH_ALERT 37 /* Indicates Alert on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1259 | #define BITP_ADISENSE_CORE_DATA_FIFO_CH_ERROR 36 /* Indicates Error on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1260 | #define BITP_ADISENSE_CORE_DATA_FIFO_CHANNEL_ID 32 /* Indicates Which Channel This FIFO Data Corresponds to */ |
| seanwilson10 | 0:76fed7dd9235 | 1261 | #define BITP_ADISENSE_CORE_DATA_FIFO_SENSOR_RESULT 0 /* Linearized and Compensated Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1262 | #define BITM_ADISENSE_CORE_DATA_FIFO_RAW_SAMPLE 0xFFFFFF0000000000 /* ADC Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1263 | #define BITM_ADISENSE_CORE_DATA_FIFO_CH_VALID 0x8000000000 /* Indicates Whether Valid Data Read from FIFO */ |
| seanwilson10 | 0:76fed7dd9235 | 1264 | #define BITM_ADISENSE_CORE_DATA_FIFO_CH_RAW 0x4000000000 /* Indicates If RAW Data is Valid */ |
| seanwilson10 | 0:76fed7dd9235 | 1265 | #define BITM_ADISENSE_CORE_DATA_FIFO_CH_ALERT 0x2000000000 /* Indicates Alert on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1266 | #define BITM_ADISENSE_CORE_DATA_FIFO_CH_ERROR 0x1000000000 /* Indicates Error on Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1267 | #define BITM_ADISENSE_CORE_DATA_FIFO_CHANNEL_ID 0xF00000000 /* Indicates Which Channel This FIFO Data Corresponds to */ |
| seanwilson10 | 0:76fed7dd9235 | 1268 | #define BITM_ADISENSE_CORE_DATA_FIFO_SENSOR_RESULT 0xFFFFFFFF /* Linearized and Compensated Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1269 | |
| seanwilson10 | 0:76fed7dd9235 | 1270 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1271 | ADISENSE_CORE_LUT_SELECT Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1272 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1273 | #define BITP_ADISENSE_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1274 | #define BITM_ADISENSE_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1275 | #define ENUM_ADISENSE_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read Addressed LUT Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1276 | #define ENUM_ADISENSE_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write Addressed LUT Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1277 | |
| seanwilson10 | 0:76fed7dd9235 | 1278 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1279 | ADISENSE_CORE_LUT_OFFSET Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1280 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1281 | #define BITP_ADISENSE_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1282 | #define BITM_ADISENSE_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1283 | |
| seanwilson10 | 0:76fed7dd9235 | 1284 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1285 | ADISENSE_CORE_LUT_DATA Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1286 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1287 | #define BITP_ADISENSE_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1288 | #define BITM_ADISENSE_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */ |
| seanwilson10 | 0:76fed7dd9235 | 1289 | |
| seanwilson10 | 0:76fed7dd9235 | 1290 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1291 | ADISENSE_CORE_CAL_OFFSET Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1292 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1293 | #define BITP_ADISENSE_CORE_CAL_OFFSET_CAL_OFFSET 0 /* Offset into Calibration Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1294 | #define BITM_ADISENSE_CORE_CAL_OFFSET_CAL_OFFSET 0x00003FFF /* Offset into Calibration Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1295 | |
| seanwilson10 | 0:76fed7dd9235 | 1296 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1297 | ADISENSE_CORE_CAL_DATA Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1298 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1299 | #define BITP_ADISENSE_CORE_CAL_DATA_CAL_DATA 0 /* Data to Write to / Read from Calibration Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1300 | #define BITM_ADISENSE_CORE_CAL_DATA_CAL_DATA 0x000000FF /* Data to Write to / Read from Calibration Data */ |
| seanwilson10 | 0:76fed7dd9235 | 1301 | |
| seanwilson10 | 0:76fed7dd9235 | 1302 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1303 | ADISENSE_CORE_REVISION Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1304 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1305 | #define BITP_ADISENSE_CORE_REVISION_COMMS_PROTOCOL 16 /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1306 | #define BITP_ADISENSE_CORE_REVISION_HARDWARE_REVISION 8 /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1307 | #define BITP_ADISENSE_CORE_REVISION_FIRMWARE_REVISION 0 /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1308 | #define BITM_ADISENSE_CORE_REVISION_COMMS_PROTOCOL 0x00FF0000 /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1309 | #define BITM_ADISENSE_CORE_REVISION_HARDWARE_REVISION 0x0000FF00 /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1310 | #define BITM_ADISENSE_CORE_REVISION_FIRMWARE_REVISION 0x000000FF /* ID Info */ |
| seanwilson10 | 0:76fed7dd9235 | 1311 | |
| seanwilson10 | 0:76fed7dd9235 | 1312 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1313 | ADISENSE_CORE_CHANNEL_COUNT[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1314 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1315 | #define BITP_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1316 | #define BITP_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1317 | #define BITM_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1318 | #define BITM_ADISENSE_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */ |
| seanwilson10 | 0:76fed7dd9235 | 1319 | |
| seanwilson10 | 0:76fed7dd9235 | 1320 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1321 | ADISENSE_CORE_SENSOR_TYPE[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1322 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1323 | #define BITP_ADISENSE_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */ |
| seanwilson10 | 0:76fed7dd9235 | 1324 | #define BITM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */ |
| seanwilson10 | 0:76fed7dd9235 | 1325 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_DEF_L1 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1326 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_DEF_L1 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1327 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_DEF_L1 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1328 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_DEF_L2 0x0000000C /* Sensor_Type: Thermocouple Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1329 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_DEF_L2 0x0000000D /* Sensor_Type: Thermocouple Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1330 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_DEF_L2 0x0000000E /* Sensor_Type: Thermocouple Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1331 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_DEF_L2 0x0000000F /* Sensor_Type: Thermocouple Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1332 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_ADV_L1 0x00000010 /* Sensor_Type: Thermocouple T-Type Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1333 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_ADV_L1 0x00000011 /* Sensor_Type: Thermocouple J-Type Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1334 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_ADV_L1 0x00000012 /* Sensor_Type: Thermocouple K-Type Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1335 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_ADV_L2 0x0000001C /* Sensor_Type: Thermocouple Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1336 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_ADV_L2 0x0000001D /* Sensor_Type: Thermocouple Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1337 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_ADV_L2 0x0000001E /* Sensor_Type: Thermocouple Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1338 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_ADV_L2 0x0000001F /* Sensor_Type: Thermocouple Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1339 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_DEF_L1 0x00000020 /* Sensor_Type: RTD 2 Wire PT100 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1340 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_DEF_L1 0x00000021 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1341 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_DEF_L2 0x0000002C /* Sensor_Type: RTD 2 Wire Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1342 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_DEF_L2 0x0000002D /* Sensor_Type: RTD 2 Wire Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1343 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_DEF_L2 0x0000002E /* Sensor_Type: RTD 2 Wire Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1344 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_DEF_L2 0x0000002F /* Sensor_Type: RTD 2 Wire Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1345 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_ADV_L1 0x00000030 /* Sensor_Type: RTD 2 Wire PT100 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1346 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_ADV_L1 0x00000031 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1347 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_ADV_L2 0x0000003C /* Sensor_Type: RTD 2 Wire Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1348 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_ADV_L2 0x0000003D /* Sensor_Type: RTD 2 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1349 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_ADV_L2 0x0000003E /* Sensor_Type: RTD 2 Wire Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1350 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_ADV_L2 0x0000003F /* Sensor_Type: RTD 2 Wire Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1351 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_DEF_L1 0x00000040 /* Sensor_Type: RTD 3 Wire PT100 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1352 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_DEF_L1 0x00000041 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1353 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_DEF_L2 0x0000004C /* Sensor_Type: RTD 3 Wire Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1354 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_DEF_L2 0x0000004D /* Sensor_Type: RTD 3 Wire Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1355 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_DEF_L2 0x0000004E /* Sensor_Type: RTD 3 Wire Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1356 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_DEF_L2 0x0000004F /* Sensor_Type: RTD 3 Wire Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1357 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ADV_L1 0x00000050 /* Sensor_Type: RTD 3 Wire PT100 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1358 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ADV_L1 0x00000051 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1359 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_ADV_L2 0x0000005C /* Sensor_Type: RTD 3 Wire Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1360 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_ADV_L2 0x0000005D /* Sensor_Type: RTD 3 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1361 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_ADV_L2 0x0000005E /* Sensor_Type: RTD 3 Wire Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1362 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_ADV_L2 0x0000005F /* Sensor_Type: RTD 3 Wire Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1363 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_DEF_L1 0x00000060 /* Sensor_Type: RTD 4 Wire PT100 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1364 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_DEF_L1 0x00000061 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1365 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_DEF_L2 0x0000006C /* Sensor_Type: RTD 4 Wire Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1366 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_DEF_L2 0x0000006D /* Sensor_Type: RTD 4 Wire Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1367 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_DEF_L2 0x0000006E /* Sensor_Type: RTD 4 Wire Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1368 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_DEF_L2 0x0000006F /* Sensor_Type: RTD 4 Wire Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1369 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_ADV_L1 0x00000070 /* Sensor_Type: RTD 4 Wire PT100 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1370 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_ADV_L1 0x00000071 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1371 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_ADV_L2 0x0000007C /* Sensor_Type: RTD 4 Wire Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1372 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_ADV_L2 0x0000007D /* Sensor_Type: RTD 4 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1373 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_ADV_L2 0x0000007E /* Sensor_Type: RTD 4 Wire Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1374 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_ADV_L2 0x0000007F /* Sensor_Type: RTD 4 Wire Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1375 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_DEF_L1 0x00000080 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1376 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_DEF_L1 0x00000081 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Defined Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1377 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_DEF_L2 0x0000008C /* Sensor_Type: Thermistor Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1378 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_DEF_L2 0x0000008D /* Sensor_Type: Thermistor Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1379 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_DEF_L2 0x0000008E /* Sensor_Type: Thermistor Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1380 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_DEF_L2 0x0000008F /* Sensor_Type: Thermistor Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1381 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_ADV_L1 0x00000090 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1382 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_ADV_L1 0x00000091 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Advanced Level 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1383 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_ADV_L2 0x0000009C /* Sensor_Type: Thermistor Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1384 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_ADV_L2 0x0000009D /* Sensor_Type: Thermistor Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1385 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_ADV_L2 0x0000009E /* Sensor_Type: Thermistor Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1386 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_ADV_L2 0x0000009F /* Sensor_Type: Thermistor Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1387 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_DEF_L2 0x000000A0 /* Sensor_Type: Bridge 4 Wire Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1388 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_DEF_L2 0x000000A1 /* Sensor_Type: Bridge 4 Wire Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1389 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_DEF_L2 0x000000A2 /* Sensor_Type: Bridge 4 Wire Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1390 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_DEF_L2 0x000000A3 /* Sensor_Type: Bridge 4 Wire Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1391 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_ADV_L2 0x000000B0 /* Sensor_Type: Bridge 4 Wire Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1392 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_ADV_L2 0x000000B1 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1393 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_ADV_L2 0x000000B2 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1394 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_ADV_L2 0x000000B3 /* Sensor_Type: Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1395 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_DEF_L2 0x000000C0 /* Sensor_Type: Bridge 6 Wire Sensor 1 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1396 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_DEF_L2 0x000000C1 /* Sensor_Type: Bridge 6 Wire Sensor 2 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1397 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_DEF_L2 0x000000C2 /* Sensor_Type: Bridge 6 Wire Sensor 3 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1398 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_DEF_L2 0x000000C3 /* Sensor_Type: Bridge 6 Wire Sensor 4 Defined Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1399 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_ADV_L2 0x000000D0 /* Sensor_Type: Bridge 6 Wire Sensor 1 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1400 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_ADV_L2 0x000000D1 /* Sensor_Type: Bridge 6 Wire Sensor 2 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1401 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_ADV_L2 0x000000D2 /* Sensor_Type: Bridge 6 Wire Sensor 3 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1402 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_ADV_L2 0x000000D3 /* Sensor_Type: Bridge 6 Wire Sensor 4 Advanced Level 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1403 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000100 /* Sensor_Type: Voltage Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1404 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_HONEYWELL_TRUSTABILITY 0x00000110 /* Sensor_Type: Voltage Output Pressure Sensor 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1405 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_AMPHENOL_NPA300X 0x00000111 /* Sensor_Type: Voltage Output Pressure Sensor 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1406 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_3_DEF 0x00000112 /* Sensor_Type: Voltage Output Pressure Sensor 3 */ |
| seanwilson10 | 0:76fed7dd9235 | 1407 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000180 /* Sensor_Type: Current Input */ |
| seanwilson10 | 0:76fed7dd9235 | 1408 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_HONEYWELL_PX2 0x00000181 /* Sensor_Type: Current Output Pressure Sensor 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1409 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_2 0x00000182 /* Sensor_Type: Current Output Pressure Sensor 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1410 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_CUSTOM1 0x00000200 /* Sensor_Type: Custom1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1411 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_1 0x00000800 /* Sensor_Type: I2C Pressure Sensor 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1412 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_2 0x00000801 /* Sensor_Type: I2C Pressure Sensor 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1413 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_HONEYWELL_HUMIDICON 0x00000840 /* Sensor_Type: I2C Humidity Sensor 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1414 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_SENSIRION_SHT3X 0x00000841 /* Sensor_Type: I2C Humidity Sensor 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1415 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_HONEYWELL_TRUSTABILITY 0x00000C00 /* Sensor_Type: SPI Pressure Sensor 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1416 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_2 0x00000C01 /* Sensor_Type: SPI Pressure Sensor 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1417 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_1 0x00000C40 /* Sensor_Type: SPI Humidity Sensor Type 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1418 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_2 0x00000C41 /* Sensor_Type: SPI Humidity Sensor Type 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1419 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_1 0x00000C80 /* Sensor_Type: SPI Accelerometer Sensor Type 1 3-Axis */ |
| seanwilson10 | 0:76fed7dd9235 | 1420 | #define ENUM_ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_2 0x00000C81 /* Sensor_Type: SPI Accelerometer Sensor Type 2 3-Axis */ |
| seanwilson10 | 0:76fed7dd9235 | 1421 | |
| seanwilson10 | 0:76fed7dd9235 | 1422 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1423 | ADISENSE_CORE_SENSOR_DETAILS[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1424 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1425 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */ |
| seanwilson10 | 0:76fed7dd9235 | 1426 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */ |
| seanwilson10 | 0:76fed7dd9235 | 1427 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 1428 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */ |
| seanwilson10 | 0:76fed7dd9235 | 1429 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */ |
| seanwilson10 | 0:76fed7dd9235 | 1430 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1431 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 12 /* Indicates Channel for Third Term of Compensation */ |
| seanwilson10 | 0:76fed7dd9235 | 1432 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 8 /* Indicates Channel for Second Term of Compensation */ |
| seanwilson10 | 0:76fed7dd9235 | 1433 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1434 | #define BITP_ADISENSE_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */ |
| seanwilson10 | 0:76fed7dd9235 | 1435 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */ |
| seanwilson10 | 0:76fed7dd9235 | 1436 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */ |
| seanwilson10 | 0:76fed7dd9235 | 1437 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */ |
| seanwilson10 | 0:76fed7dd9235 | 1438 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */ |
| seanwilson10 | 0:76fed7dd9235 | 1439 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */ |
| seanwilson10 | 0:76fed7dd9235 | 1440 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1441 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 0x0000F000 /* Indicates Channel for Third Term of Compensation */ |
| seanwilson10 | 0:76fed7dd9235 | 1442 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 0x00000F00 /* Indicates Channel for Second Term of Compensation */ |
| seanwilson10 | 0:76fed7dd9235 | 1443 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1444 | #define BITM_ADISENSE_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */ |
| seanwilson10 | 0:76fed7dd9235 | 1445 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1446 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1447 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */ |
| seanwilson10 | 0:76fed7dd9235 | 1448 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_8 0x03000000 /* PGA_Gain: Gain of 8 */ |
| seanwilson10 | 0:76fed7dd9235 | 1449 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_16 0x04000000 /* PGA_Gain: Gain of 16 */ |
| seanwilson10 | 0:76fed7dd9235 | 1450 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_32 0x05000000 /* PGA_Gain: Gain of 32 */ |
| seanwilson10 | 0:76fed7dd9235 | 1451 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */ |
| seanwilson10 | 0:76fed7dd9235 | 1452 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */ |
| seanwilson10 | 0:76fed7dd9235 | 1453 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_INT 0x00000000 /* Reference_Select: Internal Reference */ |
| seanwilson10 | 0:76fed7dd9235 | 1454 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_AVDD 0x00100000 /* Reference_Select: AVDD */ |
| seanwilson10 | 0:76fed7dd9235 | 1455 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT1 0x00200000 /* Reference_Select: External Voltage on Refin1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1456 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT2 0x00300000 /* Reference_Select: External Voltage on Refin2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1457 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_RINT1 0x00400000 /* Reference_Select: Internal Resistor1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1458 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_RINT2 0x00500000 /* Reference_Select: Internal Resistor2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1459 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_REXT1 0x00600000 /* Reference_Select: External Resistor on Refin1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1460 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_REXT2 0x00700000 /* Reference_Select: External Resistor on Refin2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1461 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_REF_EXC 0x00800000 /* Reference_Select: Bridge Excitation Voltage */ |
| seanwilson10 | 0:76fed7dd9235 | 1462 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000000 /* Measurement_Units: Degrees C */ |
| seanwilson10 | 0:76fed7dd9235 | 1463 | #define ENUM_ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000001 /* Measurement_Units: Degrees F */ |
| seanwilson10 | 0:76fed7dd9235 | 1464 | |
| seanwilson10 | 0:76fed7dd9235 | 1465 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1466 | ADISENSE_CORE_CHANNEL_EXCITATION[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1467 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1468 | #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ |
| seanwilson10 | 0:76fed7dd9235 | 1469 | #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_STATIC_SWAP_3WIRE 6 /* Indicates 3-Wire Excitation Currents Should Be Swapped */ |
| seanwilson10 | 0:76fed7dd9235 | 1470 | #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 4 /* Disable Second Current Source */ |
| seanwilson10 | 0:76fed7dd9235 | 1471 | #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 3 /* Disable First Current Source */ |
| seanwilson10 | 0:76fed7dd9235 | 1472 | #define BITP_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1473 | #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_DONT_SWAP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ |
| seanwilson10 | 0:76fed7dd9235 | 1474 | #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_STATIC_SWAP_3WIRE 0x00000040 /* Indicates 3-Wire Excitation Currents Should Be Swapped */ |
| seanwilson10 | 0:76fed7dd9235 | 1475 | #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 0x00000010 /* Disable Second Current Source */ |
| seanwilson10 | 0:76fed7dd9235 | 1476 | #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 0x00000008 /* Disable First Current Source */ |
| seanwilson10 | 0:76fed7dd9235 | 1477 | #define BITM_ADISENSE_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */ |
| seanwilson10 | 0:76fed7dd9235 | 1478 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_OFF 0x00000000 /* IOUT_Excitation_Current: Disabled */ |
| seanwilson10 | 0:76fed7dd9235 | 1479 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_50UA 0x00000001 /* IOUT_Excitation_Current: 50 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1480 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_100UA 0x00000002 /* IOUT_Excitation_Current: 100 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1481 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000003 /* IOUT_Excitation_Current: 250 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1482 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000004 /* IOUT_Excitation_Current: 500 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1483 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_750UA 0x00000005 /* IOUT_Excitation_Current: 750 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1484 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000006 /* IOUT_Excitation_Current: 1000 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1485 | #define ENUM_ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA_2 0x00000007 /* IOUT_Excitation_Current: 1000 \mu;A */ |
| seanwilson10 | 0:76fed7dd9235 | 1486 | |
| seanwilson10 | 0:76fed7dd9235 | 1487 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1488 | ADISENSE_CORE_SETTLING_TIME[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1489 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1490 | #define BITP_ADISENSE_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1491 | #define BITM_ADISENSE_CORE_SETTLING_TIME_SETTLING_TIME 0x0000FFFF /* Settling Time to Allow When Switching to Channel */ |
| seanwilson10 | 0:76fed7dd9235 | 1492 | |
| seanwilson10 | 0:76fed7dd9235 | 1493 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1494 | ADISENSE_CORE_FILTER_SELECT[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1495 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1496 | #define BITP_ADISENSE_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */ |
| seanwilson10 | 0:76fed7dd9235 | 1497 | #define BITP_ADISENSE_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */ |
| seanwilson10 | 0:76fed7dd9235 | 1498 | #define BITM_ADISENSE_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x0000F800 /* ADC Digital Filter Type */ |
| seanwilson10 | 0:76fed7dd9235 | 1499 | #define BITM_ADISENSE_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */ |
| seanwilson10 | 0:76fed7dd9235 | 1500 | #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_25SPS 0x00000000 /* ADC_Filter_Type: FIR Filter 25 SPS */ |
| seanwilson10 | 0:76fed7dd9235 | 1501 | #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_20SPS 0x00000800 /* ADC_Filter_Type: FIR Filter 20 SPS */ |
| seanwilson10 | 0:76fed7dd9235 | 1502 | #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_SINC4 0x00001000 /* ADC_Filter_Type: Sinc4 Filter */ |
| seanwilson10 | 0:76fed7dd9235 | 1503 | #define ENUM_ADISENSE_CORE_FILTER_SELECT_FILTER_TBD 0x00001800 /* ADC_Filter_Type: TBD Filter */ |
| seanwilson10 | 0:76fed7dd9235 | 1504 | |
| seanwilson10 | 0:76fed7dd9235 | 1505 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1506 | ADISENSE_CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1507 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1508 | #define BITP_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */ |
| seanwilson10 | 0:76fed7dd9235 | 1509 | #define BITM_ADISENSE_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */ |
| seanwilson10 | 0:76fed7dd9235 | 1510 | |
| seanwilson10 | 0:76fed7dd9235 | 1511 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1512 | ADISENSE_CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1513 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1514 | #define BITP_ADISENSE_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */ |
| seanwilson10 | 0:76fed7dd9235 | 1515 | #define BITM_ADISENSE_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */ |
| seanwilson10 | 0:76fed7dd9235 | 1516 | |
| seanwilson10 | 0:76fed7dd9235 | 1517 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1518 | ADISENSE_CORE_SENSOR_OFFSET[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1519 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1520 | #define BITP_ADISENSE_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 1521 | #define BITM_ADISENSE_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 1522 | |
| seanwilson10 | 0:76fed7dd9235 | 1523 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1524 | ADISENSE_CORE_SENSOR_GAIN[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1525 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1526 | #define BITP_ADISENSE_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 1527 | #define BITM_ADISENSE_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */ |
| seanwilson10 | 0:76fed7dd9235 | 1528 | |
| seanwilson10 | 0:76fed7dd9235 | 1529 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1530 | ADISENSE_CORE_ALERT_CODE_CH[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1531 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1532 | #define BITP_ADISENSE_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0 /* Per-Channel Code Indicating Type of Alert */ |
| seanwilson10 | 0:76fed7dd9235 | 1533 | #define BITM_ADISENSE_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0x0000FFFF /* Per-Channel Code Indicating Type of Alert */ |
| seanwilson10 | 0:76fed7dd9235 | 1534 | |
| seanwilson10 | 0:76fed7dd9235 | 1535 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1536 | ADISENSE_CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1537 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1538 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */ |
| seanwilson10 | 0:76fed7dd9235 | 1539 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 8 /* Number of bytes to read from the sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1540 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 4 /* Data Bit Offset, relative to alignment */ |
| seanwilson10 | 0:76fed7dd9235 | 1541 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 3 /* Data Alignment within the data frame */ |
| seanwilson10 | 0:76fed7dd9235 | 1542 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 2 /* Data Endianness of Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1543 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0 /* Data Encoding of Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1544 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 0x000F800 /* Number of Relevant Data Bits */ |
| seanwilson10 | 0:76fed7dd9235 | 1545 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 0x0000700 /* Number of bytes to read from the sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1546 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 0x000000F0 /* Data Bit Offset, relative to alignment */ |
| seanwilson10 | 0:76fed7dd9235 | 1547 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFTALIGNED 0x00000008 /* Data Alignment within the data frame */ |
| seanwilson10 | 0:76fed7dd9235 | 1548 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTEENDIAN 0x00000004 /* Data Endianness of Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1549 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */ |
| seanwilson10 | 0:76fed7dd9235 | 1550 | #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */ |
| seanwilson10 | 0:76fed7dd9235 | 1551 | #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */ |
| seanwilson10 | 0:76fed7dd9235 | 1552 | #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos Complement */ |
| seanwilson10 | 0:76fed7dd9235 | 1553 | #define ENUM_ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset Binary */ |
| seanwilson10 | 0:76fed7dd9235 | 1554 | |
| seanwilson10 | 0:76fed7dd9235 | 1555 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1556 | ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1557 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1558 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1559 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1560 | |
| seanwilson10 | 0:76fed7dd9235 | 1561 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1562 | ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1563 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1564 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 4 /* Number of Read Commands for Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1565 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0 /* Number of Configuration Commands for Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1566 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 0x00000070 /* Number of Read Commands for Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1567 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0x00000007 /* Number of Configuration Commands for Digital Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1568 | |
| seanwilson10 | 0:76fed7dd9235 | 1569 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1570 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1571 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1572 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1573 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1574 | |
| seanwilson10 | 0:76fed7dd9235 | 1575 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1576 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1577 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1578 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1579 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1580 | |
| seanwilson10 | 0:76fed7dd9235 | 1581 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1582 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1583 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1584 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1585 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1586 | |
| seanwilson10 | 0:76fed7dd9235 | 1587 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1588 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1589 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1590 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1591 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1592 | |
| seanwilson10 | 0:76fed7dd9235 | 1593 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1594 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1595 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1596 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1597 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1598 | |
| seanwilson10 | 0:76fed7dd9235 | 1599 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1600 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1601 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1602 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1603 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1604 | |
| seanwilson10 | 0:76fed7dd9235 | 1605 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1606 | ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1607 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1608 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1609 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1610 | |
| seanwilson10 | 0:76fed7dd9235 | 1611 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1612 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1613 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1614 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1615 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1616 | |
| seanwilson10 | 0:76fed7dd9235 | 1617 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1618 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1619 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1620 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1621 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1622 | |
| seanwilson10 | 0:76fed7dd9235 | 1623 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1624 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1625 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1626 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1627 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1628 | |
| seanwilson10 | 0:76fed7dd9235 | 1629 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1630 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1631 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1632 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1633 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1634 | |
| seanwilson10 | 0:76fed7dd9235 | 1635 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1636 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1637 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1638 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1639 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1640 | |
| seanwilson10 | 0:76fed7dd9235 | 1641 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1642 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1643 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1644 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1645 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1646 | |
| seanwilson10 | 0:76fed7dd9235 | 1647 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1648 | ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7[n] Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1649 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1650 | #define BITP_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1651 | #define BITM_ADISENSE_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
| seanwilson10 | 0:76fed7dd9235 | 1652 | |
| seanwilson10 | 0:76fed7dd9235 | 1653 | |
| seanwilson10 | 0:76fed7dd9235 | 1654 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 1655 | Test Registers |
| seanwilson10 | 0:76fed7dd9235 | 1656 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 1657 | |
| seanwilson10 | 0:76fed7dd9235 | 1658 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 1659 | ADISENSE_TEST |
| seanwilson10 | 0:76fed7dd9235 | 1660 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 1661 | #define MOD_ADISENSE_TEST_BASE 0x00000400 /* Test Registers */ |
| seanwilson10 | 0:76fed7dd9235 | 1662 | #define MOD_ADISENSE_TEST_MASK 0x00007FFF /* Test Registers */ |
| seanwilson10 | 0:76fed7dd9235 | 1663 | #define REG_ADISENSE_TEST_TEST_REG_0_RESET 0x00000000 /* Reset Value for test_reg_0 */ |
| seanwilson10 | 0:76fed7dd9235 | 1664 | #define REG_ADISENSE_TEST_TEST_REG_0 0x00000400 /* ADISENSE_TEST Test Register 0 */ |
| seanwilson10 | 0:76fed7dd9235 | 1665 | #define REG_ADISENSE_TEST_ADC_CAL_TEMP_RESET 0x7fc00000 /* Reset Value for ADISENSE_TEST_ADC_CAL_TEMP */ |
| seanwilson10 | 0:76fed7dd9235 | 1666 | #define REG_ADISENSE_TEST_ADC_CAL_TEMP 0x00000404 /* ADC-sourced temperature used for calibration (read-only) */ |
| seanwilson10 | 0:76fed7dd9235 | 1667 | #define REG_ADISENSE_TEST_USER_CAL_TEMP_RESET 0x7fc00000 /* Reset Value for ADISENSE_TEST_USER_CAL_TEMP */ |
| seanwilson10 | 0:76fed7dd9235 | 1668 | #define REG_ADISENSE_TEST_USER_CAL_TEMP 0x00000408 /* User-specified temperature override for calibration */ |
| seanwilson10 | 0:76fed7dd9235 | 1669 | |
| seanwilson10 | 0:76fed7dd9235 | 1670 | /* ============================================================================================================================ |
| seanwilson10 | 0:76fed7dd9235 | 1671 | ADISENSE_TEST Register BitMasks, Positions & Enumerations |
| seanwilson10 | 0:76fed7dd9235 | 1672 | ============================================================================================================================ */ |
| seanwilson10 | 0:76fed7dd9235 | 1673 | /* ------------------------------------------------------------------------------------------------------------------------- |
| seanwilson10 | 0:76fed7dd9235 | 1674 | ADISENSE_TEST_TEST_REG_0 Pos/Masks Description |
| seanwilson10 | 0:76fed7dd9235 | 1675 | ------------------------------------------------------------------------------------------------------------------------- */ |
| seanwilson10 | 0:76fed7dd9235 | 1676 | #define BITP_ADISENSE_TEST_TEST_REG_0_TEST_COMMAND 0 /* Test_Command */ |
| seanwilson10 | 0:76fed7dd9235 | 1677 | #define BITM_ADISENSE_TEST_TEST_REG_0_TEST_COMMAND 0x000000FF /* Test_Command */ |
| seanwilson10 | 0:76fed7dd9235 | 1678 | |
| seanwilson10 | 0:76fed7dd9235 | 1679 | |
| seanwilson10 | 0:76fed7dd9235 | 1680 | /* ADISENSE_SPI Parameters */ |
| seanwilson10 | 0:76fed7dd9235 | 1681 | |
| seanwilson10 | 0:76fed7dd9235 | 1682 | /***** ADISENSE_SPI */ |
| seanwilson10 | 0:76fed7dd9235 | 1683 | #define PARAM_ADISENSE_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */ |
| seanwilson10 | 0:76fed7dd9235 | 1684 | #define PARAM_ADISENSE_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */ |
| seanwilson10 | 0:76fed7dd9235 | 1685 | #define PARAM_ADISENSE_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */ |
| seanwilson10 | 0:76fed7dd9235 | 1686 | #define PARAM_ADISENSE_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */ |
| seanwilson10 | 0:76fed7dd9235 | 1687 | #define PARAM_ADISENSE_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */ |
| seanwilson10 | 0:76fed7dd9235 | 1688 | #define PARAM_ADISENSE_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */ |
| seanwilson10 | 0:76fed7dd9235 | 1689 | #define PARAM_ADISENSE_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */ |
| seanwilson10 | 0:76fed7dd9235 | 1690 | #define PARAM_ADISENSE_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */ |
| seanwilson10 | 0:76fed7dd9235 | 1691 | #define PARAM_ADISENSE_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1692 | #define PARAM_ADISENSE_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */ |
| seanwilson10 | 0:76fed7dd9235 | 1693 | #define PARAM_ADISENSE_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */ |
| seanwilson10 | 0:76fed7dd9235 | 1694 | #define PARAM_ADISENSE_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */ |
| seanwilson10 | 0:76fed7dd9235 | 1695 | #define PARAM_ADISENSE_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */ |
| seanwilson10 | 0:76fed7dd9235 | 1696 | #define PARAM_ADISENSE_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */ |
| seanwilson10 | 0:76fed7dd9235 | 1697 | #define PARAM_ADISENSE_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */ |
| seanwilson10 | 0:76fed7dd9235 | 1698 | #define PARAM_ADISENSE_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */ |
| seanwilson10 | 0:76fed7dd9235 | 1699 | #define PARAM_ADISENSE_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */ |
| seanwilson10 | 0:76fed7dd9235 | 1700 | #define PARAM_ADISENSE_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */ |
| seanwilson10 | 0:76fed7dd9235 | 1701 | #define PARAM_ADISENSE_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */ |
| seanwilson10 | 0:76fed7dd9235 | 1702 | #define PARAM_ADISENSE_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */ |
| seanwilson10 | 0:76fed7dd9235 | 1703 | #define PARAM_ADISENSE_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */ |
| seanwilson10 | 0:76fed7dd9235 | 1704 | #define PARAM_ADISENSE_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */ |
| seanwilson10 | 0:76fed7dd9235 | 1705 | #define PARAM_ADISENSE_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1706 | #define PARAM_ADISENSE_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */ |
| seanwilson10 | 0:76fed7dd9235 | 1707 | #define PARAM_ADISENSE_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */ |
| seanwilson10 | 0:76fed7dd9235 | 1708 | #define PARAM_ADISENSE_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */ |
| seanwilson10 | 0:76fed7dd9235 | 1709 | #define PARAM_ADISENSE_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */ |
| seanwilson10 | 0:76fed7dd9235 | 1710 | #define PARAM_ADISENSE_SPI_SEND_STATUS_SUPPORT "NO_SEND_STATUS" /* Determines if and how the part supports the SEND_STATUS feature */ |
| seanwilson10 | 0:76fed7dd9235 | 1711 | #define PARAM_ADISENSE_SPI_SEND_STATUS_SUPPORT_ENABLE 0 /* This is used to enable various send status features */ |
| seanwilson10 | 0:76fed7dd9235 | 1712 | #define PARAM_ADISENSE_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */ |
| seanwilson10 | 0:76fed7dd9235 | 1713 | #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */ |
| seanwilson10 | 0:76fed7dd9235 | 1714 | #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */ |
| seanwilson10 | 0:76fed7dd9235 | 1715 | #define PARAM_ADISENSE_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */ |
| seanwilson10 | 0:76fed7dd9235 | 1716 | #define PARAM_ADISENSE_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */ |
| seanwilson10 | 0:76fed7dd9235 | 1717 | #define PARAM_ADISENSE_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */ |
| seanwilson10 | 0:76fed7dd9235 | 1718 | #define PARAM_ADISENSE_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */ |
| seanwilson10 | 0:76fed7dd9235 | 1719 | #define PARAM_ADISENSE_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */ |
| seanwilson10 | 0:76fed7dd9235 | 1720 | #define PARAM_ADISENSE_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1721 | #define PARAM_ADISENSE_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1722 | #define PARAM_ADISENSE_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */ |
| seanwilson10 | 0:76fed7dd9235 | 1723 | #define PARAM_ADISENSE_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */ |
| seanwilson10 | 0:76fed7dd9235 | 1724 | #define PARAM_ADISENSE_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */ |
| seanwilson10 | 0:76fed7dd9235 | 1725 | #define PARAM_ADISENSE_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */ |
| seanwilson10 | 0:76fed7dd9235 | 1726 | #define PARAM_ADISENSE_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */ |
| seanwilson10 | 0:76fed7dd9235 | 1727 | #define PARAM_ADISENSE_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */ |
| seanwilson10 | 0:76fed7dd9235 | 1728 | #define PARAM_ADISENSE_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */ |
| seanwilson10 | 0:76fed7dd9235 | 1729 | #define PARAM_ADISENSE_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */ |
| seanwilson10 | 0:76fed7dd9235 | 1730 | #define PARAM_ADISENSE_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */ |
| seanwilson10 | 0:76fed7dd9235 | 1731 | |
| seanwilson10 | 0:76fed7dd9235 | 1732 | #endif /* end ifndef _DEF_ADISENSE1000_REGISTERS_H */ |
| seanwilson10 | 0:76fed7dd9235 | 1733 |