lpc17xx_i2c.h

00001 /**********************************************************************
00002 * $Id$      lpc17xx_i2c.h               2010-05-21
00003 *//**
00004 * @file     lpc17xx_i2c.h
00005 * @brief    Contains all macro definitions and function prototypes
00006 *           support for I2C firmware library on LPC17xx
00007 * @version  2.0
00008 * @date     21. May. 2010
00009 * @author   NXP MCU SW Application Team
00010 *
00011 * Copyright(C) 2010, NXP Semiconductor
00012 * All rights reserved.
00013 *
00014 ***********************************************************************
00015 * Software that is described herein is for illustrative purposes only
00016 * which provides customers with programming information regarding the
00017 * products. This software is supplied "AS IS" without any warranties.
00018 * NXP Semiconductors assumes no responsibility or liability for the
00019 * use of the software, conveys no license or title under any patent,
00020 * copyright, or mask work right to the product. NXP Semiconductors
00021 * reserves the right to make changes in the software without
00022 * notification. NXP Semiconductors also make no representation or
00023 * warranty that such application will be suitable for the specified
00024 * use without further testing or modification.
00025 **********************************************************************/
00026 
00027 /* Peripheral group ----------------------------------------------------------- */
00028 /** @defgroup I2C I2C (Inter-IC Control bus)
00029  * @ingroup LPC1700CMSIS_FwLib_Drivers
00030  * @{
00031  */
00032 
00033 #ifndef LPC17XX_I2C_H_
00034 #define LPC17XX_I2C_H_
00035 
00036 /* Includes ------------------------------------------------------------------- */
00037 #include "LPC17xx.h"
00038 #include "lpc_types.h"
00039 
00040 
00041 #ifdef __cplusplus
00042 extern "C"
00043 {
00044 #endif
00045 
00046 
00047 /* Private Macros ------------------------------------------------------------- */
00048 /** @defgroup I2C_Private_Macros I2C Private Macros
00049  * @{
00050  */
00051 
00052 /* --------------------- BIT DEFINITIONS -------------------------------------- */
00053 /*******************************************************************//**
00054  * I2C Control Set register description
00055  *********************************************************************/
00056 #define I2C_I2CONSET_AA             ((0x04)) /*!< Assert acknowledge flag */
00057 #define I2C_I2CONSET_SI             ((0x08)) /*!< I2C interrupt flag */
00058 #define I2C_I2CONSET_STO            ((0x10)) /*!< STOP flag */
00059 #define I2C_I2CONSET_STA            ((0x20)) /*!< START flag */
00060 #define I2C_I2CONSET_I2EN           ((0x40)) /*!< I2C interface enable */
00061 
00062 /*******************************************************************//**
00063  * I2C Control Clear register description
00064  *********************************************************************/
00065 /** Assert acknowledge Clear bit */
00066 #define I2C_I2CONCLR_AAC            ((1<<2))
00067 /** I2C interrupt Clear bit */
00068 #define I2C_I2CONCLR_SIC            ((1<<3))
00069 /** START flag Clear bit */
00070 #define I2C_I2CONCLR_STAC           ((1<<5))
00071 /** I2C interface Disable bit */
00072 #define I2C_I2CONCLR_I2ENC          ((1<<6))
00073 
00074 /********************************************************************//**
00075  * I2C Status Code definition (I2C Status register)
00076  *********************************************************************/
00077 /* Return Code in I2C status register */
00078 #define I2C_STAT_CODE_BITMASK       ((0xF8))
00079 
00080 /* I2C return status code definitions ----------------------------- */
00081 
00082 /** No relevant information */
00083 #define I2C_I2STAT_NO_INF                       ((0xF8))
00084 
00085 /* Master transmit mode -------------------------------------------- */
00086 /** A start condition has been transmitted */
00087 #define I2C_I2STAT_M_TX_START                   ((0x08))
00088 /** A repeat start condition has been transmitted */
00089 #define I2C_I2STAT_M_TX_RESTART                 ((0x10))
00090 /** SLA+W has been transmitted, ACK has been received */
00091 #define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))
00092 /** SLA+W has been transmitted, NACK has been received */
00093 #define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))
00094 /** Data has been transmitted, ACK has been received */
00095 #define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))
00096 /** Data has been transmitted, NACK has been received */
00097 #define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))
00098 /** Arbitration lost in SLA+R/W or Data bytes */
00099 #define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))
00100 
00101 /* Master receive mode -------------------------------------------- */
00102 /** A start condition has been transmitted */
00103 #define I2C_I2STAT_M_RX_START                   ((0x08))
00104 /** A repeat start condition has been transmitted */
00105 #define I2C_I2STAT_M_RX_RESTART                 ((0x10))
00106 /** Arbitration lost */
00107 #define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))
00108 /** SLA+R has been transmitted, ACK has been received */
00109 #define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))
00110 /** SLA+R has been transmitted, NACK has been received */
00111 #define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))
00112 /** Data has been received, ACK has been returned */
00113 #define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))
00114 /** Data has been received, NACK has been return */
00115 #define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))
00116 
00117 /* Slave receive mode -------------------------------------------- */
00118 /** Own slave address has been received, ACK has been returned */
00119 #define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))
00120 
00121 /** Arbitration lost in SLA+R/W as master */
00122 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))
00123 /** Own SLA+W has been received, ACK returned */
00124 //#define I2C_I2STAT_S_RX_SLAW_ACK              ((0x68))
00125 
00126 /** General call address has been received, ACK has been returned */
00127 #define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))
00128 
00129 /** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
00130 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))
00131 /** General call address has been received, ACK has been returned */
00132 //#define I2C_I2STAT_S_RX_GENCALL_ACK               ((0x78))
00133 
00134 /** Previously addressed with own SLV address;
00135  * Data has been received, ACK has been return */
00136 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))
00137 /** Previously addressed with own SLA;
00138  * Data has been received and NOT ACK has been return */
00139 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))
00140 /** Previously addressed with General Call;
00141  * Data has been received and ACK has been return */
00142 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))
00143 /** Previously addressed with General Call;
00144  * Data has been received and NOT ACK has been return */
00145 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))
00146 /** A STOP condition or repeated START condition has
00147  * been received while still addressed as SLV/REC
00148  * (Slave Receive) or SLV/TRX (Slave Transmit) */
00149 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))
00150 
00151 /** Slave transmit mode */
00152 /** Own SLA+R has been received, ACK has been returned */
00153 #define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))
00154 
00155 /** Arbitration lost in SLA+R/W as master */
00156 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))
00157 /** Own SLA+R has been received, ACK has been returned */
00158 //#define I2C_I2STAT_S_TX_SLAR_ACK              ((0xB0))
00159 
00160 /** Data has been transmitted, ACK has been received */
00161 #define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))
00162 /** Data has been transmitted, NACK has been received */
00163 #define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))
00164 /** Last data byte in I2DAT has been transmitted (AA = 0);
00165  ACK has been received */
00166 #define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))
00167 
00168 /** Time out in case of using I2C slave mode */
00169 #define I2C_SLAVE_TIME_OUT                      0x10000UL
00170 
00171 /********************************************************************//**
00172  * I2C Data register definition
00173  *********************************************************************/
00174 /** Mask for I2DAT register*/
00175 #define I2C_I2DAT_BITMASK           ((0xFF))
00176 
00177 /** Idle data value will be send out in slave mode in case of the actual
00178  * expecting data requested from the master is greater than its sending data
00179  * length that can be supported */
00180 #define I2C_I2DAT_IDLE_CHAR         (0xFF)
00181 
00182 /********************************************************************//**
00183  * I2C Monitor mode control register description
00184  *********************************************************************/
00185 #define I2C_I2MMCTRL_MM_ENA         ((1<<0))        /**< Monitor mode enable */
00186 #define I2C_I2MMCTRL_ENA_SCL        ((1<<1))        /**< SCL output enable */
00187 #define I2C_I2MMCTRL_MATCH_ALL      ((1<<2))        /**< Select interrupt register match */
00188 #define I2C_I2MMCTRL_BITMASK        ((0x07))        /**< Mask for I2MMCTRL register */
00189 
00190 /********************************************************************//**
00191  * I2C Data buffer register description
00192  *********************************************************************/
00193 /** I2C Data buffer register bit mask */
00194 #define I2DATA_BUFFER_BITMASK       ((0xFF))
00195 
00196 /********************************************************************//**
00197  * I2C Slave Address registers definition
00198  *********************************************************************/
00199 /** General Call enable bit */
00200 #define I2C_I2ADR_GC                ((1<<0))
00201 /** I2C Slave Address registers bit mask */
00202 #define I2C_I2ADR_BITMASK           ((0xFF))
00203 
00204 /********************************************************************//**
00205  * I2C Mask Register definition
00206  *********************************************************************/
00207 /** I2C Mask Register mask field */
00208 #define I2C_I2MASK_MASK(n)          ((n&0xFE))
00209 
00210 /********************************************************************//**
00211  * I2C SCL HIGH duty cycle Register definition
00212  *********************************************************************/
00213 /** I2C SCL HIGH duty cycle Register bit mask */
00214 #define I2C_I2SCLH_BITMASK          ((0xFFFF))
00215 
00216 /********************************************************************//**
00217  * I2C SCL LOW duty cycle Register definition
00218  *********************************************************************/
00219 /** I2C SCL LOW duty cycle Register bit mask */
00220 #define I2C_I2SCLL_BITMASK          ((0xFFFF))
00221 
00222 /* I2C status values */
00223 #define I2C_SETUP_STATUS_ARBF   (1<<8)  /**< Arbitration false */
00224 #define I2C_SETUP_STATUS_NOACKF (1<<9)  /**< No ACK returned */
00225 #define I2C_SETUP_STATUS_DONE   (1<<10) /**< Status DONE */
00226 
00227 /*********************************************************************//**
00228  * I2C monitor control configuration defines
00229  **********************************************************************/
00230 #define I2C_MONITOR_CFG_SCL_OUTPUT  I2C_I2MMCTRL_ENA_SCL        /**< SCL output enable */
00231 #define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL      /**< Select interrupt register match */
00232 
00233 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
00234 /* Macros check I2C slave address */
00235 #define PARAM_I2C_SLAVEADDR_CH(n)   ((n>=0) && (n<=3))
00236 
00237 /** Macro to determine if it is valid SSP port number */
00238 #define PARAM_I2Cx(n)   ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
00239 || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
00240 || (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
00241 
00242 /* Macros check I2C monitor configuration type */
00243 #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
00244 
00245 /**
00246  * @}
00247  */
00248 
00249 
00250 
00251 /* Public Types --------------------------------------------------------------- */
00252 /** @defgroup I2C_Public_Types I2C Public Types
00253  * @{
00254  */
00255 
00256 /**
00257  * @brief I2C Own slave address setting structure
00258  */
00259 typedef struct {
00260     uint8_t SlaveAddrChannel;   /**< Slave Address channel in I2C control,
00261                                 should be in range from 0..3
00262                                 */
00263     uint8_t SlaveAddr_7bit;     /**< Value of 7-bit slave address */
00264     uint8_t GeneralCallState;   /**< Enable/Disable General Call Functionality
00265                                 when I2C control being in Slave mode, should be:
00266                                 - ENABLE: Enable General Call function.
00267                                 - DISABLE: Disable General Call function.
00268                                 */
00269     uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
00270                                 which is set to '1' will cause an automatic compare on
00271                                 the corresponding bit of the received address when it
00272                                 is compared to the SlaveAddr_7bit value associated with this
00273                                 mask register. In other words, bits in SlaveAddr_7bit value
00274                                 which are masked are not taken into account in determining
00275                                 an address match
00276                                 */
00277 } I2C_OWNSLAVEADDR_CFG_Type;
00278 
00279 
00280 /**
00281  * @brief Master transfer setup data structure definitions
00282  */
00283 typedef struct
00284 {
00285   uint32_t          sl_addr7bit;                /**< Slave address in 7bit mode */
00286   uint8_t*          tx_data;                    /**< Pointer to Transmit data - NULL if data transmit
00287                                                       is not used */
00288   uint32_t          tx_length;                  /**< Transmit data length - 0 if data transmit
00289                                                       is not used*/
00290   uint32_t          tx_count;                   /**< Current Transmit data counter */
00291   uint8_t*          rx_data;                    /**< Pointer to Receive data - NULL if data receive
00292                                                       is not used */
00293   uint32_t          rx_length;                  /**< Receive data length - 0 if data receive is
00294                                                        not used */
00295   uint32_t          rx_count;                   /**< Current Receive data counter */
00296   uint32_t          retransmissions_max;        /**< Max Re-Transmission value */
00297   uint32_t          retransmissions_count;      /**< Current Re-Transmission counter */
00298   uint32_t          status;                     /**< Current status of I2C activity */
00299   void              (*callback)(void);          /**< Pointer to Call back function when transmission complete
00300                                                     used in interrupt transfer mode */
00301 } I2C_M_SETUP_Type;
00302 
00303 
00304 /**
00305  * @brief Slave transfer setup data structure definitions
00306  */
00307 typedef struct
00308 {
00309   uint8_t*          tx_data;
00310   uint32_t          tx_length;
00311   uint32_t          tx_count;
00312   uint8_t*          rx_data;
00313   uint32_t          rx_length;
00314   uint32_t          rx_count;
00315   uint32_t          status;
00316   void              (*callback)(void);
00317 } I2C_S_SETUP_Type;
00318 
00319 /**
00320  * @brief Transfer option type definitions
00321  */
00322 typedef enum {
00323     I2C_TRANSFER_POLLING = 0,       /**< Transfer in polling mode */
00324     I2C_TRANSFER_INTERRUPT          /**< Transfer in interrupt mode */
00325 } I2C_TRANSFER_OPT_Type;
00326 
00327 
00328 /**
00329  * @}
00330  */
00331 
00332 
00333 /* Public Functions ----------------------------------------------------------- */
00334 /** @defgroup I2C_Public_Functions I2C Public Functions
00335  * @{
00336  */
00337 
00338 /* I2C Init/DeInit functions ---------- */
00339 void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
00340 void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
00341 //void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
00342 void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState);
00343 
00344 /* I2C transfer data functions -------- */
00345 Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
00346         I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
00347 Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
00348         I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
00349 uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx);
00350 uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx);
00351 
00352 
00353 void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
00354 uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
00355 
00356 /* I2C Monitor functions ---------------*/
00357 void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
00358 void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
00359 uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
00360 BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size);
00361 
00362 /* I2C Interrupt handler functions ------*/
00363 void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState);
00364 void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx);
00365 void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx);
00366 
00367 
00368 /**
00369  * @}
00370  */
00371 
00372 
00373 #ifdef __cplusplus
00374 }
00375 #endif
00376 
00377 #endif /* LPC17XX_I2C_H_ */
00378 
00379 /**
00380  * @}
00381  */
00382 
00383 /* --------------------------------- End Of File ------------------------------ */