BA / Mbed OS BaBoRo_test2

Backup 1

mbed-os/hal/mbed_itm_api.c@0:02dd72d1d465, 2018-04-24 (annotated)

Committer:
borlanic
Date:
Tue Apr 24 11:45:18 2018 +0000
Revision:
0:02dd72d1d465
BaBoRo_test2 - backup 1

Who changed what in which revision?

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borlanic 0:02dd72d1d465 1 /* mbed Microcontroller Library
borlanic 0:02dd72d1d465 2 * Copyright (c) 2017 ARM Limited
borlanic 0:02dd72d1d465 3 *
borlanic 0:02dd72d1d465 4 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:02dd72d1d465 5 * you may not use this file except in compliance with the License.
borlanic 0:02dd72d1d465 6 * You may obtain a copy of the License at
borlanic 0:02dd72d1d465 7 *
borlanic 0:02dd72d1d465 8 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:02dd72d1d465 9 *
borlanic 0:02dd72d1d465 10 * Unless required by applicable law or agreed to in writing, software
borlanic 0:02dd72d1d465 11 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:02dd72d1d465 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:02dd72d1d465 13 * See the License for the specific language governing permissions and
borlanic 0:02dd72d1d465 14 * limitations under the License.
borlanic 0:02dd72d1d465 15 */
borlanic 0:02dd72d1d465 16
borlanic 0:02dd72d1d465 17 #if defined(DEVICE_ITM)
borlanic 0:02dd72d1d465 18
borlanic 0:02dd72d1d465 19 #include "hal/itm_api.h"
borlanic 0:02dd72d1d465 20 #include "cmsis.h"
borlanic 0:02dd72d1d465 21
borlanic 0:02dd72d1d465 22 #include <stdbool.h>
borlanic 0:02dd72d1d465 23
borlanic 0:02dd72d1d465 24 #define ITM_ENABLE_WRITE 0xC5ACCE55
borlanic 0:02dd72d1d465 25
borlanic 0:02dd72d1d465 26 #define SWO_NRZ 0x02
borlanic 0:02dd72d1d465 27 #define SWO_STIMULUS_PORT 0x01
borlanic 0:02dd72d1d465 28
borlanic 0:02dd72d1d465 29 void mbed_itm_init(void)
borlanic 0:02dd72d1d465 30 {
borlanic 0:02dd72d1d465 31 static bool do_init = true;
borlanic 0:02dd72d1d465 32
borlanic 0:02dd72d1d465 33 if (do_init) {
borlanic 0:02dd72d1d465 34 do_init = false;
borlanic 0:02dd72d1d465 35
borlanic 0:02dd72d1d465 36 itm_init();
borlanic 0:02dd72d1d465 37
borlanic 0:02dd72d1d465 38 /* Enable write access to ITM registers. */
borlanic 0:02dd72d1d465 39 ITM->LAR = ITM_ENABLE_WRITE;
borlanic 0:02dd72d1d465 40
borlanic 0:02dd72d1d465 41 /* Trace Port Interface Selected Pin Protocol Register. */
borlanic 0:02dd72d1d465 42 TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
borlanic 0:02dd72d1d465 43
borlanic 0:02dd72d1d465 44 /* Trace Port Interface Formatter and Flush Control Register */
borlanic 0:02dd72d1d465 45 TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
borlanic 0:02dd72d1d465 46
borlanic 0:02dd72d1d465 47 /* Data Watchpoint and Trace Control Register */
borlanic 0:02dd72d1d465 48 DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) |
borlanic 0:02dd72d1d465 49 (0xF << DWT_CTRL_POSTINIT_Pos) |
borlanic 0:02dd72d1d465 50 (0xF << DWT_CTRL_POSTPRESET_Pos) |
borlanic 0:02dd72d1d465 51 (1 << DWT_CTRL_CYCCNTENA_Pos);
borlanic 0:02dd72d1d465 52
borlanic 0:02dd72d1d465 53 /* Trace Privilege Register.
borlanic 0:02dd72d1d465 54 * Disable access to trace channel configuration from non-privileged mode.
borlanic 0:02dd72d1d465 55 */
borlanic 0:02dd72d1d465 56 ITM->TPR = 0x0;
borlanic 0:02dd72d1d465 57
borlanic 0:02dd72d1d465 58 /* Trace Control Register */
borlanic 0:02dd72d1d465 59 ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) |
borlanic 0:02dd72d1d465 60 (1 << ITM_TCR_DWTENA_Pos) |
borlanic 0:02dd72d1d465 61 (1 << ITM_TCR_SYNCENA_Pos) |
borlanic 0:02dd72d1d465 62 (1 << ITM_TCR_ITMENA_Pos);
borlanic 0:02dd72d1d465 63
borlanic 0:02dd72d1d465 64 /* Trace Enable Register */
borlanic 0:02dd72d1d465 65 ITM->TER = SWO_STIMULUS_PORT;
borlanic 0:02dd72d1d465 66 }
borlanic 0:02dd72d1d465 67 }
borlanic 0:02dd72d1d465 68
borlanic 0:02dd72d1d465 69 uint32_t mbed_itm_send(uint32_t port, uint32_t data)
borlanic 0:02dd72d1d465 70 {
borlanic 0:02dd72d1d465 71 /* Check if ITM and port is enabled */
borlanic 0:02dd72d1d465 72 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
borlanic 0:02dd72d1d465 73 ((ITM->TER & (1UL << port) ) != 0UL) ) /* ITM Port enabled */
borlanic 0:02dd72d1d465 74 {
borlanic 0:02dd72d1d465 75 /* write data to port */
borlanic 0:02dd72d1d465 76 ITM->PORT[port].u32 = data;
borlanic 0:02dd72d1d465 77
borlanic 0:02dd72d1d465 78 /* Wait until data has been clocked out */
borlanic 0:02dd72d1d465 79 while (ITM->PORT[port].u32 == 0UL) {
borlanic 0:02dd72d1d465 80 __NOP();
borlanic 0:02dd72d1d465 81 }
borlanic 0:02dd72d1d465 82 }
borlanic 0:02dd72d1d465 83
borlanic 0:02dd72d1d465 84 return data;
borlanic 0:02dd72d1d465 85 }
borlanic 0:02dd72d1d465 86
borlanic 0:02dd72d1d465 87 #endif // defined(DEVICE_ITM)