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mbed-os/cmsis/TARGET_CORTEX_A/core_ca.h@0:02dd72d1d465, 2018-04-24 (annotated)

Committer:
borlanic
Date:
Tue Apr 24 11:45:18 2018 +0000
Revision:
0:02dd72d1d465
BaBoRo_test2 - backup 1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:02dd72d1d465 1 /**************************************************************************//**
borlanic 0:02dd72d1d465 2 * @file core_ca.h
borlanic 0:02dd72d1d465 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
borlanic 0:02dd72d1d465 4 * @version V1.00
borlanic 0:02dd72d1d465 5 * @date 22. Feb 2017
borlanic 0:02dd72d1d465 6 ******************************************************************************/
borlanic 0:02dd72d1d465 7 /*
borlanic 0:02dd72d1d465 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
borlanic 0:02dd72d1d465 9 *
borlanic 0:02dd72d1d465 10 * SPDX-License-Identifier: Apache-2.0
borlanic 0:02dd72d1d465 11 *
borlanic 0:02dd72d1d465 12 * Licensed under the Apache License, Version 2.0 (the License); you may
borlanic 0:02dd72d1d465 13 * not use this file except in compliance with the License.
borlanic 0:02dd72d1d465 14 * You may obtain a copy of the License at
borlanic 0:02dd72d1d465 15 *
borlanic 0:02dd72d1d465 16 * www.apache.org/licenses/LICENSE-2.0
borlanic 0:02dd72d1d465 17 *
borlanic 0:02dd72d1d465 18 * Unless required by applicable law or agreed to in writing, software
borlanic 0:02dd72d1d465 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
borlanic 0:02dd72d1d465 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:02dd72d1d465 21 * See the License for the specific language governing permissions and
borlanic 0:02dd72d1d465 22 * limitations under the License.
borlanic 0:02dd72d1d465 23 */
borlanic 0:02dd72d1d465 24
borlanic 0:02dd72d1d465 25 #if defined ( __ICCARM__ )
borlanic 0:02dd72d1d465 26 #pragma system_include /* treat file as system include file for MISRA check */
borlanic 0:02dd72d1d465 27 #elif defined (__clang__)
borlanic 0:02dd72d1d465 28 #pragma clang system_header /* treat file as system include file */
borlanic 0:02dd72d1d465 29 #endif
borlanic 0:02dd72d1d465 30
borlanic 0:02dd72d1d465 31 #ifdef __cplusplus
borlanic 0:02dd72d1d465 32 extern "C" {
borlanic 0:02dd72d1d465 33 #endif
borlanic 0:02dd72d1d465 34
borlanic 0:02dd72d1d465 35 #ifndef __CORE_CA_H_GENERIC
borlanic 0:02dd72d1d465 36 #define __CORE_CA_H_GENERIC
borlanic 0:02dd72d1d465 37
borlanic 0:02dd72d1d465 38
borlanic 0:02dd72d1d465 39 /*******************************************************************************
borlanic 0:02dd72d1d465 40 * CMSIS definitions
borlanic 0:02dd72d1d465 41 ******************************************************************************/
borlanic 0:02dd72d1d465 42
borlanic 0:02dd72d1d465 43 /* CMSIS CA definitions */
borlanic 0:02dd72d1d465 44 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
borlanic 0:02dd72d1d465 45 #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
borlanic 0:02dd72d1d465 46 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
borlanic 0:02dd72d1d465 47 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
borlanic 0:02dd72d1d465 48
borlanic 0:02dd72d1d465 49 #if defined ( __CC_ARM )
borlanic 0:02dd72d1d465 50 #if defined __TARGET_FPU_VFP
borlanic 0:02dd72d1d465 51 #if (__FPU_PRESENT == 1)
borlanic 0:02dd72d1d465 52 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 53 #else
borlanic 0:02dd72d1d465 54 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 55 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 56 #endif
borlanic 0:02dd72d1d465 57 #else
borlanic 0:02dd72d1d465 58 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 59 #endif
borlanic 0:02dd72d1d465 60
borlanic 0:02dd72d1d465 61 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
borlanic 0:02dd72d1d465 62 #if defined __ARM_PCS_VFP
borlanic 0:02dd72d1d465 63 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
borlanic 0:02dd72d1d465 64 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 65 #else
borlanic 0:02dd72d1d465 66 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 67 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 68 #endif
borlanic 0:02dd72d1d465 69 #else
borlanic 0:02dd72d1d465 70 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 71 #endif
borlanic 0:02dd72d1d465 72
borlanic 0:02dd72d1d465 73 #elif defined ( __ICCARM__ )
borlanic 0:02dd72d1d465 74 #if defined __ARMVFP__
borlanic 0:02dd72d1d465 75 #if (__FPU_PRESENT == 1)
borlanic 0:02dd72d1d465 76 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 77 #else
borlanic 0:02dd72d1d465 78 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 79 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 80 #endif
borlanic 0:02dd72d1d465 81 #else
borlanic 0:02dd72d1d465 82 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 83 #endif
borlanic 0:02dd72d1d465 84
borlanic 0:02dd72d1d465 85 #elif defined ( __TMS470__ )
borlanic 0:02dd72d1d465 86 #if defined __TI_VFP_SUPPORT__
borlanic 0:02dd72d1d465 87 #if (__FPU_PRESENT == 1)
borlanic 0:02dd72d1d465 88 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 89 #else
borlanic 0:02dd72d1d465 90 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 91 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 92 #endif
borlanic 0:02dd72d1d465 93 #else
borlanic 0:02dd72d1d465 94 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 95 #endif
borlanic 0:02dd72d1d465 96
borlanic 0:02dd72d1d465 97 #elif defined ( __GNUC__ )
borlanic 0:02dd72d1d465 98 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
borlanic 0:02dd72d1d465 99 #if (__FPU_PRESENT == 1)
borlanic 0:02dd72d1d465 100 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 101 #else
borlanic 0:02dd72d1d465 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 103 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 104 #endif
borlanic 0:02dd72d1d465 105 #else
borlanic 0:02dd72d1d465 106 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 107 #endif
borlanic 0:02dd72d1d465 108
borlanic 0:02dd72d1d465 109 #elif defined ( __TASKING__ )
borlanic 0:02dd72d1d465 110 #if defined __FPU_VFP__
borlanic 0:02dd72d1d465 111 #if (__FPU_PRESENT == 1)
borlanic 0:02dd72d1d465 112 #define __FPU_USED 1U
borlanic 0:02dd72d1d465 113 #else
borlanic 0:02dd72d1d465 114 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
borlanic 0:02dd72d1d465 115 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 116 #endif
borlanic 0:02dd72d1d465 117 #else
borlanic 0:02dd72d1d465 118 #define __FPU_USED 0U
borlanic 0:02dd72d1d465 119 #endif
borlanic 0:02dd72d1d465 120 #endif
borlanic 0:02dd72d1d465 121
borlanic 0:02dd72d1d465 122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
borlanic 0:02dd72d1d465 123
borlanic 0:02dd72d1d465 124 #ifdef __cplusplus
borlanic 0:02dd72d1d465 125 }
borlanic 0:02dd72d1d465 126 #endif
borlanic 0:02dd72d1d465 127
borlanic 0:02dd72d1d465 128 #endif /* __CORE_CA_H_GENERIC */
borlanic 0:02dd72d1d465 129
borlanic 0:02dd72d1d465 130 #ifndef __CMSIS_GENERIC
borlanic 0:02dd72d1d465 131
borlanic 0:02dd72d1d465 132 #ifndef __CORE_CA_H_DEPENDANT
borlanic 0:02dd72d1d465 133 #define __CORE_CA_H_DEPENDANT
borlanic 0:02dd72d1d465 134
borlanic 0:02dd72d1d465 135 #ifdef __cplusplus
borlanic 0:02dd72d1d465 136 extern "C" {
borlanic 0:02dd72d1d465 137 #endif
borlanic 0:02dd72d1d465 138
borlanic 0:02dd72d1d465 139 /* check device defines and use defaults */
borlanic 0:02dd72d1d465 140 #if defined __CHECK_DEVICE_DEFINES
borlanic 0:02dd72d1d465 141 #ifndef __CA_REV
borlanic 0:02dd72d1d465 142 #define __CA_REV 0x0000U
borlanic 0:02dd72d1d465 143 #warning "__CA_REV not defined in device header file; using default!"
borlanic 0:02dd72d1d465 144 #endif
borlanic 0:02dd72d1d465 145
borlanic 0:02dd72d1d465 146 #ifndef __FPU_PRESENT
borlanic 0:02dd72d1d465 147 #define __FPU_PRESENT 0U
borlanic 0:02dd72d1d465 148 #warning "__FPU_PRESENT not defined in device header file; using default!"
borlanic 0:02dd72d1d465 149 #endif
borlanic 0:02dd72d1d465 150
borlanic 0:02dd72d1d465 151 #ifndef __GIC_PRESENT
borlanic 0:02dd72d1d465 152 #define __GIC_PRESENT 1U
borlanic 0:02dd72d1d465 153 #warning "__GIC_PRESENT not defined in device header file; using default!"
borlanic 0:02dd72d1d465 154 #endif
borlanic 0:02dd72d1d465 155
borlanic 0:02dd72d1d465 156 #ifndef __TIM_PRESENT
borlanic 0:02dd72d1d465 157 #define __TIM_PRESENT 1U
borlanic 0:02dd72d1d465 158 #warning "__TIM_PRESENT not defined in device header file; using default!"
borlanic 0:02dd72d1d465 159 #endif
borlanic 0:02dd72d1d465 160
borlanic 0:02dd72d1d465 161 #ifndef __L2C_PRESENT
borlanic 0:02dd72d1d465 162 #define __L2C_PRESENT 0U
borlanic 0:02dd72d1d465 163 #warning "__L2C_PRESENT not defined in device header file; using default!"
borlanic 0:02dd72d1d465 164 #endif
borlanic 0:02dd72d1d465 165 #endif
borlanic 0:02dd72d1d465 166
borlanic 0:02dd72d1d465 167 /* IO definitions (access restrictions to peripheral registers) */
borlanic 0:02dd72d1d465 168 #ifdef __cplusplus
borlanic 0:02dd72d1d465 169 #define __I volatile /*!< \brief Defines 'read only' permissions */
borlanic 0:02dd72d1d465 170 #else
borlanic 0:02dd72d1d465 171 #define __I volatile const /*!< \brief Defines 'read only' permissions */
borlanic 0:02dd72d1d465 172 #endif
borlanic 0:02dd72d1d465 173 #define __O volatile /*!< \brief Defines 'write only' permissions */
borlanic 0:02dd72d1d465 174 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
borlanic 0:02dd72d1d465 175
borlanic 0:02dd72d1d465 176 /* following defines should be used for structure members */
borlanic 0:02dd72d1d465 177 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
borlanic 0:02dd72d1d465 178 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
borlanic 0:02dd72d1d465 179 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
borlanic 0:02dd72d1d465 180 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
borlanic 0:02dd72d1d465 181
borlanic 0:02dd72d1d465 182 /*******************************************************************************
borlanic 0:02dd72d1d465 183 * Register Abstraction
borlanic 0:02dd72d1d465 184 Core Register contain:
borlanic 0:02dd72d1d465 185 - CPSR
borlanic 0:02dd72d1d465 186 - CP15 Registers
borlanic 0:02dd72d1d465 187 - L2C-310 Cache Controller
borlanic 0:02dd72d1d465 188 - Generic Interrupt Controller Distributor
borlanic 0:02dd72d1d465 189 - Generic Interrupt Controller Interface
borlanic 0:02dd72d1d465 190 ******************************************************************************/
borlanic 0:02dd72d1d465 191
borlanic 0:02dd72d1d465 192 /* Core Register CPSR */
borlanic 0:02dd72d1d465 193 typedef union
borlanic 0:02dd72d1d465 194 {
borlanic 0:02dd72d1d465 195 struct
borlanic 0:02dd72d1d465 196 {
borlanic 0:02dd72d1d465 197 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
borlanic 0:02dd72d1d465 198 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
borlanic 0:02dd72d1d465 199 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
borlanic 0:02dd72d1d465 200 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
borlanic 0:02dd72d1d465 201 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
borlanic 0:02dd72d1d465 202 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
borlanic 0:02dd72d1d465 203 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
borlanic 0:02dd72d1d465 204 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
borlanic 0:02dd72d1d465 205 RESERVED(0:4, uint32_t)
borlanic 0:02dd72d1d465 206 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
borlanic 0:02dd72d1d465 207 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
borlanic 0:02dd72d1d465 208 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
borlanic 0:02dd72d1d465 209 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
borlanic 0:02dd72d1d465 210 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
borlanic 0:02dd72d1d465 211 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
borlanic 0:02dd72d1d465 212 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
borlanic 0:02dd72d1d465 213 } b; /*!< \brief Structure used for bit access */
borlanic 0:02dd72d1d465 214 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 215 } CPSR_Type;
borlanic 0:02dd72d1d465 216
borlanic 0:02dd72d1d465 217
borlanic 0:02dd72d1d465 218
borlanic 0:02dd72d1d465 219 /* CPSR Register Definitions */
borlanic 0:02dd72d1d465 220 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
borlanic 0:02dd72d1d465 221 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
borlanic 0:02dd72d1d465 222
borlanic 0:02dd72d1d465 223 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
borlanic 0:02dd72d1d465 224 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
borlanic 0:02dd72d1d465 225
borlanic 0:02dd72d1d465 226 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
borlanic 0:02dd72d1d465 227 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
borlanic 0:02dd72d1d465 228
borlanic 0:02dd72d1d465 229 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
borlanic 0:02dd72d1d465 230 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
borlanic 0:02dd72d1d465 231
borlanic 0:02dd72d1d465 232 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
borlanic 0:02dd72d1d465 233 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
borlanic 0:02dd72d1d465 234
borlanic 0:02dd72d1d465 235 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
borlanic 0:02dd72d1d465 236 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
borlanic 0:02dd72d1d465 237
borlanic 0:02dd72d1d465 238 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
borlanic 0:02dd72d1d465 239 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
borlanic 0:02dd72d1d465 240
borlanic 0:02dd72d1d465 241 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
borlanic 0:02dd72d1d465 242 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
borlanic 0:02dd72d1d465 243
borlanic 0:02dd72d1d465 244 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
borlanic 0:02dd72d1d465 245 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
borlanic 0:02dd72d1d465 246
borlanic 0:02dd72d1d465 247 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
borlanic 0:02dd72d1d465 248 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
borlanic 0:02dd72d1d465 249
borlanic 0:02dd72d1d465 250 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
borlanic 0:02dd72d1d465 251 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
borlanic 0:02dd72d1d465 252
borlanic 0:02dd72d1d465 253 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
borlanic 0:02dd72d1d465 254 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
borlanic 0:02dd72d1d465 255
borlanic 0:02dd72d1d465 256 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
borlanic 0:02dd72d1d465 257 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
borlanic 0:02dd72d1d465 258
borlanic 0:02dd72d1d465 259 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
borlanic 0:02dd72d1d465 260 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
borlanic 0:02dd72d1d465 261
borlanic 0:02dd72d1d465 262 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
borlanic 0:02dd72d1d465 263 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
borlanic 0:02dd72d1d465 264
borlanic 0:02dd72d1d465 265 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
borlanic 0:02dd72d1d465 266 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
borlanic 0:02dd72d1d465 267 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
borlanic 0:02dd72d1d465 268 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
borlanic 0:02dd72d1d465 269 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
borlanic 0:02dd72d1d465 270 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
borlanic 0:02dd72d1d465 271 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
borlanic 0:02dd72d1d465 272 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
borlanic 0:02dd72d1d465 273 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
borlanic 0:02dd72d1d465 274
borlanic 0:02dd72d1d465 275 /* CP15 Register SCTLR */
borlanic 0:02dd72d1d465 276 typedef union
borlanic 0:02dd72d1d465 277 {
borlanic 0:02dd72d1d465 278 struct
borlanic 0:02dd72d1d465 279 {
borlanic 0:02dd72d1d465 280 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
borlanic 0:02dd72d1d465 281 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
borlanic 0:02dd72d1d465 282 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
borlanic 0:02dd72d1d465 283 RESERVED(0:2, uint32_t)
borlanic 0:02dd72d1d465 284 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
borlanic 0:02dd72d1d465 285 RESERVED(1:1, uint32_t)
borlanic 0:02dd72d1d465 286 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
borlanic 0:02dd72d1d465 287 RESERVED(2:2, uint32_t)
borlanic 0:02dd72d1d465 288 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
borlanic 0:02dd72d1d465 289 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
borlanic 0:02dd72d1d465 290 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
borlanic 0:02dd72d1d465 291 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
borlanic 0:02dd72d1d465 292 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
borlanic 0:02dd72d1d465 293 RESERVED(3:2, uint32_t)
borlanic 0:02dd72d1d465 294 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
borlanic 0:02dd72d1d465 295 RESERVED(4:1, uint32_t)
borlanic 0:02dd72d1d465 296 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
borlanic 0:02dd72d1d465 297 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
borlanic 0:02dd72d1d465 298 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
borlanic 0:02dd72d1d465 299 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
borlanic 0:02dd72d1d465 300 RESERVED(5:1, uint32_t)
borlanic 0:02dd72d1d465 301 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
borlanic 0:02dd72d1d465 302 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
borlanic 0:02dd72d1d465 303 RESERVED(6:1, uint32_t)
borlanic 0:02dd72d1d465 304 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
borlanic 0:02dd72d1d465 305 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
borlanic 0:02dd72d1d465 306 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
borlanic 0:02dd72d1d465 307 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
borlanic 0:02dd72d1d465 308 RESERVED(7:1, uint32_t)
borlanic 0:02dd72d1d465 309 } b; /*!< \brief Structure used for bit access */
borlanic 0:02dd72d1d465 310 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 311 } SCTLR_Type;
borlanic 0:02dd72d1d465 312
borlanic 0:02dd72d1d465 313 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
borlanic 0:02dd72d1d465 314 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
borlanic 0:02dd72d1d465 315
borlanic 0:02dd72d1d465 316 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
borlanic 0:02dd72d1d465 317 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
borlanic 0:02dd72d1d465 318
borlanic 0:02dd72d1d465 319 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
borlanic 0:02dd72d1d465 320 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
borlanic 0:02dd72d1d465 321
borlanic 0:02dd72d1d465 322 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
borlanic 0:02dd72d1d465 323 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
borlanic 0:02dd72d1d465 324
borlanic 0:02dd72d1d465 325 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
borlanic 0:02dd72d1d465 326 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
borlanic 0:02dd72d1d465 327
borlanic 0:02dd72d1d465 328 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
borlanic 0:02dd72d1d465 329 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
borlanic 0:02dd72d1d465 330
borlanic 0:02dd72d1d465 331 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
borlanic 0:02dd72d1d465 332 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
borlanic 0:02dd72d1d465 333
borlanic 0:02dd72d1d465 334 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
borlanic 0:02dd72d1d465 335 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
borlanic 0:02dd72d1d465 336
borlanic 0:02dd72d1d465 337 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
borlanic 0:02dd72d1d465 338 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
borlanic 0:02dd72d1d465 339
borlanic 0:02dd72d1d465 340 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
borlanic 0:02dd72d1d465 341 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
borlanic 0:02dd72d1d465 342
borlanic 0:02dd72d1d465 343 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
borlanic 0:02dd72d1d465 344 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
borlanic 0:02dd72d1d465 345
borlanic 0:02dd72d1d465 346 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
borlanic 0:02dd72d1d465 347 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
borlanic 0:02dd72d1d465 348
borlanic 0:02dd72d1d465 349 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
borlanic 0:02dd72d1d465 350 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
borlanic 0:02dd72d1d465 351
borlanic 0:02dd72d1d465 352 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
borlanic 0:02dd72d1d465 353 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
borlanic 0:02dd72d1d465 354
borlanic 0:02dd72d1d465 355 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
borlanic 0:02dd72d1d465 356 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
borlanic 0:02dd72d1d465 357
borlanic 0:02dd72d1d465 358 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
borlanic 0:02dd72d1d465 359 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
borlanic 0:02dd72d1d465 360
borlanic 0:02dd72d1d465 361 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
borlanic 0:02dd72d1d465 362 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
borlanic 0:02dd72d1d465 363
borlanic 0:02dd72d1d465 364 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
borlanic 0:02dd72d1d465 365 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
borlanic 0:02dd72d1d465 366
borlanic 0:02dd72d1d465 367 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
borlanic 0:02dd72d1d465 368 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
borlanic 0:02dd72d1d465 369
borlanic 0:02dd72d1d465 370 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
borlanic 0:02dd72d1d465 371 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
borlanic 0:02dd72d1d465 372
borlanic 0:02dd72d1d465 373 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
borlanic 0:02dd72d1d465 374 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
borlanic 0:02dd72d1d465 375
borlanic 0:02dd72d1d465 376 /* CP15 Register ACTLR */
borlanic 0:02dd72d1d465 377 typedef union
borlanic 0:02dd72d1d465 378 {
borlanic 0:02dd72d1d465 379 #if __CORTEX_A == 5 || defined(DOXYGEN)
borlanic 0:02dd72d1d465 380 /** \brief Structure used for bit access on Cortex-A5 */
borlanic 0:02dd72d1d465 381 struct
borlanic 0:02dd72d1d465 382 {
borlanic 0:02dd72d1d465 383 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
borlanic 0:02dd72d1d465 384 RESERVED(0:5, uint32_t)
borlanic 0:02dd72d1d465 385 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
borlanic 0:02dd72d1d465 386 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
borlanic 0:02dd72d1d465 387 RESERVED(1:2, uint32_t)
borlanic 0:02dd72d1d465 388 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
borlanic 0:02dd72d1d465 389 uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
borlanic 0:02dd72d1d465 390 uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
borlanic 0:02dd72d1d465 391 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
borlanic 0:02dd72d1d465 392 uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
borlanic 0:02dd72d1d465 393 uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
borlanic 0:02dd72d1d465 394 uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
borlanic 0:02dd72d1d465 395 RESERVED(3:9, uint32_t)
borlanic 0:02dd72d1d465 396 uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
borlanic 0:02dd72d1d465 397 RESERVED(7:3, uint32_t)
borlanic 0:02dd72d1d465 398 } b;
borlanic 0:02dd72d1d465 399 #endif
borlanic 0:02dd72d1d465 400 #if __CORTEX_A == 7 || defined(DOXYGEN)
borlanic 0:02dd72d1d465 401 /** \brief Structure used for bit access on Cortex-A7 */
borlanic 0:02dd72d1d465 402 struct
borlanic 0:02dd72d1d465 403 {
borlanic 0:02dd72d1d465 404 RESERVED(0:6, uint32_t)
borlanic 0:02dd72d1d465 405 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
borlanic 0:02dd72d1d465 406 RESERVED(1:3, uint32_t)
borlanic 0:02dd72d1d465 407 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
borlanic 0:02dd72d1d465 408 uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
borlanic 0:02dd72d1d465 409 uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
borlanic 0:02dd72d1d465 410 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
borlanic 0:02dd72d1d465 411 uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
borlanic 0:02dd72d1d465 412 RESERVED(3:12, uint32_t)
borlanic 0:02dd72d1d465 413 uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
borlanic 0:02dd72d1d465 414 RESERVED(7:3, uint32_t)
borlanic 0:02dd72d1d465 415 } b;
borlanic 0:02dd72d1d465 416 #endif
borlanic 0:02dd72d1d465 417 #if __CORTEX_A == 9 || defined(DOXYGEN)
borlanic 0:02dd72d1d465 418 /** \brief Structure used for bit access on Cortex-A9 */
borlanic 0:02dd72d1d465 419 struct
borlanic 0:02dd72d1d465 420 {
borlanic 0:02dd72d1d465 421 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
borlanic 0:02dd72d1d465 422 RESERVED(0:1, uint32_t)
borlanic 0:02dd72d1d465 423 uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
borlanic 0:02dd72d1d465 424 uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
borlanic 0:02dd72d1d465 425 RESERVED(1:2, uint32_t)
borlanic 0:02dd72d1d465 426 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
borlanic 0:02dd72d1d465 427 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
borlanic 0:02dd72d1d465 428 uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
borlanic 0:02dd72d1d465 429 uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
borlanic 0:02dd72d1d465 430 RESERVED(7:22, uint32_t)
borlanic 0:02dd72d1d465 431 } b;
borlanic 0:02dd72d1d465 432 #endif
borlanic 0:02dd72d1d465 433 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 434 } ACTLR_Type;
borlanic 0:02dd72d1d465 435
borlanic 0:02dd72d1d465 436 #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
borlanic 0:02dd72d1d465 437 #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
borlanic 0:02dd72d1d465 438
borlanic 0:02dd72d1d465 439 #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
borlanic 0:02dd72d1d465 440 #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
borlanic 0:02dd72d1d465 441
borlanic 0:02dd72d1d465 442 #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
borlanic 0:02dd72d1d465 443 #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
borlanic 0:02dd72d1d465 444
borlanic 0:02dd72d1d465 445 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
borlanic 0:02dd72d1d465 446 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
borlanic 0:02dd72d1d465 447
borlanic 0:02dd72d1d465 448 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
borlanic 0:02dd72d1d465 449 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
borlanic 0:02dd72d1d465 450
borlanic 0:02dd72d1d465 451 #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
borlanic 0:02dd72d1d465 452 #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
borlanic 0:02dd72d1d465 453
borlanic 0:02dd72d1d465 454 #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
borlanic 0:02dd72d1d465 455 #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
borlanic 0:02dd72d1d465 456
borlanic 0:02dd72d1d465 457 #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
borlanic 0:02dd72d1d465 458 #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
borlanic 0:02dd72d1d465 459
borlanic 0:02dd72d1d465 460 #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
borlanic 0:02dd72d1d465 461 #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
borlanic 0:02dd72d1d465 462
borlanic 0:02dd72d1d465 463 #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
borlanic 0:02dd72d1d465 464 #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
borlanic 0:02dd72d1d465 465
borlanic 0:02dd72d1d465 466 #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
borlanic 0:02dd72d1d465 467 #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
borlanic 0:02dd72d1d465 468
borlanic 0:02dd72d1d465 469 #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
borlanic 0:02dd72d1d465 470 #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
borlanic 0:02dd72d1d465 471
borlanic 0:02dd72d1d465 472 #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
borlanic 0:02dd72d1d465 473 #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
borlanic 0:02dd72d1d465 474
borlanic 0:02dd72d1d465 475 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
borlanic 0:02dd72d1d465 476 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
borlanic 0:02dd72d1d465 477
borlanic 0:02dd72d1d465 478 #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
borlanic 0:02dd72d1d465 479 #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
borlanic 0:02dd72d1d465 480
borlanic 0:02dd72d1d465 481 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
borlanic 0:02dd72d1d465 482 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
borlanic 0:02dd72d1d465 483
borlanic 0:02dd72d1d465 484 #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
borlanic 0:02dd72d1d465 485 #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
borlanic 0:02dd72d1d465 486
borlanic 0:02dd72d1d465 487 #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
borlanic 0:02dd72d1d465 488 #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
borlanic 0:02dd72d1d465 489
borlanic 0:02dd72d1d465 490 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
borlanic 0:02dd72d1d465 491 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
borlanic 0:02dd72d1d465 492
borlanic 0:02dd72d1d465 493 /* CP15 Register CPACR */
borlanic 0:02dd72d1d465 494 typedef union
borlanic 0:02dd72d1d465 495 {
borlanic 0:02dd72d1d465 496 struct
borlanic 0:02dd72d1d465 497 {
borlanic 0:02dd72d1d465 498 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
borlanic 0:02dd72d1d465 499 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
borlanic 0:02dd72d1d465 500 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
borlanic 0:02dd72d1d465 501 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
borlanic 0:02dd72d1d465 502 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
borlanic 0:02dd72d1d465 503 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
borlanic 0:02dd72d1d465 504 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
borlanic 0:02dd72d1d465 505 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
borlanic 0:02dd72d1d465 506 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
borlanic 0:02dd72d1d465 507 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
borlanic 0:02dd72d1d465 508 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
borlanic 0:02dd72d1d465 509 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
borlanic 0:02dd72d1d465 510 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
borlanic 0:02dd72d1d465 511 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
borlanic 0:02dd72d1d465 512 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
borlanic 0:02dd72d1d465 513 RESERVED(0:1, uint32_t)
borlanic 0:02dd72d1d465 514 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
borlanic 0:02dd72d1d465 515 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
borlanic 0:02dd72d1d465 516 } b; /*!< \brief Structure used for bit access */
borlanic 0:02dd72d1d465 517 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 518 } CPACR_Type;
borlanic 0:02dd72d1d465 519
borlanic 0:02dd72d1d465 520 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
borlanic 0:02dd72d1d465 521 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
borlanic 0:02dd72d1d465 522
borlanic 0:02dd72d1d465 523 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
borlanic 0:02dd72d1d465 524 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
borlanic 0:02dd72d1d465 525
borlanic 0:02dd72d1d465 526 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
borlanic 0:02dd72d1d465 527 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
borlanic 0:02dd72d1d465 528
borlanic 0:02dd72d1d465 529 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
borlanic 0:02dd72d1d465 530 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
borlanic 0:02dd72d1d465 531
borlanic 0:02dd72d1d465 532 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
borlanic 0:02dd72d1d465 533 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
borlanic 0:02dd72d1d465 534 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
borlanic 0:02dd72d1d465 535
borlanic 0:02dd72d1d465 536 /* CP15 Register DFSR */
borlanic 0:02dd72d1d465 537 typedef union
borlanic 0:02dd72d1d465 538 {
borlanic 0:02dd72d1d465 539 struct
borlanic 0:02dd72d1d465 540 {
borlanic 0:02dd72d1d465 541 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
borlanic 0:02dd72d1d465 542 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
borlanic 0:02dd72d1d465 543 RESERVED(0:1, uint32_t)
borlanic 0:02dd72d1d465 544 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
borlanic 0:02dd72d1d465 545 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
borlanic 0:02dd72d1d465 546 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
borlanic 0:02dd72d1d465 547 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
borlanic 0:02dd72d1d465 548 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
borlanic 0:02dd72d1d465 549 RESERVED(1:18, uint32_t)
borlanic 0:02dd72d1d465 550 } s; /*!< \brief Structure used for bit access in short format */
borlanic 0:02dd72d1d465 551 struct
borlanic 0:02dd72d1d465 552 {
borlanic 0:02dd72d1d465 553 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
borlanic 0:02dd72d1d465 554 RESERVED(0:3, uint32_t)
borlanic 0:02dd72d1d465 555 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
borlanic 0:02dd72d1d465 556 RESERVED(1:1, uint32_t)
borlanic 0:02dd72d1d465 557 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
borlanic 0:02dd72d1d465 558 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
borlanic 0:02dd72d1d465 559 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
borlanic 0:02dd72d1d465 560 RESERVED(2:18, uint32_t)
borlanic 0:02dd72d1d465 561 } l; /*!< \brief Structure used for bit access in long format */
borlanic 0:02dd72d1d465 562 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 563 } DFSR_Type;
borlanic 0:02dd72d1d465 564
borlanic 0:02dd72d1d465 565 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
borlanic 0:02dd72d1d465 566 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
borlanic 0:02dd72d1d465 567
borlanic 0:02dd72d1d465 568 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
borlanic 0:02dd72d1d465 569 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
borlanic 0:02dd72d1d465 570
borlanic 0:02dd72d1d465 571 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
borlanic 0:02dd72d1d465 572 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
borlanic 0:02dd72d1d465 573
borlanic 0:02dd72d1d465 574 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
borlanic 0:02dd72d1d465 575 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
borlanic 0:02dd72d1d465 576
borlanic 0:02dd72d1d465 577 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
borlanic 0:02dd72d1d465 578 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
borlanic 0:02dd72d1d465 579
borlanic 0:02dd72d1d465 580 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
borlanic 0:02dd72d1d465 581 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
borlanic 0:02dd72d1d465 582
borlanic 0:02dd72d1d465 583 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
borlanic 0:02dd72d1d465 584 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
borlanic 0:02dd72d1d465 585
borlanic 0:02dd72d1d465 586 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
borlanic 0:02dd72d1d465 587 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
borlanic 0:02dd72d1d465 588
borlanic 0:02dd72d1d465 589 /* CP15 Register IFSR */
borlanic 0:02dd72d1d465 590 typedef union
borlanic 0:02dd72d1d465 591 {
borlanic 0:02dd72d1d465 592 struct
borlanic 0:02dd72d1d465 593 {
borlanic 0:02dd72d1d465 594 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
borlanic 0:02dd72d1d465 595 RESERVED(0:5, uint32_t)
borlanic 0:02dd72d1d465 596 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
borlanic 0:02dd72d1d465 597 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
borlanic 0:02dd72d1d465 598 RESERVED(1:1, uint32_t)
borlanic 0:02dd72d1d465 599 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
borlanic 0:02dd72d1d465 600 RESERVED(2:19, uint32_t)
borlanic 0:02dd72d1d465 601 } s; /*!< \brief Structure used for bit access in short format */
borlanic 0:02dd72d1d465 602 struct
borlanic 0:02dd72d1d465 603 {
borlanic 0:02dd72d1d465 604 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
borlanic 0:02dd72d1d465 605 RESERVED(0:3, uint32_t)
borlanic 0:02dd72d1d465 606 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
borlanic 0:02dd72d1d465 607 RESERVED(1:2, uint32_t)
borlanic 0:02dd72d1d465 608 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
borlanic 0:02dd72d1d465 609 RESERVED(2:19, uint32_t)
borlanic 0:02dd72d1d465 610 } l; /*!< \brief Structure used for bit access in long format */
borlanic 0:02dd72d1d465 611 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 612 } IFSR_Type;
borlanic 0:02dd72d1d465 613
borlanic 0:02dd72d1d465 614 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
borlanic 0:02dd72d1d465 615 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
borlanic 0:02dd72d1d465 616
borlanic 0:02dd72d1d465 617 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
borlanic 0:02dd72d1d465 618 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
borlanic 0:02dd72d1d465 619
borlanic 0:02dd72d1d465 620 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
borlanic 0:02dd72d1d465 621 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
borlanic 0:02dd72d1d465 622
borlanic 0:02dd72d1d465 623 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
borlanic 0:02dd72d1d465 624 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
borlanic 0:02dd72d1d465 625
borlanic 0:02dd72d1d465 626 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
borlanic 0:02dd72d1d465 627 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
borlanic 0:02dd72d1d465 628
borlanic 0:02dd72d1d465 629 /* CP15 Register ISR */
borlanic 0:02dd72d1d465 630 typedef union
borlanic 0:02dd72d1d465 631 {
borlanic 0:02dd72d1d465 632 struct
borlanic 0:02dd72d1d465 633 {
borlanic 0:02dd72d1d465 634 RESERVED(0:6, uint32_t)
borlanic 0:02dd72d1d465 635 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
borlanic 0:02dd72d1d465 636 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
borlanic 0:02dd72d1d465 637 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
borlanic 0:02dd72d1d465 638 RESERVED(1:23, uint32_t)
borlanic 0:02dd72d1d465 639 } b; /*!< \brief Structure used for bit access */
borlanic 0:02dd72d1d465 640 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 641 } ISR_Type;
borlanic 0:02dd72d1d465 642
borlanic 0:02dd72d1d465 643 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
borlanic 0:02dd72d1d465 644 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
borlanic 0:02dd72d1d465 645
borlanic 0:02dd72d1d465 646 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
borlanic 0:02dd72d1d465 647 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
borlanic 0:02dd72d1d465 648
borlanic 0:02dd72d1d465 649 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
borlanic 0:02dd72d1d465 650 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
borlanic 0:02dd72d1d465 651
borlanic 0:02dd72d1d465 652 /* DACR Register */
borlanic 0:02dd72d1d465 653 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
borlanic 0:02dd72d1d465 654 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
borlanic 0:02dd72d1d465 655 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
borlanic 0:02dd72d1d465 656 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
borlanic 0:02dd72d1d465 657 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
borlanic 0:02dd72d1d465 658
borlanic 0:02dd72d1d465 659 /**
borlanic 0:02dd72d1d465 660 \brief Mask and shift a bit field value for use in a register bit range.
borlanic 0:02dd72d1d465 661 \param [in] field Name of the register bit field.
borlanic 0:02dd72d1d465 662 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
borlanic 0:02dd72d1d465 663 \return Masked and shifted value.
borlanic 0:02dd72d1d465 664 */
borlanic 0:02dd72d1d465 665 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
borlanic 0:02dd72d1d465 666
borlanic 0:02dd72d1d465 667 /**
borlanic 0:02dd72d1d465 668 \brief Mask and shift a register value to extract a bit filed value.
borlanic 0:02dd72d1d465 669 \param [in] field Name of the register bit field.
borlanic 0:02dd72d1d465 670 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
borlanic 0:02dd72d1d465 671 \return Masked and shifted bit field value.
borlanic 0:02dd72d1d465 672 */
borlanic 0:02dd72d1d465 673 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
borlanic 0:02dd72d1d465 674
borlanic 0:02dd72d1d465 675
borlanic 0:02dd72d1d465 676 /**
borlanic 0:02dd72d1d465 677 \brief Union type to access the L2C_310 Cache Controller.
borlanic 0:02dd72d1d465 678 */
borlanic 0:02dd72d1d465 679 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 680 typedef struct
borlanic 0:02dd72d1d465 681 {
borlanic 0:02dd72d1d465 682 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
borlanic 0:02dd72d1d465 683 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
borlanic 0:02dd72d1d465 684 RESERVED(0[0x3e], uint32_t)
borlanic 0:02dd72d1d465 685 __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
borlanic 0:02dd72d1d465 686 __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
borlanic 0:02dd72d1d465 687 RESERVED(1[0x3e], uint32_t)
borlanic 0:02dd72d1d465 688 __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
borlanic 0:02dd72d1d465 689 __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
borlanic 0:02dd72d1d465 690 __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
borlanic 0:02dd72d1d465 691 RESERVED(2[0x2], uint32_t)
borlanic 0:02dd72d1d465 692 __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
borlanic 0:02dd72d1d465 693 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
borlanic 0:02dd72d1d465 694 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
borlanic 0:02dd72d1d465 695 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
borlanic 0:02dd72d1d465 696 RESERVED(3[0x143], uint32_t)
borlanic 0:02dd72d1d465 697 __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
borlanic 0:02dd72d1d465 698 RESERVED(4[0xf], uint32_t)
borlanic 0:02dd72d1d465 699 __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
borlanic 0:02dd72d1d465 700 RESERVED(6[2], uint32_t)
borlanic 0:02dd72d1d465 701 __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
borlanic 0:02dd72d1d465 702 RESERVED(5[0xc], uint32_t)
borlanic 0:02dd72d1d465 703 __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
borlanic 0:02dd72d1d465 704 RESERVED(7[1], uint32_t)
borlanic 0:02dd72d1d465 705 __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
borlanic 0:02dd72d1d465 706 __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
borlanic 0:02dd72d1d465 707 RESERVED(8[0xc], uint32_t)
borlanic 0:02dd72d1d465 708 __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
borlanic 0:02dd72d1d465 709 RESERVED(9[1], uint32_t)
borlanic 0:02dd72d1d465 710 __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
borlanic 0:02dd72d1d465 711 __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
borlanic 0:02dd72d1d465 712 RESERVED(10[0x40], uint32_t)
borlanic 0:02dd72d1d465 713 __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
borlanic 0:02dd72d1d465 714 __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
borlanic 0:02dd72d1d465 715 __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
borlanic 0:02dd72d1d465 716 __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
borlanic 0:02dd72d1d465 717 __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
borlanic 0:02dd72d1d465 718 __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
borlanic 0:02dd72d1d465 719 __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
borlanic 0:02dd72d1d465 720 __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
borlanic 0:02dd72d1d465 721 __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
borlanic 0:02dd72d1d465 722 __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
borlanic 0:02dd72d1d465 723 __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
borlanic 0:02dd72d1d465 724 __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
borlanic 0:02dd72d1d465 725 __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
borlanic 0:02dd72d1d465 726 __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
borlanic 0:02dd72d1d465 727 __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
borlanic 0:02dd72d1d465 728 __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
borlanic 0:02dd72d1d465 729 RESERVED(11[0x4], uint32_t)
borlanic 0:02dd72d1d465 730 __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
borlanic 0:02dd72d1d465 731 __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
borlanic 0:02dd72d1d465 732 RESERVED(12[0xaa], uint32_t)
borlanic 0:02dd72d1d465 733 __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
borlanic 0:02dd72d1d465 734 __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
borlanic 0:02dd72d1d465 735 RESERVED(13[0xce], uint32_t)
borlanic 0:02dd72d1d465 736 __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
borlanic 0:02dd72d1d465 737 } L2C_310_TypeDef;
borlanic 0:02dd72d1d465 738
borlanic 0:02dd72d1d465 739 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
borlanic 0:02dd72d1d465 740 #endif
borlanic 0:02dd72d1d465 741
borlanic 0:02dd72d1d465 742 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 743
borlanic 0:02dd72d1d465 744 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
borlanic 0:02dd72d1d465 745 */
borlanic 0:02dd72d1d465 746 typedef struct
borlanic 0:02dd72d1d465 747 {
borlanic 0:02dd72d1d465 748 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
borlanic 0:02dd72d1d465 749 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
borlanic 0:02dd72d1d465 750 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
borlanic 0:02dd72d1d465 751 RESERVED(0, uint32_t)
borlanic 0:02dd72d1d465 752 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
borlanic 0:02dd72d1d465 753 RESERVED(1[11], uint32_t)
borlanic 0:02dd72d1d465 754 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
borlanic 0:02dd72d1d465 755 RESERVED(2, uint32_t)
borlanic 0:02dd72d1d465 756 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
borlanic 0:02dd72d1d465 757 RESERVED(3, uint32_t)
borlanic 0:02dd72d1d465 758 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
borlanic 0:02dd72d1d465 759 RESERVED(4, uint32_t)
borlanic 0:02dd72d1d465 760 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
borlanic 0:02dd72d1d465 761 RESERVED(5[9], uint32_t)
borlanic 0:02dd72d1d465 762 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
borlanic 0:02dd72d1d465 763 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
borlanic 0:02dd72d1d465 764 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
borlanic 0:02dd72d1d465 765 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
borlanic 0:02dd72d1d465 766 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
borlanic 0:02dd72d1d465 767 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
borlanic 0:02dd72d1d465 768 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
borlanic 0:02dd72d1d465 769 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
borlanic 0:02dd72d1d465 770 RESERVED(6, uint32_t)
borlanic 0:02dd72d1d465 771 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
borlanic 0:02dd72d1d465 772 RESERVED(7, uint32_t)
borlanic 0:02dd72d1d465 773 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
borlanic 0:02dd72d1d465 774 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
borlanic 0:02dd72d1d465 775 RESERVED(8[32], uint32_t)
borlanic 0:02dd72d1d465 776 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
borlanic 0:02dd72d1d465 777 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
borlanic 0:02dd72d1d465 778 RESERVED(9[3], uint32_t)
borlanic 0:02dd72d1d465 779 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
borlanic 0:02dd72d1d465 780 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
borlanic 0:02dd72d1d465 781 RESERVED(10[5236], uint32_t)
borlanic 0:02dd72d1d465 782 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
borlanic 0:02dd72d1d465 783 } GICDistributor_Type;
borlanic 0:02dd72d1d465 784
borlanic 0:02dd72d1d465 785 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
borlanic 0:02dd72d1d465 786
borlanic 0:02dd72d1d465 787 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
borlanic 0:02dd72d1d465 788 */
borlanic 0:02dd72d1d465 789 typedef struct
borlanic 0:02dd72d1d465 790 {
borlanic 0:02dd72d1d465 791 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
borlanic 0:02dd72d1d465 792 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
borlanic 0:02dd72d1d465 793 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
borlanic 0:02dd72d1d465 794 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
borlanic 0:02dd72d1d465 795 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
borlanic 0:02dd72d1d465 796 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
borlanic 0:02dd72d1d465 797 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
borlanic 0:02dd72d1d465 798 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
borlanic 0:02dd72d1d465 799 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
borlanic 0:02dd72d1d465 800 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
borlanic 0:02dd72d1d465 801 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
borlanic 0:02dd72d1d465 802 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
borlanic 0:02dd72d1d465 803 RESERVED(1[40], uint32_t)
borlanic 0:02dd72d1d465 804 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
borlanic 0:02dd72d1d465 805 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
borlanic 0:02dd72d1d465 806 RESERVED(2[3], uint32_t)
borlanic 0:02dd72d1d465 807 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
borlanic 0:02dd72d1d465 808 RESERVED(3[960], uint32_t)
borlanic 0:02dd72d1d465 809 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
borlanic 0:02dd72d1d465 810 } GICInterface_Type;
borlanic 0:02dd72d1d465 811
borlanic 0:02dd72d1d465 812 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
borlanic 0:02dd72d1d465 813 #endif
borlanic 0:02dd72d1d465 814
borlanic 0:02dd72d1d465 815 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 816 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 817 /** \brief Structure type to access the Private Timer
borlanic 0:02dd72d1d465 818 */
borlanic 0:02dd72d1d465 819 typedef struct
borlanic 0:02dd72d1d465 820 {
borlanic 0:02dd72d1d465 821 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
borlanic 0:02dd72d1d465 822 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
borlanic 0:02dd72d1d465 823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
borlanic 0:02dd72d1d465 824 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
borlanic 0:02dd72d1d465 825 RESERVED(0[4], uint32_t)
borlanic 0:02dd72d1d465 826 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
borlanic 0:02dd72d1d465 827 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
borlanic 0:02dd72d1d465 828 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
borlanic 0:02dd72d1d465 829 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
borlanic 0:02dd72d1d465 830 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
borlanic 0:02dd72d1d465 831 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
borlanic 0:02dd72d1d465 832 } Timer_Type;
borlanic 0:02dd72d1d465 833 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
borlanic 0:02dd72d1d465 834 #endif
borlanic 0:02dd72d1d465 835 #endif
borlanic 0:02dd72d1d465 836
borlanic 0:02dd72d1d465 837 /*******************************************************************************
borlanic 0:02dd72d1d465 838 * Hardware Abstraction Layer
borlanic 0:02dd72d1d465 839 Core Function Interface contains:
borlanic 0:02dd72d1d465 840 - L1 Cache Functions
borlanic 0:02dd72d1d465 841 - L2C-310 Cache Controller Functions
borlanic 0:02dd72d1d465 842 - PL1 Timer Functions
borlanic 0:02dd72d1d465 843 - GIC Functions
borlanic 0:02dd72d1d465 844 - MMU Functions
borlanic 0:02dd72d1d465 845 ******************************************************************************/
borlanic 0:02dd72d1d465 846
borlanic 0:02dd72d1d465 847 /* ########################## L1 Cache functions ################################# */
borlanic 0:02dd72d1d465 848
borlanic 0:02dd72d1d465 849 /** \brief Enable Caches by setting I and C bits in SCTLR register.
borlanic 0:02dd72d1d465 850 */
borlanic 0:02dd72d1d465 851 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
borlanic 0:02dd72d1d465 852 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
borlanic 0:02dd72d1d465 853 __ISB();
borlanic 0:02dd72d1d465 854 }
borlanic 0:02dd72d1d465 855
borlanic 0:02dd72d1d465 856 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
borlanic 0:02dd72d1d465 857 */
borlanic 0:02dd72d1d465 858 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
borlanic 0:02dd72d1d465 859 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
borlanic 0:02dd72d1d465 860 __ISB();
borlanic 0:02dd72d1d465 861 }
borlanic 0:02dd72d1d465 862
borlanic 0:02dd72d1d465 863 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
borlanic 0:02dd72d1d465 864 */
borlanic 0:02dd72d1d465 865 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
borlanic 0:02dd72d1d465 866 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
borlanic 0:02dd72d1d465 867 __ISB();
borlanic 0:02dd72d1d465 868 }
borlanic 0:02dd72d1d465 869
borlanic 0:02dd72d1d465 870 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
borlanic 0:02dd72d1d465 871 */
borlanic 0:02dd72d1d465 872 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
borlanic 0:02dd72d1d465 873 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
borlanic 0:02dd72d1d465 874 __ISB();
borlanic 0:02dd72d1d465 875 }
borlanic 0:02dd72d1d465 876
borlanic 0:02dd72d1d465 877 /** \brief Invalidate entire branch predictor array
borlanic 0:02dd72d1d465 878 */
borlanic 0:02dd72d1d465 879 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
borlanic 0:02dd72d1d465 880 __set_BPIALL(0);
borlanic 0:02dd72d1d465 881 __DSB(); //ensure completion of the invalidation
borlanic 0:02dd72d1d465 882 __ISB(); //ensure instruction fetch path sees new state
borlanic 0:02dd72d1d465 883 }
borlanic 0:02dd72d1d465 884
borlanic 0:02dd72d1d465 885 /** \brief Invalidate the whole instruction cache
borlanic 0:02dd72d1d465 886 */
borlanic 0:02dd72d1d465 887 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
borlanic 0:02dd72d1d465 888 __set_ICIALLU(0);
borlanic 0:02dd72d1d465 889 __DSB(); //ensure completion of the invalidation
borlanic 0:02dd72d1d465 890 __ISB(); //ensure instruction fetch path sees new I cache state
borlanic 0:02dd72d1d465 891 }
borlanic 0:02dd72d1d465 892
borlanic 0:02dd72d1d465 893 /** \brief Clean data cache line by address.
borlanic 0:02dd72d1d465 894 * \param [in] va Pointer to data to clear the cache for.
borlanic 0:02dd72d1d465 895 */
borlanic 0:02dd72d1d465 896 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
borlanic 0:02dd72d1d465 897 __set_DCCMVAC((uint32_t)va);
borlanic 0:02dd72d1d465 898 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
borlanic 0:02dd72d1d465 899 }
borlanic 0:02dd72d1d465 900
borlanic 0:02dd72d1d465 901 /** \brief Invalidate data cache line by address.
borlanic 0:02dd72d1d465 902 * \param [in] va Pointer to data to invalidate the cache for.
borlanic 0:02dd72d1d465 903 */
borlanic 0:02dd72d1d465 904 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
borlanic 0:02dd72d1d465 905 __set_DCIMVAC((uint32_t)va);
borlanic 0:02dd72d1d465 906 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
borlanic 0:02dd72d1d465 907 }
borlanic 0:02dd72d1d465 908
borlanic 0:02dd72d1d465 909 /** \brief Clean and Invalidate data cache by address.
borlanic 0:02dd72d1d465 910 * \param [in] va Pointer to data to invalidate the cache for.
borlanic 0:02dd72d1d465 911 */
borlanic 0:02dd72d1d465 912 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
borlanic 0:02dd72d1d465 913 __set_DCCIMVAC((uint32_t)va);
borlanic 0:02dd72d1d465 914 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
borlanic 0:02dd72d1d465 915 }
borlanic 0:02dd72d1d465 916
borlanic 0:02dd72d1d465 917 /** \brief Calculate log2 rounded up
borlanic 0:02dd72d1d465 918 * - log(0) => 0
borlanic 0:02dd72d1d465 919 * - log(1) => 0
borlanic 0:02dd72d1d465 920 * - log(2) => 1
borlanic 0:02dd72d1d465 921 * - log(3) => 2
borlanic 0:02dd72d1d465 922 * - log(4) => 2
borlanic 0:02dd72d1d465 923 * - log(5) => 3
borlanic 0:02dd72d1d465 924 * : :
borlanic 0:02dd72d1d465 925 * - log(16) => 4
borlanic 0:02dd72d1d465 926 * - log(32) => 5
borlanic 0:02dd72d1d465 927 * : :
borlanic 0:02dd72d1d465 928 * \param [in] n input value parameter
borlanic 0:02dd72d1d465 929 * \return log2(n)
borlanic 0:02dd72d1d465 930 */
borlanic 0:02dd72d1d465 931 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
borlanic 0:02dd72d1d465 932 {
borlanic 0:02dd72d1d465 933 if (n < 2U) {
borlanic 0:02dd72d1d465 934 return 0U;
borlanic 0:02dd72d1d465 935 }
borlanic 0:02dd72d1d465 936 uint8_t log = 0U;
borlanic 0:02dd72d1d465 937 uint32_t t = n;
borlanic 0:02dd72d1d465 938 while(t > 1U)
borlanic 0:02dd72d1d465 939 {
borlanic 0:02dd72d1d465 940 log++;
borlanic 0:02dd72d1d465 941 t >>= 1U;
borlanic 0:02dd72d1d465 942 }
borlanic 0:02dd72d1d465 943 if (n & 1U) { log++; }
borlanic 0:02dd72d1d465 944 return log;
borlanic 0:02dd72d1d465 945 }
borlanic 0:02dd72d1d465 946
borlanic 0:02dd72d1d465 947 /** \brief Apply cache maintenance to given cache level.
borlanic 0:02dd72d1d465 948 * \param [in] level cache level to be maintained
borlanic 0:02dd72d1d465 949 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
borlanic 0:02dd72d1d465 950 */
borlanic 0:02dd72d1d465 951 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
borlanic 0:02dd72d1d465 952 {
borlanic 0:02dd72d1d465 953 register volatile uint32_t Dummy;
borlanic 0:02dd72d1d465 954 register volatile uint32_t ccsidr;
borlanic 0:02dd72d1d465 955 uint32_t num_sets;
borlanic 0:02dd72d1d465 956 uint32_t num_ways;
borlanic 0:02dd72d1d465 957 uint32_t shift_way;
borlanic 0:02dd72d1d465 958 uint32_t log2_linesize;
borlanic 0:02dd72d1d465 959 int32_t log2_num_ways;
borlanic 0:02dd72d1d465 960
borlanic 0:02dd72d1d465 961 Dummy = level << 1U;
borlanic 0:02dd72d1d465 962 /* set csselr, select ccsidr register */
borlanic 0:02dd72d1d465 963 __set_CCSIDR(Dummy);
borlanic 0:02dd72d1d465 964 /* get current ccsidr register */
borlanic 0:02dd72d1d465 965 ccsidr = __get_CCSIDR();
borlanic 0:02dd72d1d465 966 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
borlanic 0:02dd72d1d465 967 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
borlanic 0:02dd72d1d465 968 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
borlanic 0:02dd72d1d465 969 log2_num_ways = __log2_up(num_ways);
borlanic 0:02dd72d1d465 970 if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
borlanic 0:02dd72d1d465 971 return; // FATAL ERROR
borlanic 0:02dd72d1d465 972 }
borlanic 0:02dd72d1d465 973 shift_way = 32U - (uint32_t)log2_num_ways;
borlanic 0:02dd72d1d465 974 for(int32_t way = num_ways-1; way >= 0; way--)
borlanic 0:02dd72d1d465 975 {
borlanic 0:02dd72d1d465 976 for(int32_t set = num_sets-1; set >= 0; set--)
borlanic 0:02dd72d1d465 977 {
borlanic 0:02dd72d1d465 978 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
borlanic 0:02dd72d1d465 979 switch (maint)
borlanic 0:02dd72d1d465 980 {
borlanic 0:02dd72d1d465 981 case 0U: __set_DCISW(Dummy); break;
borlanic 0:02dd72d1d465 982 case 1U: __set_DCCSW(Dummy); break;
borlanic 0:02dd72d1d465 983 default: __set_DCCISW(Dummy); break;
borlanic 0:02dd72d1d465 984 }
borlanic 0:02dd72d1d465 985 }
borlanic 0:02dd72d1d465 986 }
borlanic 0:02dd72d1d465 987 __DMB();
borlanic 0:02dd72d1d465 988 }
borlanic 0:02dd72d1d465 989
borlanic 0:02dd72d1d465 990 /** \brief Clean and Invalidate the entire data or unified cache
borlanic 0:02dd72d1d465 991 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
borlanic 0:02dd72d1d465 992 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
borlanic 0:02dd72d1d465 993 */
borlanic 0:02dd72d1d465 994 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
borlanic 0:02dd72d1d465 995 register volatile uint32_t clidr;
borlanic 0:02dd72d1d465 996 uint32_t cache_type;
borlanic 0:02dd72d1d465 997 clidr = __get_CLIDR();
borlanic 0:02dd72d1d465 998 for(uint32_t i = 0U; i<7U; i++)
borlanic 0:02dd72d1d465 999 {
borlanic 0:02dd72d1d465 1000 cache_type = (clidr >> i*3U) & 0x7UL;
borlanic 0:02dd72d1d465 1001 if ((cache_type >= 2U) && (cache_type <= 4U))
borlanic 0:02dd72d1d465 1002 {
borlanic 0:02dd72d1d465 1003 __L1C_MaintainDCacheSetWay(i, op);
borlanic 0:02dd72d1d465 1004 }
borlanic 0:02dd72d1d465 1005 }
borlanic 0:02dd72d1d465 1006 }
borlanic 0:02dd72d1d465 1007
borlanic 0:02dd72d1d465 1008 /** \brief Clean and Invalidate the entire data or unified cache
borlanic 0:02dd72d1d465 1009 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
borlanic 0:02dd72d1d465 1010 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
borlanic 0:02dd72d1d465 1011 * \deprecated Use generic L1C_CleanInvalidateCache instead.
borlanic 0:02dd72d1d465 1012 */
borlanic 0:02dd72d1d465 1013 CMSIS_DEPRECATED
borlanic 0:02dd72d1d465 1014 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
borlanic 0:02dd72d1d465 1015 L1C_CleanInvalidateCache(op);
borlanic 0:02dd72d1d465 1016 }
borlanic 0:02dd72d1d465 1017
borlanic 0:02dd72d1d465 1018 /** \brief Invalidate the whole data cache.
borlanic 0:02dd72d1d465 1019 */
borlanic 0:02dd72d1d465 1020 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
borlanic 0:02dd72d1d465 1021 L1C_CleanInvalidateCache(0);
borlanic 0:02dd72d1d465 1022 }
borlanic 0:02dd72d1d465 1023
borlanic 0:02dd72d1d465 1024 /** \brief Clean the whole data cache.
borlanic 0:02dd72d1d465 1025 */
borlanic 0:02dd72d1d465 1026 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
borlanic 0:02dd72d1d465 1027 L1C_CleanInvalidateCache(1);
borlanic 0:02dd72d1d465 1028 }
borlanic 0:02dd72d1d465 1029
borlanic 0:02dd72d1d465 1030 /** \brief Clean and invalidate the whole data cache.
borlanic 0:02dd72d1d465 1031 */
borlanic 0:02dd72d1d465 1032 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
borlanic 0:02dd72d1d465 1033 L1C_CleanInvalidateCache(2);
borlanic 0:02dd72d1d465 1034 }
borlanic 0:02dd72d1d465 1035
borlanic 0:02dd72d1d465 1036 /* ########################## L2 Cache functions ################################# */
borlanic 0:02dd72d1d465 1037 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 1038 /** \brief Cache Sync operation by writing CACHE_SYNC register.
borlanic 0:02dd72d1d465 1039 */
borlanic 0:02dd72d1d465 1040 __STATIC_INLINE void L2C_Sync(void)
borlanic 0:02dd72d1d465 1041 {
borlanic 0:02dd72d1d465 1042 L2C_310->CACHE_SYNC = 0x0;
borlanic 0:02dd72d1d465 1043 }
borlanic 0:02dd72d1d465 1044
borlanic 0:02dd72d1d465 1045 /** \brief Read cache controller cache ID from CACHE_ID register.
borlanic 0:02dd72d1d465 1046 * \return L2C_310_TypeDef::CACHE_ID
borlanic 0:02dd72d1d465 1047 */
borlanic 0:02dd72d1d465 1048 __STATIC_INLINE int L2C_GetID (void)
borlanic 0:02dd72d1d465 1049 {
borlanic 0:02dd72d1d465 1050 return L2C_310->CACHE_ID;
borlanic 0:02dd72d1d465 1051 }
borlanic 0:02dd72d1d465 1052
borlanic 0:02dd72d1d465 1053 /** \brief Read cache controller cache type from CACHE_TYPE register.
borlanic 0:02dd72d1d465 1054 * \return L2C_310_TypeDef::CACHE_TYPE
borlanic 0:02dd72d1d465 1055 */
borlanic 0:02dd72d1d465 1056 __STATIC_INLINE int L2C_GetType (void)
borlanic 0:02dd72d1d465 1057 {
borlanic 0:02dd72d1d465 1058 return L2C_310->CACHE_TYPE;
borlanic 0:02dd72d1d465 1059 }
borlanic 0:02dd72d1d465 1060
borlanic 0:02dd72d1d465 1061 /** \brief Invalidate all cache by way
borlanic 0:02dd72d1d465 1062 */
borlanic 0:02dd72d1d465 1063 __STATIC_INLINE void L2C_InvAllByWay (void)
borlanic 0:02dd72d1d465 1064 {
borlanic 0:02dd72d1d465 1065 unsigned int assoc;
borlanic 0:02dd72d1d465 1066
borlanic 0:02dd72d1d465 1067 if (L2C_310->AUX_CNT & (1U << 16U)) {
borlanic 0:02dd72d1d465 1068 assoc = 16U;
borlanic 0:02dd72d1d465 1069 } else {
borlanic 0:02dd72d1d465 1070 assoc = 8U;
borlanic 0:02dd72d1d465 1071 }
borlanic 0:02dd72d1d465 1072
borlanic 0:02dd72d1d465 1073 L2C_310->INV_WAY = (1U << assoc) - 1U;
borlanic 0:02dd72d1d465 1074 while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
borlanic 0:02dd72d1d465 1075
borlanic 0:02dd72d1d465 1076 L2C_Sync();
borlanic 0:02dd72d1d465 1077 }
borlanic 0:02dd72d1d465 1078
borlanic 0:02dd72d1d465 1079 /** \brief Clean and Invalidate all cache by way
borlanic 0:02dd72d1d465 1080 */
borlanic 0:02dd72d1d465 1081 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
borlanic 0:02dd72d1d465 1082 {
borlanic 0:02dd72d1d465 1083 unsigned int assoc;
borlanic 0:02dd72d1d465 1084
borlanic 0:02dd72d1d465 1085 if (L2C_310->AUX_CNT & (1U << 16U)) {
borlanic 0:02dd72d1d465 1086 assoc = 16U;
borlanic 0:02dd72d1d465 1087 } else {
borlanic 0:02dd72d1d465 1088 assoc = 8U;
borlanic 0:02dd72d1d465 1089 }
borlanic 0:02dd72d1d465 1090
borlanic 0:02dd72d1d465 1091 L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
borlanic 0:02dd72d1d465 1092 while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
borlanic 0:02dd72d1d465 1093
borlanic 0:02dd72d1d465 1094 L2C_Sync();
borlanic 0:02dd72d1d465 1095 }
borlanic 0:02dd72d1d465 1096
borlanic 0:02dd72d1d465 1097 /** \brief Enable Level 2 Cache
borlanic 0:02dd72d1d465 1098 */
borlanic 0:02dd72d1d465 1099 __STATIC_INLINE void L2C_Enable(void)
borlanic 0:02dd72d1d465 1100 {
borlanic 0:02dd72d1d465 1101 L2C_310->CONTROL = 0;
borlanic 0:02dd72d1d465 1102 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
borlanic 0:02dd72d1d465 1103 L2C_310->DEBUG_CONTROL = 0;
borlanic 0:02dd72d1d465 1104 L2C_310->DATA_LOCK_0_WAY = 0;
borlanic 0:02dd72d1d465 1105 L2C_310->CACHE_SYNC = 0;
borlanic 0:02dd72d1d465 1106 L2C_310->CONTROL = 0x01;
borlanic 0:02dd72d1d465 1107 L2C_Sync();
borlanic 0:02dd72d1d465 1108 }
borlanic 0:02dd72d1d465 1109
borlanic 0:02dd72d1d465 1110 /** \brief Disable Level 2 Cache
borlanic 0:02dd72d1d465 1111 */
borlanic 0:02dd72d1d465 1112 __STATIC_INLINE void L2C_Disable(void)
borlanic 0:02dd72d1d465 1113 {
borlanic 0:02dd72d1d465 1114 L2C_310->CONTROL = 0x00;
borlanic 0:02dd72d1d465 1115 L2C_Sync();
borlanic 0:02dd72d1d465 1116 }
borlanic 0:02dd72d1d465 1117
borlanic 0:02dd72d1d465 1118 /** \brief Invalidate cache by physical address
borlanic 0:02dd72d1d465 1119 * \param [in] pa Pointer to data to invalidate cache for.
borlanic 0:02dd72d1d465 1120 */
borlanic 0:02dd72d1d465 1121 __STATIC_INLINE void L2C_InvPa (void *pa)
borlanic 0:02dd72d1d465 1122 {
borlanic 0:02dd72d1d465 1123 L2C_310->INV_LINE_PA = (unsigned int)pa;
borlanic 0:02dd72d1d465 1124 L2C_Sync();
borlanic 0:02dd72d1d465 1125 }
borlanic 0:02dd72d1d465 1126
borlanic 0:02dd72d1d465 1127 /** \brief Clean cache by physical address
borlanic 0:02dd72d1d465 1128 * \param [in] pa Pointer to data to invalidate cache for.
borlanic 0:02dd72d1d465 1129 */
borlanic 0:02dd72d1d465 1130 __STATIC_INLINE void L2C_CleanPa (void *pa)
borlanic 0:02dd72d1d465 1131 {
borlanic 0:02dd72d1d465 1132 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
borlanic 0:02dd72d1d465 1133 L2C_Sync();
borlanic 0:02dd72d1d465 1134 }
borlanic 0:02dd72d1d465 1135
borlanic 0:02dd72d1d465 1136 /** \brief Clean and invalidate cache by physical address
borlanic 0:02dd72d1d465 1137 * \param [in] pa Pointer to data to invalidate cache for.
borlanic 0:02dd72d1d465 1138 */
borlanic 0:02dd72d1d465 1139 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
borlanic 0:02dd72d1d465 1140 {
borlanic 0:02dd72d1d465 1141 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
borlanic 0:02dd72d1d465 1142 L2C_Sync();
borlanic 0:02dd72d1d465 1143 }
borlanic 0:02dd72d1d465 1144 #endif
borlanic 0:02dd72d1d465 1145
borlanic 0:02dd72d1d465 1146 /* ########################## GIC functions ###################################### */
borlanic 0:02dd72d1d465 1147 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 1148
borlanic 0:02dd72d1d465 1149 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
borlanic 0:02dd72d1d465 1150 */
borlanic 0:02dd72d1d465 1151 __STATIC_INLINE void GIC_EnableDistributor(void)
borlanic 0:02dd72d1d465 1152 {
borlanic 0:02dd72d1d465 1153 GICDistributor->CTLR |= 1U;
borlanic 0:02dd72d1d465 1154 }
borlanic 0:02dd72d1d465 1155
borlanic 0:02dd72d1d465 1156 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
borlanic 0:02dd72d1d465 1157 */
borlanic 0:02dd72d1d465 1158 __STATIC_INLINE void GIC_DisableDistributor(void)
borlanic 0:02dd72d1d465 1159 {
borlanic 0:02dd72d1d465 1160 GICDistributor->CTLR &=~1U;
borlanic 0:02dd72d1d465 1161 }
borlanic 0:02dd72d1d465 1162
borlanic 0:02dd72d1d465 1163 /** \brief Read the GIC's TYPER register.
borlanic 0:02dd72d1d465 1164 * \return GICDistributor_Type::TYPER
borlanic 0:02dd72d1d465 1165 */
borlanic 0:02dd72d1d465 1166 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
borlanic 0:02dd72d1d465 1167 {
borlanic 0:02dd72d1d465 1168 return (GICDistributor->TYPER);
borlanic 0:02dd72d1d465 1169 }
borlanic 0:02dd72d1d465 1170
borlanic 0:02dd72d1d465 1171 /** \brief Reads the GIC's IIDR register.
borlanic 0:02dd72d1d465 1172 * \return GICDistributor_Type::IIDR
borlanic 0:02dd72d1d465 1173 */
borlanic 0:02dd72d1d465 1174 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
borlanic 0:02dd72d1d465 1175 {
borlanic 0:02dd72d1d465 1176 return (GICDistributor->IIDR);
borlanic 0:02dd72d1d465 1177 }
borlanic 0:02dd72d1d465 1178
borlanic 0:02dd72d1d465 1179 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
borlanic 0:02dd72d1d465 1180 * \param [in] IRQn Interrupt to be configured.
borlanic 0:02dd72d1d465 1181 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
borlanic 0:02dd72d1d465 1182 */
borlanic 0:02dd72d1d465 1183 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
borlanic 0:02dd72d1d465 1184 {
borlanic 0:02dd72d1d465 1185 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
borlanic 0:02dd72d1d465 1186 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
borlanic 0:02dd72d1d465 1187 }
borlanic 0:02dd72d1d465 1188
borlanic 0:02dd72d1d465 1189 /** \brief Read the GIC's ITARGETSR register.
borlanic 0:02dd72d1d465 1190 * \param [in] IRQn Interrupt to acquire the configuration for.
borlanic 0:02dd72d1d465 1191 * \return GICDistributor_Type::ITARGETSR
borlanic 0:02dd72d1d465 1192 */
borlanic 0:02dd72d1d465 1193 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1194 {
borlanic 0:02dd72d1d465 1195 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
borlanic 0:02dd72d1d465 1196 }
borlanic 0:02dd72d1d465 1197
borlanic 0:02dd72d1d465 1198 /** \brief Enable the CPU's interrupt interface.
borlanic 0:02dd72d1d465 1199 */
borlanic 0:02dd72d1d465 1200 __STATIC_INLINE void GIC_EnableInterface(void)
borlanic 0:02dd72d1d465 1201 {
borlanic 0:02dd72d1d465 1202 GICInterface->CTLR |= 1U; //enable interface
borlanic 0:02dd72d1d465 1203 }
borlanic 0:02dd72d1d465 1204
borlanic 0:02dd72d1d465 1205 /** \brief Disable the CPU's interrupt interface.
borlanic 0:02dd72d1d465 1206 */
borlanic 0:02dd72d1d465 1207 __STATIC_INLINE void GIC_DisableInterface(void)
borlanic 0:02dd72d1d465 1208 {
borlanic 0:02dd72d1d465 1209 GICInterface->CTLR &=~1U; //disable distributor
borlanic 0:02dd72d1d465 1210 }
borlanic 0:02dd72d1d465 1211
borlanic 0:02dd72d1d465 1212 /** \brief Read the CPU's IAR register.
borlanic 0:02dd72d1d465 1213 * \return GICInterface_Type::IAR
borlanic 0:02dd72d1d465 1214 */
borlanic 0:02dd72d1d465 1215 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
borlanic 0:02dd72d1d465 1216 {
borlanic 0:02dd72d1d465 1217 return (IRQn_Type)(GICInterface->IAR);
borlanic 0:02dd72d1d465 1218 }
borlanic 0:02dd72d1d465 1219
borlanic 0:02dd72d1d465 1220 /** \brief Writes the given interrupt number to the CPU's EOIR register.
borlanic 0:02dd72d1d465 1221 * \param [in] IRQn The interrupt to be signaled as finished.
borlanic 0:02dd72d1d465 1222 */
borlanic 0:02dd72d1d465 1223 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1224 {
borlanic 0:02dd72d1d465 1225 GICInterface->EOIR = IRQn;
borlanic 0:02dd72d1d465 1226 }
borlanic 0:02dd72d1d465 1227
borlanic 0:02dd72d1d465 1228 /** \brief Enables the given interrupt using GIC's ISENABLER register.
borlanic 0:02dd72d1d465 1229 * \param [in] IRQn The interrupt to be enabled.
borlanic 0:02dd72d1d465 1230 */
borlanic 0:02dd72d1d465 1231 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1232 {
borlanic 0:02dd72d1d465 1233 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
borlanic 0:02dd72d1d465 1234 }
borlanic 0:02dd72d1d465 1235
borlanic 0:02dd72d1d465 1236 /** \brief Get interrupt enable status using GIC's ISENABLER register.
borlanic 0:02dd72d1d465 1237 * \param [in] IRQn The interrupt to be queried.
borlanic 0:02dd72d1d465 1238 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
borlanic 0:02dd72d1d465 1239 */
borlanic 0:02dd72d1d465 1240 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1241 {
borlanic 0:02dd72d1d465 1242 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
borlanic 0:02dd72d1d465 1243 }
borlanic 0:02dd72d1d465 1244
borlanic 0:02dd72d1d465 1245 /** \brief Disables the given interrupt using GIC's ICENABLER register.
borlanic 0:02dd72d1d465 1246 * \param [in] IRQn The interrupt to be disabled.
borlanic 0:02dd72d1d465 1247 */
borlanic 0:02dd72d1d465 1248 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1249 {
borlanic 0:02dd72d1d465 1250 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
borlanic 0:02dd72d1d465 1251 }
borlanic 0:02dd72d1d465 1252
borlanic 0:02dd72d1d465 1253 /** \brief Get interrupt pending status from GIC's ISPENDR register.
borlanic 0:02dd72d1d465 1254 * \param [in] IRQn The interrupt to be queried.
borlanic 0:02dd72d1d465 1255 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
borlanic 0:02dd72d1d465 1256 */
borlanic 0:02dd72d1d465 1257 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1258 {
borlanic 0:02dd72d1d465 1259 uint32_t pend;
borlanic 0:02dd72d1d465 1260
borlanic 0:02dd72d1d465 1261 if (IRQn >= 16U) {
borlanic 0:02dd72d1d465 1262 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
borlanic 0:02dd72d1d465 1263 } else {
borlanic 0:02dd72d1d465 1264 // INTID 0-15 Software Generated Interrupt
borlanic 0:02dd72d1d465 1265 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
borlanic 0:02dd72d1d465 1266 // No CPU identification offered
borlanic 0:02dd72d1d465 1267 if (pend != 0U) {
borlanic 0:02dd72d1d465 1268 pend = 1U;
borlanic 0:02dd72d1d465 1269 } else {
borlanic 0:02dd72d1d465 1270 pend = 0U;
borlanic 0:02dd72d1d465 1271 }
borlanic 0:02dd72d1d465 1272 }
borlanic 0:02dd72d1d465 1273
borlanic 0:02dd72d1d465 1274 return (pend);
borlanic 0:02dd72d1d465 1275 }
borlanic 0:02dd72d1d465 1276
borlanic 0:02dd72d1d465 1277 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
borlanic 0:02dd72d1d465 1278 * \param [in] IRQn The interrupt to be enabled.
borlanic 0:02dd72d1d465 1279 */
borlanic 0:02dd72d1d465 1280 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1281 {
borlanic 0:02dd72d1d465 1282 if (IRQn >= 16U) {
borlanic 0:02dd72d1d465 1283 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
borlanic 0:02dd72d1d465 1284 } else {
borlanic 0:02dd72d1d465 1285 // INTID 0-15 Software Generated Interrupt
borlanic 0:02dd72d1d465 1286 GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
borlanic 0:02dd72d1d465 1287 // Forward the interrupt to the CPU interface that requested it
borlanic 0:02dd72d1d465 1288 GICDistributor->SGIR = (IRQn | 0x02000000U);
borlanic 0:02dd72d1d465 1289 }
borlanic 0:02dd72d1d465 1290 }
borlanic 0:02dd72d1d465 1291
borlanic 0:02dd72d1d465 1292 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
borlanic 0:02dd72d1d465 1293 * \param [in] IRQn The interrupt to be enabled.
borlanic 0:02dd72d1d465 1294 */
borlanic 0:02dd72d1d465 1295 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1296 {
borlanic 0:02dd72d1d465 1297 if (IRQn >= 16U) {
borlanic 0:02dd72d1d465 1298 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
borlanic 0:02dd72d1d465 1299 } else {
borlanic 0:02dd72d1d465 1300 // INTID 0-15 Software Generated Interrupt
borlanic 0:02dd72d1d465 1301 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
borlanic 0:02dd72d1d465 1302 }
borlanic 0:02dd72d1d465 1303 }
borlanic 0:02dd72d1d465 1304
borlanic 0:02dd72d1d465 1305 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
borlanic 0:02dd72d1d465 1306 * \param [in] IRQn The interrupt to be configured.
borlanic 0:02dd72d1d465 1307 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
borlanic 0:02dd72d1d465 1308 * Bit 1: 0 - level sensitive, 1 - edge triggered
borlanic 0:02dd72d1d465 1309 */
borlanic 0:02dd72d1d465 1310 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
borlanic 0:02dd72d1d465 1311 {
borlanic 0:02dd72d1d465 1312 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
borlanic 0:02dd72d1d465 1313 uint32_t shift = (IRQn % 16U) << 1U;
borlanic 0:02dd72d1d465 1314
borlanic 0:02dd72d1d465 1315 icfgr &= (~(3U << shift));
borlanic 0:02dd72d1d465 1316 icfgr |= ( int_config << shift);
borlanic 0:02dd72d1d465 1317
borlanic 0:02dd72d1d465 1318 GICDistributor->ICFGR[IRQn / 16U] = icfgr;
borlanic 0:02dd72d1d465 1319 }
borlanic 0:02dd72d1d465 1320
borlanic 0:02dd72d1d465 1321 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
borlanic 0:02dd72d1d465 1322 * \param [in] IRQn Interrupt to acquire the configuration for.
borlanic 0:02dd72d1d465 1323 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
borlanic 0:02dd72d1d465 1324 * Bit 1: 0 - level sensitive, 1 - edge triggered
borlanic 0:02dd72d1d465 1325 */
borlanic 0:02dd72d1d465 1326 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1327 {
borlanic 0:02dd72d1d465 1328 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
borlanic 0:02dd72d1d465 1329 }
borlanic 0:02dd72d1d465 1330
borlanic 0:02dd72d1d465 1331 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
borlanic 0:02dd72d1d465 1332 * \param [in] IRQn The interrupt to be configured.
borlanic 0:02dd72d1d465 1333 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
borlanic 0:02dd72d1d465 1334 */
borlanic 0:02dd72d1d465 1335 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
borlanic 0:02dd72d1d465 1336 {
borlanic 0:02dd72d1d465 1337 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
borlanic 0:02dd72d1d465 1338 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
borlanic 0:02dd72d1d465 1339 }
borlanic 0:02dd72d1d465 1340
borlanic 0:02dd72d1d465 1341 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
borlanic 0:02dd72d1d465 1342 * \param [in] IRQn The interrupt to be queried.
borlanic 0:02dd72d1d465 1343 */
borlanic 0:02dd72d1d465 1344 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1345 {
borlanic 0:02dd72d1d465 1346 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
borlanic 0:02dd72d1d465 1347 }
borlanic 0:02dd72d1d465 1348
borlanic 0:02dd72d1d465 1349 /** \brief Set the interrupt priority mask using CPU's PMR register.
borlanic 0:02dd72d1d465 1350 * \param [in] priority Priority mask to be set.
borlanic 0:02dd72d1d465 1351 */
borlanic 0:02dd72d1d465 1352 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
borlanic 0:02dd72d1d465 1353 {
borlanic 0:02dd72d1d465 1354 GICInterface->PMR = priority & 0xFFUL; //set priority mask
borlanic 0:02dd72d1d465 1355 }
borlanic 0:02dd72d1d465 1356
borlanic 0:02dd72d1d465 1357 /** \brief Read the current interrupt priority mask from CPU's PMR register.
borlanic 0:02dd72d1d465 1358 * \result GICInterface_Type::PMR
borlanic 0:02dd72d1d465 1359 */
borlanic 0:02dd72d1d465 1360 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
borlanic 0:02dd72d1d465 1361 {
borlanic 0:02dd72d1d465 1362 return GICInterface->PMR;
borlanic 0:02dd72d1d465 1363 }
borlanic 0:02dd72d1d465 1364
borlanic 0:02dd72d1d465 1365 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
borlanic 0:02dd72d1d465 1366 * \param [in] binary_point Amount of bits used as subpriority.
borlanic 0:02dd72d1d465 1367 */
borlanic 0:02dd72d1d465 1368 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
borlanic 0:02dd72d1d465 1369 {
borlanic 0:02dd72d1d465 1370 GICInterface->BPR = binary_point & 7U; //set binary point
borlanic 0:02dd72d1d465 1371 }
borlanic 0:02dd72d1d465 1372
borlanic 0:02dd72d1d465 1373 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
borlanic 0:02dd72d1d465 1374 * \return GICInterface_Type::BPR
borlanic 0:02dd72d1d465 1375 */
borlanic 0:02dd72d1d465 1376 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
borlanic 0:02dd72d1d465 1377 {
borlanic 0:02dd72d1d465 1378 return GICInterface->BPR;
borlanic 0:02dd72d1d465 1379 }
borlanic 0:02dd72d1d465 1380
borlanic 0:02dd72d1d465 1381 /** \brief Get the status for a given interrupt.
borlanic 0:02dd72d1d465 1382 * \param [in] IRQn The interrupt to get status for.
borlanic 0:02dd72d1d465 1383 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
borlanic 0:02dd72d1d465 1384 */
borlanic 0:02dd72d1d465 1385 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1386 {
borlanic 0:02dd72d1d465 1387 uint32_t pending, active;
borlanic 0:02dd72d1d465 1388
borlanic 0:02dd72d1d465 1389 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
borlanic 0:02dd72d1d465 1390 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
borlanic 0:02dd72d1d465 1391
borlanic 0:02dd72d1d465 1392 return ((active<<1U) | pending);
borlanic 0:02dd72d1d465 1393 }
borlanic 0:02dd72d1d465 1394
borlanic 0:02dd72d1d465 1395 /** \brief Generate a software interrupt using GIC's SGIR register.
borlanic 0:02dd72d1d465 1396 * \param [in] IRQn Software interrupt to be generated.
borlanic 0:02dd72d1d465 1397 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
borlanic 0:02dd72d1d465 1398 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
borlanic 0:02dd72d1d465 1399 */
borlanic 0:02dd72d1d465 1400 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
borlanic 0:02dd72d1d465 1401 {
borlanic 0:02dd72d1d465 1402 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
borlanic 0:02dd72d1d465 1403 }
borlanic 0:02dd72d1d465 1404
borlanic 0:02dd72d1d465 1405 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
borlanic 0:02dd72d1d465 1406 * \return GICInterface_Type::HPPIR
borlanic 0:02dd72d1d465 1407 */
borlanic 0:02dd72d1d465 1408 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
borlanic 0:02dd72d1d465 1409 {
borlanic 0:02dd72d1d465 1410 return GICInterface->HPPIR;
borlanic 0:02dd72d1d465 1411 }
borlanic 0:02dd72d1d465 1412
borlanic 0:02dd72d1d465 1413 /** \brief Provides information about the implementer and revision of the CPU interface.
borlanic 0:02dd72d1d465 1414 * \return GICInterface_Type::IIDR
borlanic 0:02dd72d1d465 1415 */
borlanic 0:02dd72d1d465 1416 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
borlanic 0:02dd72d1d465 1417 {
borlanic 0:02dd72d1d465 1418 return GICInterface->IIDR;
borlanic 0:02dd72d1d465 1419 }
borlanic 0:02dd72d1d465 1420
borlanic 0:02dd72d1d465 1421 /** \brief Set the interrupt group from the GIC's IGROUPR register.
borlanic 0:02dd72d1d465 1422 * \param [in] IRQn The interrupt to be queried.
borlanic 0:02dd72d1d465 1423 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
borlanic 0:02dd72d1d465 1424 */
borlanic 0:02dd72d1d465 1425 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
borlanic 0:02dd72d1d465 1426 {
borlanic 0:02dd72d1d465 1427 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
borlanic 0:02dd72d1d465 1428 uint32_t shift = (IRQn % 32U);
borlanic 0:02dd72d1d465 1429
borlanic 0:02dd72d1d465 1430 igroupr &= (~(1U << shift));
borlanic 0:02dd72d1d465 1431 igroupr |= ( (group & 1U) << shift);
borlanic 0:02dd72d1d465 1432
borlanic 0:02dd72d1d465 1433 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
borlanic 0:02dd72d1d465 1434 }
borlanic 0:02dd72d1d465 1435 #define GIC_SetSecurity GIC_SetGroup
borlanic 0:02dd72d1d465 1436
borlanic 0:02dd72d1d465 1437 /** \brief Get the interrupt group from the GIC's IGROUPR register.
borlanic 0:02dd72d1d465 1438 * \param [in] IRQn The interrupt to be queried.
borlanic 0:02dd72d1d465 1439 * \return 0 - Group 0, 1 - Group 1
borlanic 0:02dd72d1d465 1440 */
borlanic 0:02dd72d1d465 1441 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
borlanic 0:02dd72d1d465 1442 {
borlanic 0:02dd72d1d465 1443 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
borlanic 0:02dd72d1d465 1444 }
borlanic 0:02dd72d1d465 1445 #define GIC_GetSecurity GIC_GetGroup
borlanic 0:02dd72d1d465 1446
borlanic 0:02dd72d1d465 1447 /** \brief Initialize the interrupt distributor.
borlanic 0:02dd72d1d465 1448 */
borlanic 0:02dd72d1d465 1449 __STATIC_INLINE void GIC_DistInit(void)
borlanic 0:02dd72d1d465 1450 {
borlanic 0:02dd72d1d465 1451 uint32_t i;
borlanic 0:02dd72d1d465 1452 uint32_t num_irq = 0U;
borlanic 0:02dd72d1d465 1453 uint32_t priority_field;
borlanic 0:02dd72d1d465 1454
borlanic 0:02dd72d1d465 1455 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
borlanic 0:02dd72d1d465 1456 //configuring all of the interrupts as Secure.
borlanic 0:02dd72d1d465 1457
borlanic 0:02dd72d1d465 1458 //Disable interrupt forwarding
borlanic 0:02dd72d1d465 1459 GIC_DisableDistributor();
borlanic 0:02dd72d1d465 1460 //Get the maximum number of interrupts that the GIC supports
borlanic 0:02dd72d1d465 1461 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
borlanic 0:02dd72d1d465 1462
borlanic 0:02dd72d1d465 1463 /* Priority level is implementation defined.
borlanic 0:02dd72d1d465 1464 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
borlanic 0:02dd72d1d465 1465 priority field and read back the value stored.*/
borlanic 0:02dd72d1d465 1466 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
borlanic 0:02dd72d1d465 1467 priority_field = GIC_GetPriority((IRQn_Type)0U);
borlanic 0:02dd72d1d465 1468
borlanic 0:02dd72d1d465 1469 for (i = 32U; i < num_irq; i++)
borlanic 0:02dd72d1d465 1470 {
borlanic 0:02dd72d1d465 1471 //Disable the SPI interrupt
borlanic 0:02dd72d1d465 1472 GIC_DisableIRQ((IRQn_Type)i);
borlanic 0:02dd72d1d465 1473 //Set level-sensitive (and N-N model)
borlanic 0:02dd72d1d465 1474 GIC_SetConfiguration((IRQn_Type)i, 0U);
borlanic 0:02dd72d1d465 1475 //Set priority
borlanic 0:02dd72d1d465 1476 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
borlanic 0:02dd72d1d465 1477 //Set target list to CPU0
borlanic 0:02dd72d1d465 1478 GIC_SetTarget((IRQn_Type)i, 1U);
borlanic 0:02dd72d1d465 1479 }
borlanic 0:02dd72d1d465 1480 //Enable distributor
borlanic 0:02dd72d1d465 1481 GIC_EnableDistributor();
borlanic 0:02dd72d1d465 1482 }
borlanic 0:02dd72d1d465 1483
borlanic 0:02dd72d1d465 1484 /** \brief Initialize the CPU's interrupt interface
borlanic 0:02dd72d1d465 1485 */
borlanic 0:02dd72d1d465 1486 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
borlanic 0:02dd72d1d465 1487 {
borlanic 0:02dd72d1d465 1488 uint32_t i;
borlanic 0:02dd72d1d465 1489 uint32_t priority_field;
borlanic 0:02dd72d1d465 1490
borlanic 0:02dd72d1d465 1491 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
borlanic 0:02dd72d1d465 1492 //configuring all of the interrupts as Secure.
borlanic 0:02dd72d1d465 1493
borlanic 0:02dd72d1d465 1494 //Disable interrupt forwarding
borlanic 0:02dd72d1d465 1495 GIC_DisableInterface();
borlanic 0:02dd72d1d465 1496
borlanic 0:02dd72d1d465 1497 /* Priority level is implementation defined.
borlanic 0:02dd72d1d465 1498 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
borlanic 0:02dd72d1d465 1499 priority field and read back the value stored.*/
borlanic 0:02dd72d1d465 1500 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
borlanic 0:02dd72d1d465 1501 priority_field = GIC_GetPriority((IRQn_Type)0U);
borlanic 0:02dd72d1d465 1502
borlanic 0:02dd72d1d465 1503 //SGI and PPI
borlanic 0:02dd72d1d465 1504 for (i = 0U; i < 32U; i++)
borlanic 0:02dd72d1d465 1505 {
borlanic 0:02dd72d1d465 1506 if(i > 15U) {
borlanic 0:02dd72d1d465 1507 //Set level-sensitive (and N-N model) for PPI
borlanic 0:02dd72d1d465 1508 GIC_SetConfiguration((IRQn_Type)i, 0U);
borlanic 0:02dd72d1d465 1509 }
borlanic 0:02dd72d1d465 1510 //Disable SGI and PPI interrupts
borlanic 0:02dd72d1d465 1511 GIC_DisableIRQ((IRQn_Type)i);
borlanic 0:02dd72d1d465 1512 //Set priority
borlanic 0:02dd72d1d465 1513 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
borlanic 0:02dd72d1d465 1514 }
borlanic 0:02dd72d1d465 1515 //Enable interface
borlanic 0:02dd72d1d465 1516 GIC_EnableInterface();
borlanic 0:02dd72d1d465 1517 //Set binary point to 0
borlanic 0:02dd72d1d465 1518 GIC_SetBinaryPoint(0U);
borlanic 0:02dd72d1d465 1519 //Set priority mask
borlanic 0:02dd72d1d465 1520 GIC_SetInterfacePriorityMask(0xFFU);
borlanic 0:02dd72d1d465 1521 }
borlanic 0:02dd72d1d465 1522
borlanic 0:02dd72d1d465 1523 /** \brief Initialize and enable the GIC
borlanic 0:02dd72d1d465 1524 */
borlanic 0:02dd72d1d465 1525 __STATIC_INLINE void GIC_Enable(void)
borlanic 0:02dd72d1d465 1526 {
borlanic 0:02dd72d1d465 1527 GIC_DistInit();
borlanic 0:02dd72d1d465 1528 GIC_CPUInterfaceInit(); //per CPU
borlanic 0:02dd72d1d465 1529 }
borlanic 0:02dd72d1d465 1530 #endif
borlanic 0:02dd72d1d465 1531
borlanic 0:02dd72d1d465 1532 /* ########################## Generic Timer functions ############################ */
borlanic 0:02dd72d1d465 1533 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 1534
borlanic 0:02dd72d1d465 1535 /* PL1 Physical Timer */
borlanic 0:02dd72d1d465 1536 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 1537
borlanic 0:02dd72d1d465 1538 /** \brief Physical Timer Control register */
borlanic 0:02dd72d1d465 1539 typedef union
borlanic 0:02dd72d1d465 1540 {
borlanic 0:02dd72d1d465 1541 struct
borlanic 0:02dd72d1d465 1542 {
borlanic 0:02dd72d1d465 1543 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
borlanic 0:02dd72d1d465 1544 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
borlanic 0:02dd72d1d465 1545 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
borlanic 0:02dd72d1d465 1546 RESERVED(0:29, uint32_t)
borlanic 0:02dd72d1d465 1547 } b; /*!< \brief Structure used for bit access */
borlanic 0:02dd72d1d465 1548 uint32_t w; /*!< \brief Type used for word access */
borlanic 0:02dd72d1d465 1549 } CNTP_CTL_Type;
borlanic 0:02dd72d1d465 1550
borlanic 0:02dd72d1d465 1551 /** \brief Configures the frequency the timer shall run at.
borlanic 0:02dd72d1d465 1552 * \param [in] value The timer frequency in Hz.
borlanic 0:02dd72d1d465 1553 */
borlanic 0:02dd72d1d465 1554 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
borlanic 0:02dd72d1d465 1555 {
borlanic 0:02dd72d1d465 1556 __set_CNTFRQ(value);
borlanic 0:02dd72d1d465 1557 __ISB();
borlanic 0:02dd72d1d465 1558 }
borlanic 0:02dd72d1d465 1559
borlanic 0:02dd72d1d465 1560 /** \brief Sets the reset value of the timer.
borlanic 0:02dd72d1d465 1561 * \param [in] value The value the timer is loaded with.
borlanic 0:02dd72d1d465 1562 */
borlanic 0:02dd72d1d465 1563 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
borlanic 0:02dd72d1d465 1564 {
borlanic 0:02dd72d1d465 1565 __set_CNTP_TVAL(value);
borlanic 0:02dd72d1d465 1566 __ISB();
borlanic 0:02dd72d1d465 1567 }
borlanic 0:02dd72d1d465 1568
borlanic 0:02dd72d1d465 1569 /** \brief Get the current counter value.
borlanic 0:02dd72d1d465 1570 * \return Current counter value.
borlanic 0:02dd72d1d465 1571 */
borlanic 0:02dd72d1d465 1572 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
borlanic 0:02dd72d1d465 1573 {
borlanic 0:02dd72d1d465 1574 return(__get_CNTP_TVAL());
borlanic 0:02dd72d1d465 1575 }
borlanic 0:02dd72d1d465 1576
borlanic 0:02dd72d1d465 1577 /** \brief Get the current physical counter value.
borlanic 0:02dd72d1d465 1578 * \return Current physical counter value.
borlanic 0:02dd72d1d465 1579 */
borlanic 0:02dd72d1d465 1580 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
borlanic 0:02dd72d1d465 1581 {
borlanic 0:02dd72d1d465 1582 return(__get_CNTPCT());
borlanic 0:02dd72d1d465 1583 }
borlanic 0:02dd72d1d465 1584
borlanic 0:02dd72d1d465 1585 /** \brief Set the physical compare value.
borlanic 0:02dd72d1d465 1586 * \param [in] value New physical timer compare value.
borlanic 0:02dd72d1d465 1587 */
borlanic 0:02dd72d1d465 1588 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
borlanic 0:02dd72d1d465 1589 {
borlanic 0:02dd72d1d465 1590 __set_CNTP_CVAL(value);
borlanic 0:02dd72d1d465 1591 __ISB();
borlanic 0:02dd72d1d465 1592 }
borlanic 0:02dd72d1d465 1593
borlanic 0:02dd72d1d465 1594 /** \brief Get the physical compare value.
borlanic 0:02dd72d1d465 1595 * \return Physical compare value.
borlanic 0:02dd72d1d465 1596 */
borlanic 0:02dd72d1d465 1597 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
borlanic 0:02dd72d1d465 1598 {
borlanic 0:02dd72d1d465 1599 return(__get_CNTP_CVAL());
borlanic 0:02dd72d1d465 1600 }
borlanic 0:02dd72d1d465 1601
borlanic 0:02dd72d1d465 1602 /** \brief Configure the timer by setting the control value.
borlanic 0:02dd72d1d465 1603 * \param [in] value New timer control value.
borlanic 0:02dd72d1d465 1604 */
borlanic 0:02dd72d1d465 1605 __STATIC_INLINE void PL1_SetControl(uint32_t value)
borlanic 0:02dd72d1d465 1606 {
borlanic 0:02dd72d1d465 1607 __set_CNTP_CTL(value);
borlanic 0:02dd72d1d465 1608 __ISB();
borlanic 0:02dd72d1d465 1609 }
borlanic 0:02dd72d1d465 1610
borlanic 0:02dd72d1d465 1611 /** \brief Get the control value.
borlanic 0:02dd72d1d465 1612 * \return Control value.
borlanic 0:02dd72d1d465 1613 */
borlanic 0:02dd72d1d465 1614 __STATIC_INLINE uint32_t PL1_GetControl(void)
borlanic 0:02dd72d1d465 1615 {
borlanic 0:02dd72d1d465 1616 return(__get_CNTP_CTL());
borlanic 0:02dd72d1d465 1617 }
borlanic 0:02dd72d1d465 1618 #endif
borlanic 0:02dd72d1d465 1619
borlanic 0:02dd72d1d465 1620 /* Private Timer */
borlanic 0:02dd72d1d465 1621 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
borlanic 0:02dd72d1d465 1622 /** \brief Set the load value to timers LOAD register.
borlanic 0:02dd72d1d465 1623 * \param [in] value The load value to be set.
borlanic 0:02dd72d1d465 1624 */
borlanic 0:02dd72d1d465 1625 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
borlanic 0:02dd72d1d465 1626 {
borlanic 0:02dd72d1d465 1627 PTIM->LOAD = value;
borlanic 0:02dd72d1d465 1628 }
borlanic 0:02dd72d1d465 1629
borlanic 0:02dd72d1d465 1630 /** \brief Get the load value from timers LOAD register.
borlanic 0:02dd72d1d465 1631 * \return Timer_Type::LOAD
borlanic 0:02dd72d1d465 1632 */
borlanic 0:02dd72d1d465 1633 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
borlanic 0:02dd72d1d465 1634 {
borlanic 0:02dd72d1d465 1635 return(PTIM->LOAD);
borlanic 0:02dd72d1d465 1636 }
borlanic 0:02dd72d1d465 1637
borlanic 0:02dd72d1d465 1638 /** \brief Set current counter value from its COUNTER register.
borlanic 0:02dd72d1d465 1639 */
borlanic 0:02dd72d1d465 1640 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
borlanic 0:02dd72d1d465 1641 {
borlanic 0:02dd72d1d465 1642 PTIM->COUNTER = value;
borlanic 0:02dd72d1d465 1643 }
borlanic 0:02dd72d1d465 1644
borlanic 0:02dd72d1d465 1645 /** \brief Get current counter value from timers COUNTER register.
borlanic 0:02dd72d1d465 1646 * \result Timer_Type::COUNTER
borlanic 0:02dd72d1d465 1647 */
borlanic 0:02dd72d1d465 1648 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
borlanic 0:02dd72d1d465 1649 {
borlanic 0:02dd72d1d465 1650 return(PTIM->COUNTER);
borlanic 0:02dd72d1d465 1651 }
borlanic 0:02dd72d1d465 1652
borlanic 0:02dd72d1d465 1653 /** \brief Configure the timer using its CONTROL register.
borlanic 0:02dd72d1d465 1654 * \param [in] value The new configuration value to be set.
borlanic 0:02dd72d1d465 1655 */
borlanic 0:02dd72d1d465 1656 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
borlanic 0:02dd72d1d465 1657 {
borlanic 0:02dd72d1d465 1658 PTIM->CONTROL = value;
borlanic 0:02dd72d1d465 1659 }
borlanic 0:02dd72d1d465 1660
borlanic 0:02dd72d1d465 1661 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
borlanic 0:02dd72d1d465 1662 * \return Timer_Type::CONTROL
borlanic 0:02dd72d1d465 1663 */
borlanic 0:02dd72d1d465 1664 __STATIC_INLINE uint32_t PTIM_GetControl(void)
borlanic 0:02dd72d1d465 1665 {
borlanic 0:02dd72d1d465 1666 return(PTIM->CONTROL);
borlanic 0:02dd72d1d465 1667 }
borlanic 0:02dd72d1d465 1668
borlanic 0:02dd72d1d465 1669 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
borlanic 0:02dd72d1d465 1670 * \return 0 - flag is not set, 1- flag is set
borlanic 0:02dd72d1d465 1671 */
borlanic 0:02dd72d1d465 1672 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
borlanic 0:02dd72d1d465 1673 {
borlanic 0:02dd72d1d465 1674 return (PTIM->ISR & 1UL);
borlanic 0:02dd72d1d465 1675 }
borlanic 0:02dd72d1d465 1676
borlanic 0:02dd72d1d465 1677 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
borlanic 0:02dd72d1d465 1678 */
borlanic 0:02dd72d1d465 1679 __STATIC_INLINE void PTIM_ClearEventFlag(void)
borlanic 0:02dd72d1d465 1680 {
borlanic 0:02dd72d1d465 1681 PTIM->ISR = 1;
borlanic 0:02dd72d1d465 1682 }
borlanic 0:02dd72d1d465 1683 #endif
borlanic 0:02dd72d1d465 1684 #endif
borlanic 0:02dd72d1d465 1685
borlanic 0:02dd72d1d465 1686 /* ########################## MMU functions ###################################### */
borlanic 0:02dd72d1d465 1687
borlanic 0:02dd72d1d465 1688 #define SECTION_DESCRIPTOR (0x2)
borlanic 0:02dd72d1d465 1689 #define SECTION_MASK (0xFFFFFFFC)
borlanic 0:02dd72d1d465 1690
borlanic 0:02dd72d1d465 1691 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
borlanic 0:02dd72d1d465 1692 #define SECTION_B_SHIFT (2)
borlanic 0:02dd72d1d465 1693 #define SECTION_C_SHIFT (3)
borlanic 0:02dd72d1d465 1694 #define SECTION_TEX0_SHIFT (12)
borlanic 0:02dd72d1d465 1695 #define SECTION_TEX1_SHIFT (13)
borlanic 0:02dd72d1d465 1696 #define SECTION_TEX2_SHIFT (14)
borlanic 0:02dd72d1d465 1697
borlanic 0:02dd72d1d465 1698 #define SECTION_XN_MASK (0xFFFFFFEF)
borlanic 0:02dd72d1d465 1699 #define SECTION_XN_SHIFT (4)
borlanic 0:02dd72d1d465 1700
borlanic 0:02dd72d1d465 1701 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
borlanic 0:02dd72d1d465 1702 #define SECTION_DOMAIN_SHIFT (5)
borlanic 0:02dd72d1d465 1703
borlanic 0:02dd72d1d465 1704 #define SECTION_P_MASK (0xFFFFFDFF)
borlanic 0:02dd72d1d465 1705 #define SECTION_P_SHIFT (9)
borlanic 0:02dd72d1d465 1706
borlanic 0:02dd72d1d465 1707 #define SECTION_AP_MASK (0xFFFF73FF)
borlanic 0:02dd72d1d465 1708 #define SECTION_AP_SHIFT (10)
borlanic 0:02dd72d1d465 1709 #define SECTION_AP2_SHIFT (15)
borlanic 0:02dd72d1d465 1710
borlanic 0:02dd72d1d465 1711 #define SECTION_S_MASK (0xFFFEFFFF)
borlanic 0:02dd72d1d465 1712 #define SECTION_S_SHIFT (16)
borlanic 0:02dd72d1d465 1713
borlanic 0:02dd72d1d465 1714 #define SECTION_NG_MASK (0xFFFDFFFF)
borlanic 0:02dd72d1d465 1715 #define SECTION_NG_SHIFT (17)
borlanic 0:02dd72d1d465 1716
borlanic 0:02dd72d1d465 1717 #define SECTION_NS_MASK (0xFFF7FFFF)
borlanic 0:02dd72d1d465 1718 #define SECTION_NS_SHIFT (19)
borlanic 0:02dd72d1d465 1719
borlanic 0:02dd72d1d465 1720 #define PAGE_L1_DESCRIPTOR (0x1)
borlanic 0:02dd72d1d465 1721 #define PAGE_L1_MASK (0xFFFFFFFC)
borlanic 0:02dd72d1d465 1722
borlanic 0:02dd72d1d465 1723 #define PAGE_L2_4K_DESC (0x2)
borlanic 0:02dd72d1d465 1724 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
borlanic 0:02dd72d1d465 1725
borlanic 0:02dd72d1d465 1726 #define PAGE_L2_64K_DESC (0x1)
borlanic 0:02dd72d1d465 1727 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
borlanic 0:02dd72d1d465 1728
borlanic 0:02dd72d1d465 1729 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
borlanic 0:02dd72d1d465 1730 #define PAGE_4K_B_SHIFT (2)
borlanic 0:02dd72d1d465 1731 #define PAGE_4K_C_SHIFT (3)
borlanic 0:02dd72d1d465 1732 #define PAGE_4K_TEX0_SHIFT (6)
borlanic 0:02dd72d1d465 1733 #define PAGE_4K_TEX1_SHIFT (7)
borlanic 0:02dd72d1d465 1734 #define PAGE_4K_TEX2_SHIFT (8)
borlanic 0:02dd72d1d465 1735
borlanic 0:02dd72d1d465 1736 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
borlanic 0:02dd72d1d465 1737 #define PAGE_64K_B_SHIFT (2)
borlanic 0:02dd72d1d465 1738 #define PAGE_64K_C_SHIFT (3)
borlanic 0:02dd72d1d465 1739 #define PAGE_64K_TEX0_SHIFT (12)
borlanic 0:02dd72d1d465 1740 #define PAGE_64K_TEX1_SHIFT (13)
borlanic 0:02dd72d1d465 1741 #define PAGE_64K_TEX2_SHIFT (14)
borlanic 0:02dd72d1d465 1742
borlanic 0:02dd72d1d465 1743 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
borlanic 0:02dd72d1d465 1744 #define PAGE_B_SHIFT (2)
borlanic 0:02dd72d1d465 1745 #define PAGE_C_SHIFT (3)
borlanic 0:02dd72d1d465 1746 #define PAGE_TEX_SHIFT (12)
borlanic 0:02dd72d1d465 1747
borlanic 0:02dd72d1d465 1748 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
borlanic 0:02dd72d1d465 1749 #define PAGE_XN_4K_SHIFT (0)
borlanic 0:02dd72d1d465 1750 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
borlanic 0:02dd72d1d465 1751 #define PAGE_XN_64K_SHIFT (15)
borlanic 0:02dd72d1d465 1752
borlanic 0:02dd72d1d465 1753 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
borlanic 0:02dd72d1d465 1754 #define PAGE_DOMAIN_SHIFT (5)
borlanic 0:02dd72d1d465 1755
borlanic 0:02dd72d1d465 1756 #define PAGE_P_MASK (0xFFFFFDFF)
borlanic 0:02dd72d1d465 1757 #define PAGE_P_SHIFT (9)
borlanic 0:02dd72d1d465 1758
borlanic 0:02dd72d1d465 1759 #define PAGE_AP_MASK (0xFFFFFDCF)
borlanic 0:02dd72d1d465 1760 #define PAGE_AP_SHIFT (4)
borlanic 0:02dd72d1d465 1761 #define PAGE_AP2_SHIFT (9)
borlanic 0:02dd72d1d465 1762
borlanic 0:02dd72d1d465 1763 #define PAGE_S_MASK (0xFFFFFBFF)
borlanic 0:02dd72d1d465 1764 #define PAGE_S_SHIFT (10)
borlanic 0:02dd72d1d465 1765
borlanic 0:02dd72d1d465 1766 #define PAGE_NG_MASK (0xFFFFF7FF)
borlanic 0:02dd72d1d465 1767 #define PAGE_NG_SHIFT (11)
borlanic 0:02dd72d1d465 1768
borlanic 0:02dd72d1d465 1769 #define PAGE_NS_MASK (0xFFFFFFF7)
borlanic 0:02dd72d1d465 1770 #define PAGE_NS_SHIFT (3)
borlanic 0:02dd72d1d465 1771
borlanic 0:02dd72d1d465 1772 #define OFFSET_1M (0x00100000)
borlanic 0:02dd72d1d465 1773 #define OFFSET_64K (0x00010000)
borlanic 0:02dd72d1d465 1774 #define OFFSET_4K (0x00001000)
borlanic 0:02dd72d1d465 1775
borlanic 0:02dd72d1d465 1776 #define DESCRIPTOR_FAULT (0x00000000)
borlanic 0:02dd72d1d465 1777
borlanic 0:02dd72d1d465 1778 /* Attributes enumerations */
borlanic 0:02dd72d1d465 1779
borlanic 0:02dd72d1d465 1780 /* Region size attributes */
borlanic 0:02dd72d1d465 1781 typedef enum
borlanic 0:02dd72d1d465 1782 {
borlanic 0:02dd72d1d465 1783 SECTION,
borlanic 0:02dd72d1d465 1784 PAGE_4k,
borlanic 0:02dd72d1d465 1785 PAGE_64k,
borlanic 0:02dd72d1d465 1786 } mmu_region_size_Type;
borlanic 0:02dd72d1d465 1787
borlanic 0:02dd72d1d465 1788 /* Region type attributes */
borlanic 0:02dd72d1d465 1789 typedef enum
borlanic 0:02dd72d1d465 1790 {
borlanic 0:02dd72d1d465 1791 NORMAL,
borlanic 0:02dd72d1d465 1792 DEVICE,
borlanic 0:02dd72d1d465 1793 SHARED_DEVICE,
borlanic 0:02dd72d1d465 1794 NON_SHARED_DEVICE,
borlanic 0:02dd72d1d465 1795 STRONGLY_ORDERED
borlanic 0:02dd72d1d465 1796 } mmu_memory_Type;
borlanic 0:02dd72d1d465 1797
borlanic 0:02dd72d1d465 1798 /* Region cacheability attributes */
borlanic 0:02dd72d1d465 1799 typedef enum
borlanic 0:02dd72d1d465 1800 {
borlanic 0:02dd72d1d465 1801 NON_CACHEABLE,
borlanic 0:02dd72d1d465 1802 WB_WA,
borlanic 0:02dd72d1d465 1803 WT,
borlanic 0:02dd72d1d465 1804 WB_NO_WA,
borlanic 0:02dd72d1d465 1805 } mmu_cacheability_Type;
borlanic 0:02dd72d1d465 1806
borlanic 0:02dd72d1d465 1807 /* Region parity check attributes */
borlanic 0:02dd72d1d465 1808 typedef enum
borlanic 0:02dd72d1d465 1809 {
borlanic 0:02dd72d1d465 1810 ECC_DISABLED,
borlanic 0:02dd72d1d465 1811 ECC_ENABLED,
borlanic 0:02dd72d1d465 1812 } mmu_ecc_check_Type;
borlanic 0:02dd72d1d465 1813
borlanic 0:02dd72d1d465 1814 /* Region execution attributes */
borlanic 0:02dd72d1d465 1815 typedef enum
borlanic 0:02dd72d1d465 1816 {
borlanic 0:02dd72d1d465 1817 EXECUTE,
borlanic 0:02dd72d1d465 1818 NON_EXECUTE,
borlanic 0:02dd72d1d465 1819 } mmu_execute_Type;
borlanic 0:02dd72d1d465 1820
borlanic 0:02dd72d1d465 1821 /* Region global attributes */
borlanic 0:02dd72d1d465 1822 typedef enum
borlanic 0:02dd72d1d465 1823 {
borlanic 0:02dd72d1d465 1824 GLOBAL,
borlanic 0:02dd72d1d465 1825 NON_GLOBAL,
borlanic 0:02dd72d1d465 1826 } mmu_global_Type;
borlanic 0:02dd72d1d465 1827
borlanic 0:02dd72d1d465 1828 /* Region shareability attributes */
borlanic 0:02dd72d1d465 1829 typedef enum
borlanic 0:02dd72d1d465 1830 {
borlanic 0:02dd72d1d465 1831 NON_SHARED,
borlanic 0:02dd72d1d465 1832 SHARED,
borlanic 0:02dd72d1d465 1833 } mmu_shared_Type;
borlanic 0:02dd72d1d465 1834
borlanic 0:02dd72d1d465 1835 /* Region security attributes */
borlanic 0:02dd72d1d465 1836 typedef enum
borlanic 0:02dd72d1d465 1837 {
borlanic 0:02dd72d1d465 1838 SECURE,
borlanic 0:02dd72d1d465 1839 NON_SECURE,
borlanic 0:02dd72d1d465 1840 } mmu_secure_Type;
borlanic 0:02dd72d1d465 1841
borlanic 0:02dd72d1d465 1842 /* Region access attributes */
borlanic 0:02dd72d1d465 1843 typedef enum
borlanic 0:02dd72d1d465 1844 {
borlanic 0:02dd72d1d465 1845 NO_ACCESS,
borlanic 0:02dd72d1d465 1846 RW,
borlanic 0:02dd72d1d465 1847 READ,
borlanic 0:02dd72d1d465 1848 } mmu_access_Type;
borlanic 0:02dd72d1d465 1849
borlanic 0:02dd72d1d465 1850 /* Memory Region definition */
borlanic 0:02dd72d1d465 1851 typedef struct RegionStruct {
borlanic 0:02dd72d1d465 1852 mmu_region_size_Type rg_t;
borlanic 0:02dd72d1d465 1853 mmu_memory_Type mem_t;
borlanic 0:02dd72d1d465 1854 uint8_t domain;
borlanic 0:02dd72d1d465 1855 mmu_cacheability_Type inner_norm_t;
borlanic 0:02dd72d1d465 1856 mmu_cacheability_Type outer_norm_t;
borlanic 0:02dd72d1d465 1857 mmu_ecc_check_Type e_t;
borlanic 0:02dd72d1d465 1858 mmu_execute_Type xn_t;
borlanic 0:02dd72d1d465 1859 mmu_global_Type g_t;
borlanic 0:02dd72d1d465 1860 mmu_secure_Type sec_t;
borlanic 0:02dd72d1d465 1861 mmu_access_Type priv_t;
borlanic 0:02dd72d1d465 1862 mmu_access_Type user_t;
borlanic 0:02dd72d1d465 1863 mmu_shared_Type sh_t;
borlanic 0:02dd72d1d465 1864
borlanic 0:02dd72d1d465 1865 } mmu_region_attributes_Type;
borlanic 0:02dd72d1d465 1866
borlanic 0:02dd72d1d465 1867 //Following macros define the descriptors and attributes
borlanic 0:02dd72d1d465 1868 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
borlanic 0:02dd72d1d465 1869 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1870 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1871 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1872 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1873 region.inner_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1874 region.outer_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1875 region.mem_t = NORMAL; \
borlanic 0:02dd72d1d465 1876 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1877 region.xn_t = EXECUTE; \
borlanic 0:02dd72d1d465 1878 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1879 region.user_t = RW; \
borlanic 0:02dd72d1d465 1880 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1881 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1882
borlanic 0:02dd72d1d465 1883 //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
borlanic 0:02dd72d1d465 1884 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1885 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1886 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1887 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1888 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1889 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1890 region.mem_t = NORMAL; \
borlanic 0:02dd72d1d465 1891 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1892 region.xn_t = EXECUTE; \
borlanic 0:02dd72d1d465 1893 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1894 region.user_t = RW; \
borlanic 0:02dd72d1d465 1895 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1896 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1897
borlanic 0:02dd72d1d465 1898 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
borlanic 0:02dd72d1d465 1899 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1900 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1901 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1902 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1903 region.inner_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1904 region.outer_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1905 region.mem_t = NORMAL; \
borlanic 0:02dd72d1d465 1906 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1907 region.xn_t = EXECUTE; \
borlanic 0:02dd72d1d465 1908 region.priv_t = READ; \
borlanic 0:02dd72d1d465 1909 region.user_t = READ; \
borlanic 0:02dd72d1d465 1910 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1911 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1912
borlanic 0:02dd72d1d465 1913 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
borlanic 0:02dd72d1d465 1914 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1915 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1916 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1917 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1918 region.inner_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1919 region.outer_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1920 region.mem_t = NORMAL; \
borlanic 0:02dd72d1d465 1921 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1922 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1923 region.priv_t = READ; \
borlanic 0:02dd72d1d465 1924 region.user_t = READ; \
borlanic 0:02dd72d1d465 1925 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1926 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1927
borlanic 0:02dd72d1d465 1928 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
borlanic 0:02dd72d1d465 1929 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1930 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1931 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1932 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1933 region.inner_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1934 region.outer_norm_t = WB_WA; \
borlanic 0:02dd72d1d465 1935 region.mem_t = NORMAL; \
borlanic 0:02dd72d1d465 1936 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1937 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1938 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1939 region.user_t = RW; \
borlanic 0:02dd72d1d465 1940 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1941 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1942 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
borlanic 0:02dd72d1d465 1943 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1944 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1945 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1946 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1947 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1948 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1949 region.mem_t = STRONGLY_ORDERED; \
borlanic 0:02dd72d1d465 1950 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1951 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1952 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1953 region.user_t = RW; \
borlanic 0:02dd72d1d465 1954 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1955 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1956
borlanic 0:02dd72d1d465 1957 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
borlanic 0:02dd72d1d465 1958 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1959 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1960 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1961 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1962 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1963 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1964 region.mem_t = STRONGLY_ORDERED; \
borlanic 0:02dd72d1d465 1965 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1966 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1967 region.priv_t = READ; \
borlanic 0:02dd72d1d465 1968 region.user_t = READ; \
borlanic 0:02dd72d1d465 1969 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1970 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1971
borlanic 0:02dd72d1d465 1972 //Sect_Device_RW. Sect_Device_RO, but writeable
borlanic 0:02dd72d1d465 1973 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
borlanic 0:02dd72d1d465 1974 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1975 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1976 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1977 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1978 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1979 region.mem_t = STRONGLY_ORDERED; \
borlanic 0:02dd72d1d465 1980 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1981 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1982 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1983 region.user_t = RW; \
borlanic 0:02dd72d1d465 1984 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1985 MMU_GetSectionDescriptor(&descriptor_l1, region);
borlanic 0:02dd72d1d465 1986 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
borlanic 0:02dd72d1d465 1987 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
borlanic 0:02dd72d1d465 1988 region.domain = 0x0; \
borlanic 0:02dd72d1d465 1989 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 1990 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 1991 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1992 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 1993 region.mem_t = SHARED_DEVICE; \
borlanic 0:02dd72d1d465 1994 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 1995 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 1996 region.priv_t = RW; \
borlanic 0:02dd72d1d465 1997 region.user_t = RW; \
borlanic 0:02dd72d1d465 1998 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 1999 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
borlanic 0:02dd72d1d465 2000
borlanic 0:02dd72d1d465 2001 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
borlanic 0:02dd72d1d465 2002 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
borlanic 0:02dd72d1d465 2003 region.domain = 0x0; \
borlanic 0:02dd72d1d465 2004 region.e_t = ECC_DISABLED; \
borlanic 0:02dd72d1d465 2005 region.g_t = GLOBAL; \
borlanic 0:02dd72d1d465 2006 region.inner_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 2007 region.outer_norm_t = NON_CACHEABLE; \
borlanic 0:02dd72d1d465 2008 region.mem_t = SHARED_DEVICE; \
borlanic 0:02dd72d1d465 2009 region.sec_t = SECURE; \
borlanic 0:02dd72d1d465 2010 region.xn_t = NON_EXECUTE; \
borlanic 0:02dd72d1d465 2011 region.priv_t = RW; \
borlanic 0:02dd72d1d465 2012 region.user_t = RW; \
borlanic 0:02dd72d1d465 2013 region.sh_t = NON_SHARED; \
borlanic 0:02dd72d1d465 2014 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
borlanic 0:02dd72d1d465 2015
borlanic 0:02dd72d1d465 2016 /** \brief Set section execution-never attribute
borlanic 0:02dd72d1d465 2017
borlanic 0:02dd72d1d465 2018 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2019 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
borlanic 0:02dd72d1d465 2020
borlanic 0:02dd72d1d465 2021 \return 0
borlanic 0:02dd72d1d465 2022 */
borlanic 0:02dd72d1d465 2023 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
borlanic 0:02dd72d1d465 2024 {
borlanic 0:02dd72d1d465 2025 *descriptor_l1 &= SECTION_XN_MASK;
borlanic 0:02dd72d1d465 2026 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
borlanic 0:02dd72d1d465 2027 return 0;
borlanic 0:02dd72d1d465 2028 }
borlanic 0:02dd72d1d465 2029
borlanic 0:02dd72d1d465 2030 /** \brief Set section domain
borlanic 0:02dd72d1d465 2031
borlanic 0:02dd72d1d465 2032 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2033 \param [in] domain Section domain
borlanic 0:02dd72d1d465 2034
borlanic 0:02dd72d1d465 2035 \return 0
borlanic 0:02dd72d1d465 2036 */
borlanic 0:02dd72d1d465 2037 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
borlanic 0:02dd72d1d465 2038 {
borlanic 0:02dd72d1d465 2039 *descriptor_l1 &= SECTION_DOMAIN_MASK;
borlanic 0:02dd72d1d465 2040 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
borlanic 0:02dd72d1d465 2041 return 0;
borlanic 0:02dd72d1d465 2042 }
borlanic 0:02dd72d1d465 2043
borlanic 0:02dd72d1d465 2044 /** \brief Set section parity check
borlanic 0:02dd72d1d465 2045
borlanic 0:02dd72d1d465 2046 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2047 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
borlanic 0:02dd72d1d465 2048
borlanic 0:02dd72d1d465 2049 \return 0
borlanic 0:02dd72d1d465 2050 */
borlanic 0:02dd72d1d465 2051 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
borlanic 0:02dd72d1d465 2052 {
borlanic 0:02dd72d1d465 2053 *descriptor_l1 &= SECTION_P_MASK;
borlanic 0:02dd72d1d465 2054 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
borlanic 0:02dd72d1d465 2055 return 0;
borlanic 0:02dd72d1d465 2056 }
borlanic 0:02dd72d1d465 2057
borlanic 0:02dd72d1d465 2058 /** \brief Set section access privileges
borlanic 0:02dd72d1d465 2059
borlanic 0:02dd72d1d465 2060 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2061 \param [in] user User Level Access: NO_ACCESS, RW, READ
borlanic 0:02dd72d1d465 2062 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
borlanic 0:02dd72d1d465 2063 \param [in] afe Access flag enable
borlanic 0:02dd72d1d465 2064
borlanic 0:02dd72d1d465 2065 \return 0
borlanic 0:02dd72d1d465 2066 */
borlanic 0:02dd72d1d465 2067 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
borlanic 0:02dd72d1d465 2068 {
borlanic 0:02dd72d1d465 2069 uint32_t ap = 0;
borlanic 0:02dd72d1d465 2070
borlanic 0:02dd72d1d465 2071 if (afe == 0) { //full access
borlanic 0:02dd72d1d465 2072 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
borlanic 0:02dd72d1d465 2073 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
borlanic 0:02dd72d1d465 2074 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
borlanic 0:02dd72d1d465 2075 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
borlanic 0:02dd72d1d465 2076 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
borlanic 0:02dd72d1d465 2077 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
borlanic 0:02dd72d1d465 2078 }
borlanic 0:02dd72d1d465 2079
borlanic 0:02dd72d1d465 2080 else { //Simplified access
borlanic 0:02dd72d1d465 2081 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
borlanic 0:02dd72d1d465 2082 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
borlanic 0:02dd72d1d465 2083 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
borlanic 0:02dd72d1d465 2084 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
borlanic 0:02dd72d1d465 2085 }
borlanic 0:02dd72d1d465 2086
borlanic 0:02dd72d1d465 2087 *descriptor_l1 &= SECTION_AP_MASK;
borlanic 0:02dd72d1d465 2088 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
borlanic 0:02dd72d1d465 2089 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
borlanic 0:02dd72d1d465 2090
borlanic 0:02dd72d1d465 2091 return 0;
borlanic 0:02dd72d1d465 2092 }
borlanic 0:02dd72d1d465 2093
borlanic 0:02dd72d1d465 2094 /** \brief Set section shareability
borlanic 0:02dd72d1d465 2095
borlanic 0:02dd72d1d465 2096 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2097 \param [in] s_bit Section shareability: NON_SHARED, SHARED
borlanic 0:02dd72d1d465 2098
borlanic 0:02dd72d1d465 2099 \return 0
borlanic 0:02dd72d1d465 2100 */
borlanic 0:02dd72d1d465 2101 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
borlanic 0:02dd72d1d465 2102 {
borlanic 0:02dd72d1d465 2103 *descriptor_l1 &= SECTION_S_MASK;
borlanic 0:02dd72d1d465 2104 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
borlanic 0:02dd72d1d465 2105 return 0;
borlanic 0:02dd72d1d465 2106 }
borlanic 0:02dd72d1d465 2107
borlanic 0:02dd72d1d465 2108 /** \brief Set section Global attribute
borlanic 0:02dd72d1d465 2109
borlanic 0:02dd72d1d465 2110 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2111 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
borlanic 0:02dd72d1d465 2112
borlanic 0:02dd72d1d465 2113 \return 0
borlanic 0:02dd72d1d465 2114 */
borlanic 0:02dd72d1d465 2115 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
borlanic 0:02dd72d1d465 2116 {
borlanic 0:02dd72d1d465 2117 *descriptor_l1 &= SECTION_NG_MASK;
borlanic 0:02dd72d1d465 2118 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
borlanic 0:02dd72d1d465 2119 return 0;
borlanic 0:02dd72d1d465 2120 }
borlanic 0:02dd72d1d465 2121
borlanic 0:02dd72d1d465 2122 /** \brief Set section Security attribute
borlanic 0:02dd72d1d465 2123
borlanic 0:02dd72d1d465 2124 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2125 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
borlanic 0:02dd72d1d465 2126
borlanic 0:02dd72d1d465 2127 \return 0
borlanic 0:02dd72d1d465 2128 */
borlanic 0:02dd72d1d465 2129 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
borlanic 0:02dd72d1d465 2130 {
borlanic 0:02dd72d1d465 2131 *descriptor_l1 &= SECTION_NS_MASK;
borlanic 0:02dd72d1d465 2132 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
borlanic 0:02dd72d1d465 2133 return 0;
borlanic 0:02dd72d1d465 2134 }
borlanic 0:02dd72d1d465 2135
borlanic 0:02dd72d1d465 2136 /* Page 4k or 64k */
borlanic 0:02dd72d1d465 2137 /** \brief Set 4k/64k page execution-never attribute
borlanic 0:02dd72d1d465 2138
borlanic 0:02dd72d1d465 2139 \param [out] descriptor_l2 L2 descriptor.
borlanic 0:02dd72d1d465 2140 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
borlanic 0:02dd72d1d465 2141 \param [in] page Page size: PAGE_4k, PAGE_64k,
borlanic 0:02dd72d1d465 2142
borlanic 0:02dd72d1d465 2143 \return 0
borlanic 0:02dd72d1d465 2144 */
borlanic 0:02dd72d1d465 2145 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
borlanic 0:02dd72d1d465 2146 {
borlanic 0:02dd72d1d465 2147 if (page == PAGE_4k)
borlanic 0:02dd72d1d465 2148 {
borlanic 0:02dd72d1d465 2149 *descriptor_l2 &= PAGE_XN_4K_MASK;
borlanic 0:02dd72d1d465 2150 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
borlanic 0:02dd72d1d465 2151 }
borlanic 0:02dd72d1d465 2152 else
borlanic 0:02dd72d1d465 2153 {
borlanic 0:02dd72d1d465 2154 *descriptor_l2 &= PAGE_XN_64K_MASK;
borlanic 0:02dd72d1d465 2155 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
borlanic 0:02dd72d1d465 2156 }
borlanic 0:02dd72d1d465 2157 return 0;
borlanic 0:02dd72d1d465 2158 }
borlanic 0:02dd72d1d465 2159
borlanic 0:02dd72d1d465 2160 /** \brief Set 4k/64k page domain
borlanic 0:02dd72d1d465 2161
borlanic 0:02dd72d1d465 2162 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2163 \param [in] domain Page domain
borlanic 0:02dd72d1d465 2164
borlanic 0:02dd72d1d465 2165 \return 0
borlanic 0:02dd72d1d465 2166 */
borlanic 0:02dd72d1d465 2167 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
borlanic 0:02dd72d1d465 2168 {
borlanic 0:02dd72d1d465 2169 *descriptor_l1 &= PAGE_DOMAIN_MASK;
borlanic 0:02dd72d1d465 2170 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
borlanic 0:02dd72d1d465 2171 return 0;
borlanic 0:02dd72d1d465 2172 }
borlanic 0:02dd72d1d465 2173
borlanic 0:02dd72d1d465 2174 /** \brief Set 4k/64k page parity check
borlanic 0:02dd72d1d465 2175
borlanic 0:02dd72d1d465 2176 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2177 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
borlanic 0:02dd72d1d465 2178
borlanic 0:02dd72d1d465 2179 \return 0
borlanic 0:02dd72d1d465 2180 */
borlanic 0:02dd72d1d465 2181 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
borlanic 0:02dd72d1d465 2182 {
borlanic 0:02dd72d1d465 2183 *descriptor_l1 &= SECTION_P_MASK;
borlanic 0:02dd72d1d465 2184 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
borlanic 0:02dd72d1d465 2185 return 0;
borlanic 0:02dd72d1d465 2186 }
borlanic 0:02dd72d1d465 2187
borlanic 0:02dd72d1d465 2188 /** \brief Set 4k/64k page access privileges
borlanic 0:02dd72d1d465 2189
borlanic 0:02dd72d1d465 2190 \param [out] descriptor_l2 L2 descriptor.
borlanic 0:02dd72d1d465 2191 \param [in] user User Level Access: NO_ACCESS, RW, READ
borlanic 0:02dd72d1d465 2192 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
borlanic 0:02dd72d1d465 2193 \param [in] afe Access flag enable
borlanic 0:02dd72d1d465 2194
borlanic 0:02dd72d1d465 2195 \return 0
borlanic 0:02dd72d1d465 2196 */
borlanic 0:02dd72d1d465 2197 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
borlanic 0:02dd72d1d465 2198 {
borlanic 0:02dd72d1d465 2199 uint32_t ap = 0;
borlanic 0:02dd72d1d465 2200
borlanic 0:02dd72d1d465 2201 if (afe == 0) { //full access
borlanic 0:02dd72d1d465 2202 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
borlanic 0:02dd72d1d465 2203 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
borlanic 0:02dd72d1d465 2204 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
borlanic 0:02dd72d1d465 2205 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
borlanic 0:02dd72d1d465 2206 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
borlanic 0:02dd72d1d465 2207 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
borlanic 0:02dd72d1d465 2208 }
borlanic 0:02dd72d1d465 2209
borlanic 0:02dd72d1d465 2210 else { //Simplified access
borlanic 0:02dd72d1d465 2211 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
borlanic 0:02dd72d1d465 2212 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
borlanic 0:02dd72d1d465 2213 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
borlanic 0:02dd72d1d465 2214 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
borlanic 0:02dd72d1d465 2215 }
borlanic 0:02dd72d1d465 2216
borlanic 0:02dd72d1d465 2217 *descriptor_l2 &= PAGE_AP_MASK;
borlanic 0:02dd72d1d465 2218 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
borlanic 0:02dd72d1d465 2219 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
borlanic 0:02dd72d1d465 2220
borlanic 0:02dd72d1d465 2221 return 0;
borlanic 0:02dd72d1d465 2222 }
borlanic 0:02dd72d1d465 2223
borlanic 0:02dd72d1d465 2224 /** \brief Set 4k/64k page shareability
borlanic 0:02dd72d1d465 2225
borlanic 0:02dd72d1d465 2226 \param [out] descriptor_l2 L2 descriptor.
borlanic 0:02dd72d1d465 2227 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
borlanic 0:02dd72d1d465 2228
borlanic 0:02dd72d1d465 2229 \return 0
borlanic 0:02dd72d1d465 2230 */
borlanic 0:02dd72d1d465 2231 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
borlanic 0:02dd72d1d465 2232 {
borlanic 0:02dd72d1d465 2233 *descriptor_l2 &= PAGE_S_MASK;
borlanic 0:02dd72d1d465 2234 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
borlanic 0:02dd72d1d465 2235 return 0;
borlanic 0:02dd72d1d465 2236 }
borlanic 0:02dd72d1d465 2237
borlanic 0:02dd72d1d465 2238 /** \brief Set 4k/64k page Global attribute
borlanic 0:02dd72d1d465 2239
borlanic 0:02dd72d1d465 2240 \param [out] descriptor_l2 L2 descriptor.
borlanic 0:02dd72d1d465 2241 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
borlanic 0:02dd72d1d465 2242
borlanic 0:02dd72d1d465 2243 \return 0
borlanic 0:02dd72d1d465 2244 */
borlanic 0:02dd72d1d465 2245 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
borlanic 0:02dd72d1d465 2246 {
borlanic 0:02dd72d1d465 2247 *descriptor_l2 &= PAGE_NG_MASK;
borlanic 0:02dd72d1d465 2248 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
borlanic 0:02dd72d1d465 2249 return 0;
borlanic 0:02dd72d1d465 2250 }
borlanic 0:02dd72d1d465 2251
borlanic 0:02dd72d1d465 2252 /** \brief Set 4k/64k page Security attribute
borlanic 0:02dd72d1d465 2253
borlanic 0:02dd72d1d465 2254 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2255 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
borlanic 0:02dd72d1d465 2256
borlanic 0:02dd72d1d465 2257 \return 0
borlanic 0:02dd72d1d465 2258 */
borlanic 0:02dd72d1d465 2259 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
borlanic 0:02dd72d1d465 2260 {
borlanic 0:02dd72d1d465 2261 *descriptor_l1 &= PAGE_NS_MASK;
borlanic 0:02dd72d1d465 2262 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
borlanic 0:02dd72d1d465 2263 return 0;
borlanic 0:02dd72d1d465 2264 }
borlanic 0:02dd72d1d465 2265
borlanic 0:02dd72d1d465 2266 /** \brief Set Section memory attributes
borlanic 0:02dd72d1d465 2267
borlanic 0:02dd72d1d465 2268 \param [out] descriptor_l1 L1 descriptor.
borlanic 0:02dd72d1d465 2269 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
borlanic 0:02dd72d1d465 2270 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
borlanic 0:02dd72d1d465 2271 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
borlanic 0:02dd72d1d465 2272
borlanic 0:02dd72d1d465 2273 \return 0
borlanic 0:02dd72d1d465 2274 */
borlanic 0:02dd72d1d465 2275 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
borlanic 0:02dd72d1d465 2276 {
borlanic 0:02dd72d1d465 2277 *descriptor_l1 &= SECTION_TEXCB_MASK;
borlanic 0:02dd72d1d465 2278
borlanic 0:02dd72d1d465 2279 if (STRONGLY_ORDERED == mem)
borlanic 0:02dd72d1d465 2280 {
borlanic 0:02dd72d1d465 2281 return 0;
borlanic 0:02dd72d1d465 2282 }
borlanic 0:02dd72d1d465 2283 else if (SHARED_DEVICE == mem)
borlanic 0:02dd72d1d465 2284 {
borlanic 0:02dd72d1d465 2285 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
borlanic 0:02dd72d1d465 2286 }
borlanic 0:02dd72d1d465 2287 else if (NON_SHARED_DEVICE == mem)
borlanic 0:02dd72d1d465 2288 {
borlanic 0:02dd72d1d465 2289 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
borlanic 0:02dd72d1d465 2290 }
borlanic 0:02dd72d1d465 2291 else if (NORMAL == mem)
borlanic 0:02dd72d1d465 2292 {
borlanic 0:02dd72d1d465 2293 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
borlanic 0:02dd72d1d465 2294 switch(inner)
borlanic 0:02dd72d1d465 2295 {
borlanic 0:02dd72d1d465 2296 case NON_CACHEABLE:
borlanic 0:02dd72d1d465 2297 break;
borlanic 0:02dd72d1d465 2298 case WB_WA:
borlanic 0:02dd72d1d465 2299 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
borlanic 0:02dd72d1d465 2300 break;
borlanic 0:02dd72d1d465 2301 case WT:
borlanic 0:02dd72d1d465 2302 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
borlanic 0:02dd72d1d465 2303 break;
borlanic 0:02dd72d1d465 2304 case WB_NO_WA:
borlanic 0:02dd72d1d465 2305 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
borlanic 0:02dd72d1d465 2306 break;
borlanic 0:02dd72d1d465 2307 }
borlanic 0:02dd72d1d465 2308 switch(outer)
borlanic 0:02dd72d1d465 2309 {
borlanic 0:02dd72d1d465 2310 case NON_CACHEABLE:
borlanic 0:02dd72d1d465 2311 break;
borlanic 0:02dd72d1d465 2312 case WB_WA:
borlanic 0:02dd72d1d465 2313 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
borlanic 0:02dd72d1d465 2314 break;
borlanic 0:02dd72d1d465 2315 case WT:
borlanic 0:02dd72d1d465 2316 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
borlanic 0:02dd72d1d465 2317 break;
borlanic 0:02dd72d1d465 2318 case WB_NO_WA:
borlanic 0:02dd72d1d465 2319 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
borlanic 0:02dd72d1d465 2320 break;
borlanic 0:02dd72d1d465 2321 }
borlanic 0:02dd72d1d465 2322 }
borlanic 0:02dd72d1d465 2323 return 0;
borlanic 0:02dd72d1d465 2324 }
borlanic 0:02dd72d1d465 2325
borlanic 0:02dd72d1d465 2326 /** \brief Set 4k/64k page memory attributes
borlanic 0:02dd72d1d465 2327
borlanic 0:02dd72d1d465 2328 \param [out] descriptor_l2 L2 descriptor.
borlanic 0:02dd72d1d465 2329 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
borlanic 0:02dd72d1d465 2330 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
borlanic 0:02dd72d1d465 2331 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
borlanic 0:02dd72d1d465 2332 \param [in] page Page size
borlanic 0:02dd72d1d465 2333
borlanic 0:02dd72d1d465 2334 \return 0
borlanic 0:02dd72d1d465 2335 */
borlanic 0:02dd72d1d465 2336 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
borlanic 0:02dd72d1d465 2337 {
borlanic 0:02dd72d1d465 2338 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
borlanic 0:02dd72d1d465 2339
borlanic 0:02dd72d1d465 2340 if (page == PAGE_64k)
borlanic 0:02dd72d1d465 2341 {
borlanic 0:02dd72d1d465 2342 //same as section
borlanic 0:02dd72d1d465 2343 MMU_MemorySection(descriptor_l2, mem, outer, inner);
borlanic 0:02dd72d1d465 2344 }
borlanic 0:02dd72d1d465 2345 else
borlanic 0:02dd72d1d465 2346 {
borlanic 0:02dd72d1d465 2347 if (STRONGLY_ORDERED == mem)
borlanic 0:02dd72d1d465 2348 {
borlanic 0:02dd72d1d465 2349 return 0;
borlanic 0:02dd72d1d465 2350 }
borlanic 0:02dd72d1d465 2351 else if (SHARED_DEVICE == mem)
borlanic 0:02dd72d1d465 2352 {
borlanic 0:02dd72d1d465 2353 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
borlanic 0:02dd72d1d465 2354 }
borlanic 0:02dd72d1d465 2355 else if (NON_SHARED_DEVICE == mem)
borlanic 0:02dd72d1d465 2356 {
borlanic 0:02dd72d1d465 2357 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
borlanic 0:02dd72d1d465 2358 }
borlanic 0:02dd72d1d465 2359 else if (NORMAL == mem)
borlanic 0:02dd72d1d465 2360 {
borlanic 0:02dd72d1d465 2361 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
borlanic 0:02dd72d1d465 2362 switch(inner)
borlanic 0:02dd72d1d465 2363 {
borlanic 0:02dd72d1d465 2364 case NON_CACHEABLE:
borlanic 0:02dd72d1d465 2365 break;
borlanic 0:02dd72d1d465 2366 case WB_WA:
borlanic 0:02dd72d1d465 2367 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
borlanic 0:02dd72d1d465 2368 break;
borlanic 0:02dd72d1d465 2369 case WT:
borlanic 0:02dd72d1d465 2370 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
borlanic 0:02dd72d1d465 2371 break;
borlanic 0:02dd72d1d465 2372 case WB_NO_WA:
borlanic 0:02dd72d1d465 2373 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
borlanic 0:02dd72d1d465 2374 break;
borlanic 0:02dd72d1d465 2375 }
borlanic 0:02dd72d1d465 2376 switch(outer)
borlanic 0:02dd72d1d465 2377 {
borlanic 0:02dd72d1d465 2378 case NON_CACHEABLE:
borlanic 0:02dd72d1d465 2379 break;
borlanic 0:02dd72d1d465 2380 case WB_WA:
borlanic 0:02dd72d1d465 2381 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
borlanic 0:02dd72d1d465 2382 break;
borlanic 0:02dd72d1d465 2383 case WT:
borlanic 0:02dd72d1d465 2384 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
borlanic 0:02dd72d1d465 2385 break;
borlanic 0:02dd72d1d465 2386 case WB_NO_WA:
borlanic 0:02dd72d1d465 2387 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
borlanic 0:02dd72d1d465 2388 break;
borlanic 0:02dd72d1d465 2389 }
borlanic 0:02dd72d1d465 2390 }
borlanic 0:02dd72d1d465 2391 }
borlanic 0:02dd72d1d465 2392
borlanic 0:02dd72d1d465 2393 return 0;
borlanic 0:02dd72d1d465 2394 }
borlanic 0:02dd72d1d465 2395
borlanic 0:02dd72d1d465 2396 /** \brief Create a L1 section descriptor
borlanic 0:02dd72d1d465 2397
borlanic 0:02dd72d1d465 2398 \param [out] descriptor L1 descriptor
borlanic 0:02dd72d1d465 2399 \param [in] reg Section attributes
borlanic 0:02dd72d1d465 2400
borlanic 0:02dd72d1d465 2401 \return 0
borlanic 0:02dd72d1d465 2402 */
borlanic 0:02dd72d1d465 2403 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
borlanic 0:02dd72d1d465 2404 {
borlanic 0:02dd72d1d465 2405 *descriptor = 0;
borlanic 0:02dd72d1d465 2406
borlanic 0:02dd72d1d465 2407 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
borlanic 0:02dd72d1d465 2408 MMU_XNSection(descriptor,reg.xn_t);
borlanic 0:02dd72d1d465 2409 MMU_DomainSection(descriptor, reg.domain);
borlanic 0:02dd72d1d465 2410 MMU_PSection(descriptor, reg.e_t);
borlanic 0:02dd72d1d465 2411 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
borlanic 0:02dd72d1d465 2412 MMU_SharedSection(descriptor,reg.sh_t);
borlanic 0:02dd72d1d465 2413 MMU_GlobalSection(descriptor,reg.g_t);
borlanic 0:02dd72d1d465 2414 MMU_SecureSection(descriptor,reg.sec_t);
borlanic 0:02dd72d1d465 2415 *descriptor &= SECTION_MASK;
borlanic 0:02dd72d1d465 2416 *descriptor |= SECTION_DESCRIPTOR;
borlanic 0:02dd72d1d465 2417
borlanic 0:02dd72d1d465 2418 return 0;
borlanic 0:02dd72d1d465 2419 }
borlanic 0:02dd72d1d465 2420
borlanic 0:02dd72d1d465 2421
borlanic 0:02dd72d1d465 2422 /** \brief Create a L1 and L2 4k/64k page descriptor
borlanic 0:02dd72d1d465 2423
borlanic 0:02dd72d1d465 2424 \param [out] descriptor L1 descriptor
borlanic 0:02dd72d1d465 2425 \param [out] descriptor2 L2 descriptor
borlanic 0:02dd72d1d465 2426 \param [in] reg 4k/64k page attributes
borlanic 0:02dd72d1d465 2427
borlanic 0:02dd72d1d465 2428 \return 0
borlanic 0:02dd72d1d465 2429 */
borlanic 0:02dd72d1d465 2430 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
borlanic 0:02dd72d1d465 2431 {
borlanic 0:02dd72d1d465 2432 *descriptor = 0;
borlanic 0:02dd72d1d465 2433 *descriptor2 = 0;
borlanic 0:02dd72d1d465 2434
borlanic 0:02dd72d1d465 2435 switch (reg.rg_t)
borlanic 0:02dd72d1d465 2436 {
borlanic 0:02dd72d1d465 2437 case PAGE_4k:
borlanic 0:02dd72d1d465 2438 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
borlanic 0:02dd72d1d465 2439 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
borlanic 0:02dd72d1d465 2440 MMU_DomainPage(descriptor, reg.domain);
borlanic 0:02dd72d1d465 2441 MMU_PPage(descriptor, reg.e_t);
borlanic 0:02dd72d1d465 2442 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
borlanic 0:02dd72d1d465 2443 MMU_SharedPage(descriptor2,reg.sh_t);
borlanic 0:02dd72d1d465 2444 MMU_GlobalPage(descriptor2,reg.g_t);
borlanic 0:02dd72d1d465 2445 MMU_SecurePage(descriptor,reg.sec_t);
borlanic 0:02dd72d1d465 2446 *descriptor &= PAGE_L1_MASK;
borlanic 0:02dd72d1d465 2447 *descriptor |= PAGE_L1_DESCRIPTOR;
borlanic 0:02dd72d1d465 2448 *descriptor2 &= PAGE_L2_4K_MASK;
borlanic 0:02dd72d1d465 2449 *descriptor2 |= PAGE_L2_4K_DESC;
borlanic 0:02dd72d1d465 2450 break;
borlanic 0:02dd72d1d465 2451
borlanic 0:02dd72d1d465 2452 case PAGE_64k:
borlanic 0:02dd72d1d465 2453 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
borlanic 0:02dd72d1d465 2454 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
borlanic 0:02dd72d1d465 2455 MMU_DomainPage(descriptor, reg.domain);
borlanic 0:02dd72d1d465 2456 MMU_PPage(descriptor, reg.e_t);
borlanic 0:02dd72d1d465 2457 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
borlanic 0:02dd72d1d465 2458 MMU_SharedPage(descriptor2,reg.sh_t);
borlanic 0:02dd72d1d465 2459 MMU_GlobalPage(descriptor2,reg.g_t);
borlanic 0:02dd72d1d465 2460 MMU_SecurePage(descriptor,reg.sec_t);
borlanic 0:02dd72d1d465 2461 *descriptor &= PAGE_L1_MASK;
borlanic 0:02dd72d1d465 2462 *descriptor |= PAGE_L1_DESCRIPTOR;
borlanic 0:02dd72d1d465 2463 *descriptor2 &= PAGE_L2_64K_MASK;
borlanic 0:02dd72d1d465 2464 *descriptor2 |= PAGE_L2_64K_DESC;
borlanic 0:02dd72d1d465 2465 break;
borlanic 0:02dd72d1d465 2466
borlanic 0:02dd72d1d465 2467 case SECTION:
borlanic 0:02dd72d1d465 2468 //error
borlanic 0:02dd72d1d465 2469 break;
borlanic 0:02dd72d1d465 2470 }
borlanic 0:02dd72d1d465 2471
borlanic 0:02dd72d1d465 2472 return 0;
borlanic 0:02dd72d1d465 2473 }
borlanic 0:02dd72d1d465 2474
borlanic 0:02dd72d1d465 2475 /** \brief Create a 1MB Section
borlanic 0:02dd72d1d465 2476
borlanic 0:02dd72d1d465 2477 \param [in] ttb Translation table base address
borlanic 0:02dd72d1d465 2478 \param [in] base_address Section base address
borlanic 0:02dd72d1d465 2479 \param [in] count Number of sections to create
borlanic 0:02dd72d1d465 2480 \param [in] descriptor_l1 L1 descriptor (region attributes)
borlanic 0:02dd72d1d465 2481
borlanic 0:02dd72d1d465 2482 */
borlanic 0:02dd72d1d465 2483 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
borlanic 0:02dd72d1d465 2484 {
borlanic 0:02dd72d1d465 2485 uint32_t offset;
borlanic 0:02dd72d1d465 2486 uint32_t entry;
borlanic 0:02dd72d1d465 2487 uint32_t i;
borlanic 0:02dd72d1d465 2488
borlanic 0:02dd72d1d465 2489 offset = base_address >> 20;
borlanic 0:02dd72d1d465 2490 entry = (base_address & 0xFFF00000) | descriptor_l1;
borlanic 0:02dd72d1d465 2491
borlanic 0:02dd72d1d465 2492 //4 bytes aligned
borlanic 0:02dd72d1d465 2493 ttb = ttb + offset;
borlanic 0:02dd72d1d465 2494
borlanic 0:02dd72d1d465 2495 for (i = 0; i < count; i++ )
borlanic 0:02dd72d1d465 2496 {
borlanic 0:02dd72d1d465 2497 //4 bytes aligned
borlanic 0:02dd72d1d465 2498 *ttb++ = entry;
borlanic 0:02dd72d1d465 2499 entry += OFFSET_1M;
borlanic 0:02dd72d1d465 2500 }
borlanic 0:02dd72d1d465 2501 }
borlanic 0:02dd72d1d465 2502
borlanic 0:02dd72d1d465 2503 /** \brief Create a 4k page entry
borlanic 0:02dd72d1d465 2504
borlanic 0:02dd72d1d465 2505 \param [in] ttb L1 table base address
borlanic 0:02dd72d1d465 2506 \param [in] base_address 4k base address
borlanic 0:02dd72d1d465 2507 \param [in] count Number of 4k pages to create
borlanic 0:02dd72d1d465 2508 \param [in] descriptor_l1 L1 descriptor (region attributes)
borlanic 0:02dd72d1d465 2509 \param [in] ttb_l2 L2 table base address
borlanic 0:02dd72d1d465 2510 \param [in] descriptor_l2 L2 descriptor (region attributes)
borlanic 0:02dd72d1d465 2511
borlanic 0:02dd72d1d465 2512 */
borlanic 0:02dd72d1d465 2513 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
borlanic 0:02dd72d1d465 2514 {
borlanic 0:02dd72d1d465 2515
borlanic 0:02dd72d1d465 2516 uint32_t offset, offset2;
borlanic 0:02dd72d1d465 2517 uint32_t entry, entry2;
borlanic 0:02dd72d1d465 2518 uint32_t i;
borlanic 0:02dd72d1d465 2519
borlanic 0:02dd72d1d465 2520 offset = base_address >> 20;
borlanic 0:02dd72d1d465 2521 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
borlanic 0:02dd72d1d465 2522
borlanic 0:02dd72d1d465 2523 //4 bytes aligned
borlanic 0:02dd72d1d465 2524 ttb += offset;
borlanic 0:02dd72d1d465 2525 //create l1_entry
borlanic 0:02dd72d1d465 2526 *ttb = entry;
borlanic 0:02dd72d1d465 2527
borlanic 0:02dd72d1d465 2528 offset2 = (base_address & 0xff000) >> 12;
borlanic 0:02dd72d1d465 2529 ttb_l2 += offset2;
borlanic 0:02dd72d1d465 2530 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
borlanic 0:02dd72d1d465 2531 for (i = 0; i < count; i++ )
borlanic 0:02dd72d1d465 2532 {
borlanic 0:02dd72d1d465 2533 //4 bytes aligned
borlanic 0:02dd72d1d465 2534 *ttb_l2++ = entry2;
borlanic 0:02dd72d1d465 2535 entry2 += OFFSET_4K;
borlanic 0:02dd72d1d465 2536 }
borlanic 0:02dd72d1d465 2537 }
borlanic 0:02dd72d1d465 2538
borlanic 0:02dd72d1d465 2539 /** \brief Create a 64k page entry
borlanic 0:02dd72d1d465 2540
borlanic 0:02dd72d1d465 2541 \param [in] ttb L1 table base address
borlanic 0:02dd72d1d465 2542 \param [in] base_address 64k base address
borlanic 0:02dd72d1d465 2543 \param [in] count Number of 64k pages to create
borlanic 0:02dd72d1d465 2544 \param [in] descriptor_l1 L1 descriptor (region attributes)
borlanic 0:02dd72d1d465 2545 \param [in] ttb_l2 L2 table base address
borlanic 0:02dd72d1d465 2546 \param [in] descriptor_l2 L2 descriptor (region attributes)
borlanic 0:02dd72d1d465 2547
borlanic 0:02dd72d1d465 2548 */
borlanic 0:02dd72d1d465 2549 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
borlanic 0:02dd72d1d465 2550 {
borlanic 0:02dd72d1d465 2551 uint32_t offset, offset2;
borlanic 0:02dd72d1d465 2552 uint32_t entry, entry2;
borlanic 0:02dd72d1d465 2553 uint32_t i,j;
borlanic 0:02dd72d1d465 2554
borlanic 0:02dd72d1d465 2555
borlanic 0:02dd72d1d465 2556 offset = base_address >> 20;
borlanic 0:02dd72d1d465 2557 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
borlanic 0:02dd72d1d465 2558
borlanic 0:02dd72d1d465 2559 //4 bytes aligned
borlanic 0:02dd72d1d465 2560 ttb += offset;
borlanic 0:02dd72d1d465 2561 //create l1_entry
borlanic 0:02dd72d1d465 2562 *ttb = entry;
borlanic 0:02dd72d1d465 2563
borlanic 0:02dd72d1d465 2564 offset2 = (base_address & 0xff000) >> 12;
borlanic 0:02dd72d1d465 2565 ttb_l2 += offset2;
borlanic 0:02dd72d1d465 2566 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
borlanic 0:02dd72d1d465 2567 for (i = 0; i < count; i++ )
borlanic 0:02dd72d1d465 2568 {
borlanic 0:02dd72d1d465 2569 //create 16 entries
borlanic 0:02dd72d1d465 2570 for (j = 0; j < 16; j++)
borlanic 0:02dd72d1d465 2571 {
borlanic 0:02dd72d1d465 2572 //4 bytes aligned
borlanic 0:02dd72d1d465 2573 *ttb_l2++ = entry2;
borlanic 0:02dd72d1d465 2574 }
borlanic 0:02dd72d1d465 2575 entry2 += OFFSET_64K;
borlanic 0:02dd72d1d465 2576 }
borlanic 0:02dd72d1d465 2577 }
borlanic 0:02dd72d1d465 2578
borlanic 0:02dd72d1d465 2579 /** \brief Enable MMU
borlanic 0:02dd72d1d465 2580 */
borlanic 0:02dd72d1d465 2581 __STATIC_INLINE void MMU_Enable(void)
borlanic 0:02dd72d1d465 2582 {
borlanic 0:02dd72d1d465 2583 // Set M bit 0 to enable the MMU
borlanic 0:02dd72d1d465 2584 // Set AFE bit to enable simplified access permissions model
borlanic 0:02dd72d1d465 2585 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
borlanic 0:02dd72d1d465 2586 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
borlanic 0:02dd72d1d465 2587 __ISB();
borlanic 0:02dd72d1d465 2588 }
borlanic 0:02dd72d1d465 2589
borlanic 0:02dd72d1d465 2590 /** \brief Disable MMU
borlanic 0:02dd72d1d465 2591 */
borlanic 0:02dd72d1d465 2592 __STATIC_INLINE void MMU_Disable(void)
borlanic 0:02dd72d1d465 2593 {
borlanic 0:02dd72d1d465 2594 // Clear M bit 0 to disable the MMU
borlanic 0:02dd72d1d465 2595 __set_SCTLR( __get_SCTLR() & ~1);
borlanic 0:02dd72d1d465 2596 __ISB();
borlanic 0:02dd72d1d465 2597 }
borlanic 0:02dd72d1d465 2598
borlanic 0:02dd72d1d465 2599 /** \brief Invalidate entire unified TLB
borlanic 0:02dd72d1d465 2600 */
borlanic 0:02dd72d1d465 2601
borlanic 0:02dd72d1d465 2602 __STATIC_INLINE void MMU_InvalidateTLB(void)
borlanic 0:02dd72d1d465 2603 {
borlanic 0:02dd72d1d465 2604 __set_TLBIALL(0);
borlanic 0:02dd72d1d465 2605 __DSB(); //ensure completion of the invalidation
borlanic 0:02dd72d1d465 2606 __ISB(); //ensure instruction fetch path sees new state
borlanic 0:02dd72d1d465 2607 }
borlanic 0:02dd72d1d465 2608
borlanic 0:02dd72d1d465 2609
borlanic 0:02dd72d1d465 2610 #ifdef __cplusplus
borlanic 0:02dd72d1d465 2611 }
borlanic 0:02dd72d1d465 2612 #endif
borlanic 0:02dd72d1d465 2613
borlanic 0:02dd72d1d465 2614 #endif /* __CORE_CA_H_DEPENDANT */
borlanic 0:02dd72d1d465 2615
borlanic 0:02dd72d1d465 2616 #endif /* __CMSIS_GENERIC */