BA / Mbed OS BaBoRo1

Erste version der Software für der Prototyp

mbed-os/targets/TARGET_STM/mbed_rtx.h@4:75df35ef4fb6, 2018-03-30 (annotated)

Committer:
borlanic
Date:
Fri Mar 30 14:07:05 2018 +0000
Revision:
4:75df35ef4fb6
Parent:
0:380207fcb5c1 
commentar

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borlanic 0:380207fcb5c1 1 /* mbed Microcontroller Library
borlanic 0:380207fcb5c1 2 * Copyright (c) 2017 ARM Limited
borlanic 0:380207fcb5c1 3 *
borlanic 0:380207fcb5c1 4 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:380207fcb5c1 5 * you may not use this file except in compliance with the License.
borlanic 0:380207fcb5c1 6 * You may obtain a copy of the License at
borlanic 0:380207fcb5c1 7 *
borlanic 0:380207fcb5c1 8 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:380207fcb5c1 9 *
borlanic 0:380207fcb5c1 10 * Unless required by applicable law or agreed to in writing, software
borlanic 0:380207fcb5c1 11 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:380207fcb5c1 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:380207fcb5c1 13 * See the License for the specific language governing permissions and
borlanic 0:380207fcb5c1 14 * limitations under the License.
borlanic 0:380207fcb5c1 15 */
borlanic 0:380207fcb5c1 16
borlanic 0:380207fcb5c1 17 #ifndef MBED_MBED_RTX_H
borlanic 0:380207fcb5c1 18 #define MBED_MBED_RTX_H
borlanic 0:380207fcb5c1 19
borlanic 0:380207fcb5c1 20 #ifndef INITIAL_SP
borlanic 0:380207fcb5c1 21
borlanic 0:380207fcb5c1 22 #if (defined(TARGET_STM32L475VG) ||\
borlanic 0:380207fcb5c1 23 defined(TARGET_STM32L476RG) ||\
borlanic 0:380207fcb5c1 24 defined(TARGET_STM32L476JG) ||\
borlanic 0:380207fcb5c1 25 defined(TARGET_STM32L476VG) ||\
borlanic 0:380207fcb5c1 26 defined(TARGET_STM32L486RG))
borlanic 0:380207fcb5c1 27 /* only GCC_ARM and IAR toolchains have the stack on SRAM2 */
borlanic 0:380207fcb5c1 28 #if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\
borlanic 0:380207fcb5c1 29 defined(__IAR_SYSTEMS_ICC__ )) &&\
borlanic 0:380207fcb5c1 30 defined(TWO_RAM_REGIONS))
borlanic 0:380207fcb5c1 31 #define INITIAL_SP (0x10008000UL)
borlanic 0:380207fcb5c1 32 #else
borlanic 0:380207fcb5c1 33 #define INITIAL_SP (0x20018000UL)
borlanic 0:380207fcb5c1 34 #endif /* toolchains */
borlanic 0:380207fcb5c1 35
borlanic 0:380207fcb5c1 36 #elif (defined(TARGET_STM32F051R8) ||\
borlanic 0:380207fcb5c1 37 defined(TARGET_STM32F100RB) ||\
borlanic 0:380207fcb5c1 38 defined(TARGET_STM32L031K6) ||\
borlanic 0:380207fcb5c1 39 defined(TARGET_STM32L053C8) ||\
borlanic 0:380207fcb5c1 40 defined(TARGET_STM32L053R8))
borlanic 0:380207fcb5c1 41 #define INITIAL_SP (0x20002000UL)
borlanic 0:380207fcb5c1 42
borlanic 0:380207fcb5c1 43 #elif (defined(TARGET_STM32F303K8) ||\
borlanic 0:380207fcb5c1 44 defined(TARGET_STM32F334C8) ||\
borlanic 0:380207fcb5c1 45 defined(TARGET_STM32F334R8))
borlanic 0:380207fcb5c1 46 #define INITIAL_SP (0x20003000UL)
borlanic 0:380207fcb5c1 47
borlanic 0:380207fcb5c1 48 #elif (defined(TARGET_STM32F070RB) ||\
borlanic 0:380207fcb5c1 49 defined(TARGET_STM32F072RB) ||\
borlanic 0:380207fcb5c1 50 defined(TARGET_STM32F302R8))
borlanic 0:380207fcb5c1 51 #define INITIAL_SP (0x20004000UL)
borlanic 0:380207fcb5c1 52
borlanic 0:380207fcb5c1 53 #elif (defined(TARGET_STM32F103RB) ||\
borlanic 0:380207fcb5c1 54 defined(TARGET_STM32F103C8) ||\
borlanic 0:380207fcb5c1 55 defined(TARGET_STM32L072CZ) ||\
borlanic 0:380207fcb5c1 56 defined(TARGET_STM32L073RZ) ||\
borlanic 0:380207fcb5c1 57 defined(TARGET_STM32L0x2xZ))
borlanic 0:380207fcb5c1 58 #define INITIAL_SP (0x20005000UL)
borlanic 0:380207fcb5c1 59
borlanic 0:380207fcb5c1 60 #elif (defined(TARGET_STM32F091RC) ||\
borlanic 0:380207fcb5c1 61 defined(TARGET_STM32F410RB) ||\
borlanic 4:75df35ef4fb6 62 defined(TARGET_STM32L151CBA)||\
borlanic 0:380207fcb5c1 63 defined(TARGET_STM32L151CC) ||\
borlanic 0:380207fcb5c1 64 defined(TARGET_STM32L151RC) ||\
borlanic 0:380207fcb5c1 65 defined(TARGET_STM32L152RC))
borlanic 0:380207fcb5c1 66 #define INITIAL_SP (0x20008000UL)
borlanic 0:380207fcb5c1 67
borlanic 0:380207fcb5c1 68 #elif defined(TARGET_STM32F303VC)
borlanic 0:380207fcb5c1 69 #define INITIAL_SP (0x2000A000UL)
borlanic 0:380207fcb5c1 70
borlanic 0:380207fcb5c1 71 #elif defined(TARGET_STM32L443RC)
borlanic 0:380207fcb5c1 72 #define INITIAL_SP (0x2000C000UL)
borlanic 0:380207fcb5c1 73
borlanic 0:380207fcb5c1 74 #elif defined(TARGET_STM32L432KC) ||\
borlanic 0:380207fcb5c1 75 defined (TARGET_STM32L433RC)
borlanic 0:380207fcb5c1 76 #define INITIAL_SP (0x20010000UL)
borlanic 0:380207fcb5c1 77
borlanic 0:380207fcb5c1 78 #elif (defined(TARGET_STM32F303RE) ||\
borlanic 0:380207fcb5c1 79 defined(TARGET_STM32F303ZE) ||\
borlanic 0:380207fcb5c1 80 defined(TARGET_STM32F401VC))
borlanic 0:380207fcb5c1 81 #define INITIAL_SP (0x20010000UL)
borlanic 0:380207fcb5c1 82
borlanic 0:380207fcb5c1 83 #elif defined(TARGET_STM32L152RE)
borlanic 0:380207fcb5c1 84 #define INITIAL_SP (0x20014000UL)
borlanic 0:380207fcb5c1 85
borlanic 0:380207fcb5c1 86 #elif (defined(TARGET_STM32F401RE) ||\
borlanic 0:380207fcb5c1 87 defined(TARGET_STM32F401VE))
borlanic 0:380207fcb5c1 88 #define INITIAL_SP (0x20018000UL)
borlanic 0:380207fcb5c1 89
borlanic 0:380207fcb5c1 90 #elif (defined(TARGET_STM32F207ZG) ||\
borlanic 0:380207fcb5c1 91 defined(TARGET_STM32F405RG) ||\
borlanic 0:380207fcb5c1 92 defined(TARGET_STM32F407VG) ||\
borlanic 0:380207fcb5c1 93 defined(TARGET_STM32F411RE) ||\
borlanic 0:380207fcb5c1 94 defined(TARGET_STM32F446RE) ||\
borlanic 0:380207fcb5c1 95 defined(TARGET_STM32F446VE) ||\
borlanic 0:380207fcb5c1 96 defined(TARGET_STM32F446ZE))
borlanic 0:380207fcb5c1 97 #define INITIAL_SP (0x20020000UL)
borlanic 0:380207fcb5c1 98
borlanic 0:380207fcb5c1 99 #elif (defined(TARGET_STM32F429ZI) ||\
borlanic 0:380207fcb5c1 100 defined(TARGET_STM32F437VG) ||\
borlanic 0:380207fcb5c1 101 defined(TARGET_STM32F439ZI))
borlanic 0:380207fcb5c1 102 #define INITIAL_SP (0x20030000UL)
borlanic 0:380207fcb5c1 103
borlanic 0:380207fcb5c1 104 #elif defined(TARGET_STM32F412ZG)
borlanic 0:380207fcb5c1 105 #define INITIAL_SP (0x20040000UL)
borlanic 0:380207fcb5c1 106
borlanic 0:380207fcb5c1 107 #elif (defined(TARGET_STM32F413ZH) ||\
borlanic 0:380207fcb5c1 108 defined(TARGET_STM32F469NI) ||\
borlanic 0:380207fcb5c1 109 defined(TARGET_STM32F746NG) ||\
borlanic 0:380207fcb5c1 110 defined(TARGET_STM32F746ZG) ||\
borlanic 0:380207fcb5c1 111 defined(TARGET_STM32F756ZG) ||\
borlanic 0:380207fcb5c1 112 defined(TARGET_STM32L496AG) ||\
borlanic 0:380207fcb5c1 113 defined(TARGET_STM32L496ZG))
borlanic 0:380207fcb5c1 114 #define INITIAL_SP (0x20050000UL)
borlanic 0:380207fcb5c1 115
borlanic 0:380207fcb5c1 116 #elif (defined(TARGET_STM32F767ZI) ||\
borlanic 0:380207fcb5c1 117 defined(TARGET_STM32F769NI))
borlanic 0:380207fcb5c1 118 #define INITIAL_SP (0x20080000UL)
borlanic 0:380207fcb5c1 119
borlanic 0:380207fcb5c1 120 #else
borlanic 0:380207fcb5c1 121 #error "INITIAL_SP is not defined for this target in the mbed_rtx.h file"
borlanic 0:380207fcb5c1 122 #endif
borlanic 0:380207fcb5c1 123
borlanic 0:380207fcb5c1 124 #endif // INITIAL_SP
borlanic 0:380207fcb5c1 125 #if (defined(__GNUC__) && !defined(__CC_ARM) && defined(TWO_RAM_REGIONS))
borlanic 0:380207fcb5c1 126 extern uint32_t __StackLimit[];
borlanic 0:380207fcb5c1 127 extern uint32_t __StackTop[];
borlanic 0:380207fcb5c1 128 extern uint32_t __end__[];
borlanic 0:380207fcb5c1 129 extern uint32_t __HeapLimit[];
borlanic 0:380207fcb5c1 130 #define HEAP_START ((unsigned char*)__end__)
borlanic 0:380207fcb5c1 131 #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
borlanic 0:380207fcb5c1 132 #define ISR_STACK_START ((unsigned char*)__StackLimit)
borlanic 0:380207fcb5c1 133 #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
borlanic 0:380207fcb5c1 134 #endif
borlanic 0:380207fcb5c1 135
borlanic 0:380207fcb5c1 136 #endif // MBED_MBED_RTX_H