BA / Mbed OS BaBoRo1

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mbed-os/hal/spi_api.h@4:75df35ef4fb6, 2018-03-30 (annotated)

Committer:
borlanic
Date:
Fri Mar 30 14:07:05 2018 +0000
Revision:
4:75df35ef4fb6
Parent:
0:380207fcb5c1 
commentar

Who changed what in which revision?

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borlanic 0:380207fcb5c1 1
borlanic 0:380207fcb5c1 2 /** \addtogroup hal */
borlanic 0:380207fcb5c1 3 /** @{*/
borlanic 0:380207fcb5c1 4 /* mbed Microcontroller Library
borlanic 0:380207fcb5c1 5 * Copyright (c) 2006-2013 ARM Limited
borlanic 0:380207fcb5c1 6 *
borlanic 0:380207fcb5c1 7 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:380207fcb5c1 8 * you may not use this file except in compliance with the License.
borlanic 0:380207fcb5c1 9 * You may obtain a copy of the License at
borlanic 0:380207fcb5c1 10 *
borlanic 0:380207fcb5c1 11 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:380207fcb5c1 12 *
borlanic 0:380207fcb5c1 13 * Unless required by applicable law or agreed to in writing, software
borlanic 0:380207fcb5c1 14 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:380207fcb5c1 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:380207fcb5c1 16 * See the License for the specific language governing permissions and
borlanic 0:380207fcb5c1 17 * limitations under the License.
borlanic 0:380207fcb5c1 18 */
borlanic 0:380207fcb5c1 19 #ifndef MBED_SPI_API_H
borlanic 0:380207fcb5c1 20 #define MBED_SPI_API_H
borlanic 0:380207fcb5c1 21
borlanic 0:380207fcb5c1 22 #include "device.h"
borlanic 0:380207fcb5c1 23 #include "hal/dma_api.h"
borlanic 0:380207fcb5c1 24 #include "hal/buffer.h"
borlanic 0:380207fcb5c1 25
borlanic 0:380207fcb5c1 26 #if DEVICE_SPI
borlanic 0:380207fcb5c1 27
borlanic 0:380207fcb5c1 28 #define SPI_EVENT_ERROR (1 << 1)
borlanic 0:380207fcb5c1 29 #define SPI_EVENT_COMPLETE (1 << 2)
borlanic 0:380207fcb5c1 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
borlanic 0:380207fcb5c1 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
borlanic 0:380207fcb5c1 32
borlanic 0:380207fcb5c1 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
borlanic 0:380207fcb5c1 34
borlanic 0:380207fcb5c1 35 #define SPI_FILL_WORD (0xFFFF)
borlanic 0:380207fcb5c1 36 #define SPI_FILL_CHAR (0xFF)
borlanic 0:380207fcb5c1 37
borlanic 0:380207fcb5c1 38 #if DEVICE_SPI_ASYNCH
borlanic 0:380207fcb5c1 39 /** Asynch SPI HAL structure
borlanic 0:380207fcb5c1 40 */
borlanic 0:380207fcb5c1 41 typedef struct {
borlanic 0:380207fcb5c1 42 struct spi_s spi; /**< Target specific SPI structure */
borlanic 0:380207fcb5c1 43 struct buffer_s tx_buff; /**< Tx buffer */
borlanic 0:380207fcb5c1 44 struct buffer_s rx_buff; /**< Rx buffer */
borlanic 0:380207fcb5c1 45 } spi_t;
borlanic 0:380207fcb5c1 46
borlanic 0:380207fcb5c1 47 #else
borlanic 0:380207fcb5c1 48 /** Non-asynch SPI HAL structure
borlanic 0:380207fcb5c1 49 */
borlanic 0:380207fcb5c1 50 typedef struct spi_s spi_t;
borlanic 0:380207fcb5c1 51
borlanic 0:380207fcb5c1 52 #endif
borlanic 0:380207fcb5c1 53
borlanic 0:380207fcb5c1 54 #ifdef __cplusplus
borlanic 0:380207fcb5c1 55 extern "C" {
borlanic 0:380207fcb5c1 56 #endif
borlanic 0:380207fcb5c1 57
borlanic 0:380207fcb5c1 58 /**
borlanic 0:380207fcb5c1 59 * \defgroup hal_GeneralSPI SPI Configuration Functions
borlanic 0:380207fcb5c1 60 * @{
borlanic 0:380207fcb5c1 61 */
borlanic 0:380207fcb5c1 62
borlanic 0:380207fcb5c1 63 /** Initialize the SPI peripheral
borlanic 0:380207fcb5c1 64 *
borlanic 0:380207fcb5c1 65 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
borlanic 0:380207fcb5c1 66 * @param[out] obj The SPI object to initialize
borlanic 0:380207fcb5c1 67 * @param[in] mosi The pin to use for MOSI
borlanic 0:380207fcb5c1 68 * @param[in] miso The pin to use for MISO
borlanic 0:380207fcb5c1 69 * @param[in] sclk The pin to use for SCLK
borlanic 0:380207fcb5c1 70 * @param[in] ssel The pin to use for SSEL
borlanic 0:380207fcb5c1 71 */
borlanic 0:380207fcb5c1 72 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
borlanic 0:380207fcb5c1 73
borlanic 0:380207fcb5c1 74 /** Release a SPI object
borlanic 0:380207fcb5c1 75 *
borlanic 0:380207fcb5c1 76 * TODO: spi_free is currently unimplemented
borlanic 0:380207fcb5c1 77 * This will require reference counting at the C++ level to be safe
borlanic 0:380207fcb5c1 78 *
borlanic 0:380207fcb5c1 79 * Return the pins owned by the SPI object to their reset state
borlanic 0:380207fcb5c1 80 * Disable the SPI peripheral
borlanic 0:380207fcb5c1 81 * Disable the SPI clock
borlanic 0:380207fcb5c1 82 * @param[in] obj The SPI object to deinitialize
borlanic 0:380207fcb5c1 83 */
borlanic 0:380207fcb5c1 84 void spi_free(spi_t *obj);
borlanic 0:380207fcb5c1 85
borlanic 0:380207fcb5c1 86 /** Configure the SPI format
borlanic 0:380207fcb5c1 87 *
borlanic 0:380207fcb5c1 88 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
borlanic 0:380207fcb5c1 89 * The default bit order is MSB.
borlanic 0:380207fcb5c1 90 * @param[in,out] obj The SPI object to configure
borlanic 0:380207fcb5c1 91 * @param[in] bits The number of bits per frame
borlanic 0:380207fcb5c1 92 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
borlanic 0:380207fcb5c1 93 * @param[in] slave Zero for master mode or non-zero for slave mode
borlanic 0:380207fcb5c1 94 */
borlanic 0:380207fcb5c1 95 void spi_format(spi_t *obj, int bits, int mode, int slave);
borlanic 0:380207fcb5c1 96
borlanic 0:380207fcb5c1 97 /** Set the SPI baud rate
borlanic 0:380207fcb5c1 98 *
borlanic 0:380207fcb5c1 99 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
borlanic 0:380207fcb5c1 100 * Configures the SPI peripheral's baud rate
borlanic 0:380207fcb5c1 101 * @param[in,out] obj The SPI object to configure
borlanic 0:380207fcb5c1 102 * @param[in] hz The baud rate in Hz
borlanic 0:380207fcb5c1 103 */
borlanic 0:380207fcb5c1 104 void spi_frequency(spi_t *obj, int hz);
borlanic 0:380207fcb5c1 105
borlanic 0:380207fcb5c1 106 /**@}*/
borlanic 0:380207fcb5c1 107 /**
borlanic 0:380207fcb5c1 108 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
borlanic 0:380207fcb5c1 109 * @{
borlanic 0:380207fcb5c1 110 */
borlanic 0:380207fcb5c1 111
borlanic 0:380207fcb5c1 112 /** Write a byte out in master mode and receive a value
borlanic 0:380207fcb5c1 113 *
borlanic 0:380207fcb5c1 114 * @param[in] obj The SPI peripheral to use for sending
borlanic 0:380207fcb5c1 115 * @param[in] value The value to send
borlanic 0:380207fcb5c1 116 * @return Returns the value received during send
borlanic 0:380207fcb5c1 117 */
borlanic 0:380207fcb5c1 118 int spi_master_write(spi_t *obj, int value);
borlanic 0:380207fcb5c1 119
borlanic 0:380207fcb5c1 120 /** Write a block out in master mode and receive a value
borlanic 0:380207fcb5c1 121 *
borlanic 0:380207fcb5c1 122 * The total number of bytes sent and received will be the maximum of
borlanic 0:380207fcb5c1 123 * tx_length and rx_length. The bytes written will be padded with the
borlanic 0:380207fcb5c1 124 * value 0xff.
borlanic 0:380207fcb5c1 125 *
borlanic 0:380207fcb5c1 126 * @param[in] obj The SPI peripheral to use for sending
borlanic 0:380207fcb5c1 127 * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
borlanic 0:380207fcb5c1 128 * @param[in] tx_length Number of bytes to write, may be zero
borlanic 0:380207fcb5c1 129 * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
borlanic 0:380207fcb5c1 130 * @param[in] rx_length Number of bytes to read, may be zero
borlanic 0:380207fcb5c1 131 * @param[in] write_fill Default data transmitted while performing a read
borlanic 0:380207fcb5c1 132 * @returns
borlanic 0:380207fcb5c1 133 * The number of bytes written and read from the device. This is
borlanic 0:380207fcb5c1 134 * maximum of tx_length and rx_length.
borlanic 0:380207fcb5c1 135 */
borlanic 0:380207fcb5c1 136 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
borlanic 0:380207fcb5c1 137
borlanic 0:380207fcb5c1 138 /** Check if a value is available to read
borlanic 0:380207fcb5c1 139 *
borlanic 0:380207fcb5c1 140 * @param[in] obj The SPI peripheral to check
borlanic 0:380207fcb5c1 141 * @return non-zero if a value is available
borlanic 0:380207fcb5c1 142 */
borlanic 0:380207fcb5c1 143 int spi_slave_receive(spi_t *obj);
borlanic 0:380207fcb5c1 144
borlanic 0:380207fcb5c1 145 /** Get a received value out of the SPI receive buffer in slave mode
borlanic 0:380207fcb5c1 146 *
borlanic 0:380207fcb5c1 147 * Blocks until a value is available
borlanic 0:380207fcb5c1 148 * @param[in] obj The SPI peripheral to read
borlanic 0:380207fcb5c1 149 * @return The value received
borlanic 0:380207fcb5c1 150 */
borlanic 0:380207fcb5c1 151 int spi_slave_read(spi_t *obj);
borlanic 0:380207fcb5c1 152
borlanic 0:380207fcb5c1 153 /** Write a value to the SPI peripheral in slave mode
borlanic 0:380207fcb5c1 154 *
borlanic 0:380207fcb5c1 155 * Blocks until the SPI peripheral can be written to
borlanic 0:380207fcb5c1 156 * @param[in] obj The SPI peripheral to write
borlanic 0:380207fcb5c1 157 * @param[in] value The value to write
borlanic 0:380207fcb5c1 158 */
borlanic 0:380207fcb5c1 159 void spi_slave_write(spi_t *obj, int value);
borlanic 0:380207fcb5c1 160
borlanic 0:380207fcb5c1 161 /** Checks if the specified SPI peripheral is in use
borlanic 0:380207fcb5c1 162 *
borlanic 0:380207fcb5c1 163 * @param[in] obj The SPI peripheral to check
borlanic 0:380207fcb5c1 164 * @return non-zero if the peripheral is currently transmitting
borlanic 0:380207fcb5c1 165 */
borlanic 0:380207fcb5c1 166 int spi_busy(spi_t *obj);
borlanic 0:380207fcb5c1 167
borlanic 0:380207fcb5c1 168 /** Get the module number
borlanic 0:380207fcb5c1 169 *
borlanic 0:380207fcb5c1 170 * @param[in] obj The SPI peripheral to check
borlanic 0:380207fcb5c1 171 * @return The module number
borlanic 0:380207fcb5c1 172 */
borlanic 0:380207fcb5c1 173 uint8_t spi_get_module(spi_t *obj);
borlanic 0:380207fcb5c1 174
borlanic 0:380207fcb5c1 175 /**@}*/
borlanic 0:380207fcb5c1 176
borlanic 0:380207fcb5c1 177 #if DEVICE_SPI_ASYNCH
borlanic 0:380207fcb5c1 178 /**
borlanic 0:380207fcb5c1 179 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
borlanic 0:380207fcb5c1 180 * @{
borlanic 0:380207fcb5c1 181 */
borlanic 0:380207fcb5c1 182
borlanic 0:380207fcb5c1 183 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
borlanic 0:380207fcb5c1 184 *
borlanic 0:380207fcb5c1 185 * @param[in] obj The SPI object that holds the transfer information
borlanic 0:380207fcb5c1 186 * @param[in] tx The transmit buffer
borlanic 0:380207fcb5c1 187 * @param[in] tx_length The number of bytes to transmit
borlanic 0:380207fcb5c1 188 * @param[in] rx The receive buffer
borlanic 0:380207fcb5c1 189 * @param[in] rx_length The number of bytes to receive
borlanic 0:380207fcb5c1 190 * @param[in] bit_width The bit width of buffer words
borlanic 0:380207fcb5c1 191 * @param[in] event The logical OR of events to be registered
borlanic 0:380207fcb5c1 192 * @param[in] handler SPI interrupt handler
borlanic 0:380207fcb5c1 193 * @param[in] hint A suggestion for how to use DMA with this transfer
borlanic 0:380207fcb5c1 194 */
borlanic 0:380207fcb5c1 195 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
borlanic 0:380207fcb5c1 196
borlanic 0:380207fcb5c1 197 /** The asynchronous IRQ handler
borlanic 0:380207fcb5c1 198 *
borlanic 0:380207fcb5c1 199 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
borlanic 0:380207fcb5c1 200 * conditions, such as buffer overflows or transfer complete.
borlanic 0:380207fcb5c1 201 * @param[in] obj The SPI object that holds the transfer information
borlanic 0:380207fcb5c1 202 * @return Event flags if a transfer termination condition was met; otherwise 0.
borlanic 0:380207fcb5c1 203 */
borlanic 0:380207fcb5c1 204 uint32_t spi_irq_handler_asynch(spi_t *obj);
borlanic 0:380207fcb5c1 205
borlanic 0:380207fcb5c1 206 /** Attempts to determine if the SPI peripheral is already in use
borlanic 0:380207fcb5c1 207 *
borlanic 0:380207fcb5c1 208 * If a temporary DMA channel has been allocated, peripheral is in use.
borlanic 0:380207fcb5c1 209 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
borlanic 0:380207fcb5c1 210 * channel were allocated.
borlanic 0:380207fcb5c1 211 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
borlanic 0:380207fcb5c1 212 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
borlanic 0:380207fcb5c1 213 * there are any bytes in the FIFOs.
borlanic 0:380207fcb5c1 214 * @param[in] obj The SPI object to check for activity
borlanic 0:380207fcb5c1 215 * @return Non-zero if the SPI port is active or zero if it is not.
borlanic 0:380207fcb5c1 216 */
borlanic 0:380207fcb5c1 217 uint8_t spi_active(spi_t *obj);
borlanic 0:380207fcb5c1 218
borlanic 0:380207fcb5c1 219 /** Abort an SPI transfer
borlanic 0:380207fcb5c1 220 *
borlanic 0:380207fcb5c1 221 * @param obj The SPI peripheral to stop
borlanic 0:380207fcb5c1 222 */
borlanic 0:380207fcb5c1 223 void spi_abort_asynch(spi_t *obj);
borlanic 0:380207fcb5c1 224
borlanic 0:380207fcb5c1 225
borlanic 0:380207fcb5c1 226 #endif
borlanic 0:380207fcb5c1 227
borlanic 0:380207fcb5c1 228 /**@}*/
borlanic 0:380207fcb5c1 229
borlanic 0:380207fcb5c1 230 #ifdef __cplusplus
borlanic 0:380207fcb5c1 231 }
borlanic 0:380207fcb5c1 232 #endif // __cplusplus
borlanic 0:380207fcb5c1 233
borlanic 0:380207fcb5c1 234 #endif // SPI_DEVICE
borlanic 0:380207fcb5c1 235
borlanic 0:380207fcb5c1 236 #endif // MBED_SPI_API_H
borlanic 0:380207fcb5c1 237
borlanic 0:380207fcb5c1 238 /** @}*/