Added support for the WNC M14A2A Cellular LTE Data Module.
Dependencies: WNC14A2AInterface
AT86RFReg.h
00001 /* 00002 * Copyright (c) 2014-2015 ARM Limited. All rights reserved. 00003 * SPDX-License-Identifier: Apache-2.0 00004 * Licensed under the Apache License, Version 2.0 (the License); you may 00005 * not use this file except in compliance with the License. 00006 * You may obtain a copy of the License at 00007 * 00008 * http://www.apache.org/licenses/LICENSE-2.0 00009 * 00010 * Unless required by applicable law or agreed to in writing, software 00011 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00012 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00013 * See the License for the specific language governing permissions and 00014 * limitations under the License. 00015 */ 00016 00017 #ifndef AT86RFREG_H_ 00018 #define AT86RFREG_H_ 00019 #ifdef __cplusplus 00020 extern "C" { 00021 #endif 00022 00023 /*AT86RF212 PHY Modes*/ 00024 #define BPSK_20 0x00 00025 #define BPSK_40 0x04 00026 #define BPSK_40_ALT 0x14 00027 #define OQPSK_SIN_RC_100 0x08 00028 #define OQPSK_SIN_RC_200 0x09 00029 #define OQPSK_RC_100 0x18 00030 #define OQPSK_RC_200 0x19 00031 #define OQPSK_SIN_250 0x0c 00032 #define OQPSK_SIN_500 0x0d 00033 #define OQPSK_SIN_500_ALT 0x0f 00034 #define OQPSK_RC_250 0x1c 00035 #define OQPSK_RC_500 0x1d 00036 #define OQPSK_RC_500_ALT 0x1f 00037 #define OQPSK_SIN_RC_400_SCR_ON 0x2A 00038 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A 00039 #define OQPSK_RC_400_SCR_ON 0x3A 00040 #define OQPSK_RC_400_SCR_OFF 0x1A 00041 #define OQPSK_SIN_1000_SCR_ON 0x2E 00042 #define OQPSK_SIN_1000_SCR_OFF 0x0E 00043 #define OQPSK_RC_1000_SCR_ON 0x3E 00044 #define OQPSK_RC_1000_SCR_OFF 0x1E 00045 00046 /*Supported transceivers*/ 00047 #define PART_AT86RF231 0x03 00048 #define PART_AT86RF212 0x07 00049 #define PART_AT86RF233 0x0B 00050 #define VERSION_AT86RF212 0x01 00051 #define VERSION_AT86RF212B 0x03 00052 00053 /*RF Configuration Registers*/ 00054 #define TRX_STATUS 0x01 00055 #define TRX_STATE 0x02 00056 #define TRX_CTRL_0 0x03 00057 #define TRX_CTRL_1 0x04 00058 #define PHY_TX_PWR 0x05 00059 #define PHY_RSSI 0x06 00060 #define PHY_ED_LEVEL 0x07 00061 #define PHY_CC_CCA 0x08 00062 #define RX_CTRL 0x0A 00063 #define SFD_VALUE 0x0B 00064 #define TRX_CTRL_2 0x0C 00065 #define ANT_DIV 0x0D 00066 #define IRQ_MASK 0x0E 00067 #define IRQ_STATUS 0x0F 00068 #define VREG_CTRL 0x10 00069 #define BATMON 0x11 00070 #define XOSC_CTRL 0x12 00071 #define CC_CTRL_0 0x13 00072 #define CC_CTRL_1 0x14 00073 #define RX_SYN 0x15 00074 #define TRX_RPC 0x16 00075 #define RF_CTRL_0 0x16 00076 #define XAH_CTRL_1 0x17 00077 #define FTN_CTRL 0x18 00078 #define PLL_CF 0x1A 00079 #define PLL_DCU 0x1B 00080 #define PART_NUM 0x1C 00081 #define VERSION_NUM 0x1D 00082 #define MAN_ID_0 0x1E 00083 #define MAN_ID_1 0x1F 00084 #define SHORT_ADDR_0 0x20 00085 #define SHORT_ADDR_1 0x21 00086 #define PAN_ID_0 0x22 00087 #define PAN_ID_1 0x23 00088 #define IEEE_ADDR_0 0x24 00089 #define IEEE_ADDR_1 0x25 00090 #define IEEE_ADDR_2 0x26 00091 #define IEEE_ADDR_3 0x27 00092 #define IEEE_ADDR_4 0x28 00093 #define IEEE_ADDR_5 0x29 00094 #define IEEE_ADDR_6 0x2A 00095 #define IEEE_ADDR_7 0x2B 00096 #define XAH_CTRL_0 0x2C 00097 #define CSMA_SEED_0 0x2D 00098 #define CSMA_SEED_1 0x2E 00099 #define CSMA_BE 0x2F 00100 00101 /* CSMA_SEED_1*/ 00102 #define AACK_FVN_MODE1 7 00103 #define AACK_FVN_MODE0 6 00104 #define AACK_SET_PD 5 00105 #define AACK_DIS_ACK 4 00106 #define AACK_I_AM_COORD 3 00107 #define CSMA_SEED_12 2 00108 #define CSMA_SEED_11 1 00109 #define CSMA_SEED_10 0 00110 00111 /*TRX_STATUS bits*/ 00112 #define CCA_STATUS 0x40 00113 #define CCA_DONE 0x80 00114 00115 /*PHY_CC_CCA bits*/ 00116 #define CCA_REQUEST 0x80 00117 #define CCA_MODE_1 0x20 00118 #define CCA_MODE_3 0x60 00119 00120 /*IRQ_MASK bits*/ 00121 #define RX_START 0x04 00122 #define TRX_END 0x08 00123 #define CCA_ED_DONE 0x10 00124 #define AMI 0x20 00125 #define TRX_UR 0x40 00126 00127 /*ANT_DIV bits*/ 00128 #define ANT_DIV_EN 0x08 00129 #define ANT_EXT_SW_EN 0x04 00130 #define ANT_CTRL_DEFAULT 0x03 00131 00132 /*TRX_CTRL_1 bits*/ 00133 #define PA_EXT_EN 0x80 00134 00135 /*FTN_CTRL bits*/ 00136 #define FTN_START 0x80 00137 00138 /*PHY_RSSI bits*/ 00139 #define CRC_VALID 0x80 00140 00141 /*RX_SYN bits*/ 00142 #define RX_PDT_DIS 0x80 00143 00144 /*TRX_RPC bits */ 00145 #define RX_RPC_CTRL 0xC0 00146 #define RX_RPC_EN 0x20 00147 #define PDT_RPC_EN 0x10 00148 #define PLL_RPC_EN 0x08 00149 #define XAH_TX_RPC_EN 0x04 00150 #define IPAN_RPC_EN 0x02 00151 #define TRX_RPC_RSVD_1 0x01 00152 00153 /*XAH_CTRL_1 bits*/ 00154 #define AACK_PROM_MODE 0x02 00155 00156 00157 #ifdef __cplusplus 00158 } 00159 #endif 00160 00161 #endif /* AT86RFREG_H_ */
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