Winbond W25Q32 SPI library. Tested on Winbond W74M32 embedded on Hani-IoT. Based on https://os.mbed.com/users/perezalvarezhi/code/W25Q80BV/
W25Q32.cpp@0:cc8118fdcc22, 2020-01-08 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Wed Jan 08 11:13:52 2020 +0100
- Revision:
- 0:cc8118fdcc22
- Child:
- 1:d3928deefb53
initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Pawel Zarembski |
0:cc8118fdcc22 | 1 | #include"W25Q32.h" |
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0:cc8118fdcc22 | 2 | |
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0:cc8118fdcc22 | 3 | W25Q32::W25Q32(PinName mosi, PinName miso, PinName sclk, PinName cs) : _cs(cs),_mosi(mosi),_miso(miso),_sclk(sclk){ |
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0:cc8118fdcc22 | 4 | |
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0:cc8118fdcc22 | 5 | } |
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0:cc8118fdcc22 | 6 | |
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0:cc8118fdcc22 | 7 | int W25Q80BV::getMID() |
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0:cc8118fdcc22 | 8 | { |
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0:cc8118fdcc22 | 9 | int ID = 0; |
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0:cc8118fdcc22 | 10 | chipEnable(); |
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0:cc8118fdcc22 | 11 | this->writeSPI(DEV_ID); |
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0:cc8118fdcc22 | 12 | this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 13 | this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 14 | this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 15 | this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 16 | ID = this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 17 | chipDisable(); |
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0:cc8118fdcc22 | 18 | return ID; |
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0:cc8118fdcc22 | 19 | } |
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0:cc8118fdcc22 | 20 | |
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0:cc8118fdcc22 | 21 | int W25Q80BV::readByte(int addr) |
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0:cc8118fdcc22 | 22 | { |
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0:cc8118fdcc22 | 23 | chipEnable(); |
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0:cc8118fdcc22 | 24 | this->writeSPI(READ_DATA); |
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0:cc8118fdcc22 | 25 | this->writeSPI((addr & ADDR_BMASK2) >> ADDR_BSHIFT2); |
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0:cc8118fdcc22 | 26 | this->writeSPI((addr & ADDR_BMASK1) >> ADDR_BSHIFT1); |
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0:cc8118fdcc22 | 27 | this->writeSPI((addr & ADDR_BMASK0) >> ADDR_BSHIFT0); |
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0:cc8118fdcc22 | 28 | int response = this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 29 | chipDisable(); |
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0:cc8118fdcc22 | 30 | return response; |
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0:cc8118fdcc22 | 31 | } |
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0:cc8118fdcc22 | 32 | |
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0:cc8118fdcc22 | 33 | int W25Q80BV::readByte(int a2, int a1, int a0) |
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0:cc8118fdcc22 | 34 | { |
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0:cc8118fdcc22 | 35 | chipEnable(); |
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0:cc8118fdcc22 | 36 | this->writeSPI(READ_DATA); |
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0:cc8118fdcc22 | 37 | this->writeSPI(a2); |
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0:cc8118fdcc22 | 38 | this->writeSPI(a1); |
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0:cc8118fdcc22 | 39 | this->writeSPI(a0); |
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0:cc8118fdcc22 | 40 | int response = this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 41 | chipDisable(); |
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0:cc8118fdcc22 | 42 | return response; |
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0:cc8118fdcc22 | 43 | } |
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0:cc8118fdcc22 | 44 | void W25Q80BV::readStream(int addr, char* buf, int count) |
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0:cc8118fdcc22 | 45 | { |
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0:cc8118fdcc22 | 46 | if (count < 1) { |
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0:cc8118fdcc22 | 47 | return; |
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0:cc8118fdcc22 | 48 | } |
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0:cc8118fdcc22 | 49 | |
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0:cc8118fdcc22 | 50 | chipEnable(); |
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0:cc8118fdcc22 | 51 | this->writeSPI(READ_DATA); |
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0:cc8118fdcc22 | 52 | this->writeSPI((addr & ADDR_BMASK2) >> ADDR_BSHIFT2); |
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0:cc8118fdcc22 | 53 | this->writeSPI((addr & ADDR_BMASK1) >> ADDR_BSHIFT1); |
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0:cc8118fdcc22 | 54 | this->writeSPI((addr & ADDR_BMASK0) >> ADDR_BSHIFT0); |
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0:cc8118fdcc22 | 55 | |
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0:cc8118fdcc22 | 56 | for (int i = 0; i < count; i++) { |
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0:cc8118fdcc22 | 57 | buf[i] = this->writeSPI(DUMMY_ADDR); |
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0:cc8118fdcc22 | 58 | } |
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0:cc8118fdcc22 | 59 | |
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0:cc8118fdcc22 | 60 | chipDisable(); |
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0:cc8118fdcc22 | 61 | } |
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0:cc8118fdcc22 | 62 | |
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0:cc8118fdcc22 | 63 | void W25Q80BV::writeByte(int addr, int data) |
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0:cc8118fdcc22 | 64 | { |
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0:cc8118fdcc22 | 65 | writeEnable(); |
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0:cc8118fdcc22 | 66 | chipEnable(); |
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0:cc8118fdcc22 | 67 | this->writeSPI(WRITE_DATA); |
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0:cc8118fdcc22 | 68 | this->writeSPI((addr & ADDR_BMASK2) >> ADDR_BSHIFT2); |
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0:cc8118fdcc22 | 69 | this->writeSPI((addr & ADDR_BMASK1) >> ADDR_BSHIFT1); |
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0:cc8118fdcc22 | 70 | this->writeSPI((addr & ADDR_BMASK0) >> ADDR_BSHIFT0); |
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0:cc8118fdcc22 | 71 | this->writeSPI(data); |
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0:cc8118fdcc22 | 72 | chipDisable(); |
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0:cc8118fdcc22 | 73 | writeDisable(); |
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0:cc8118fdcc22 | 74 | thread_sleep_for(WAIT_TIME); |
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0:cc8118fdcc22 | 75 | } |
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0:cc8118fdcc22 | 76 | |
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0:cc8118fdcc22 | 77 | void W25Q80BV::writeByte(int a2, int a1, int a0, int data) |
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0:cc8118fdcc22 | 78 | { |
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0:cc8118fdcc22 | 79 | writeEnable(); |
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0:cc8118fdcc22 | 80 | chipEnable(); |
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0:cc8118fdcc22 | 81 | this->writeSPI(WRITE_DATA); |
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0:cc8118fdcc22 | 82 | this->writeSPI(a2); |
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0:cc8118fdcc22 | 83 | this->writeSPI(a1); |
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0:cc8118fdcc22 | 84 | this->writeSPI(a0); |
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0:cc8118fdcc22 | 85 | this->writeSPI(data); |
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0:cc8118fdcc22 | 86 | chipDisable(); |
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0:cc8118fdcc22 | 87 | writeDisable(); |
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0:cc8118fdcc22 | 88 | thread_sleep_for(WAIT_TIME); |
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0:cc8118fdcc22 | 89 | } |
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0:cc8118fdcc22 | 90 | |
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0:cc8118fdcc22 | 91 | void W25Q80BV::writeStream(int addr, char* buf, int count) { |
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0:cc8118fdcc22 | 92 | if (count < 1) { |
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0:cc8118fdcc22 | 93 | return; |
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0:cc8118fdcc22 | 94 | } |
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0:cc8118fdcc22 | 95 | |
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0:cc8118fdcc22 | 96 | writeEnable(); |
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0:cc8118fdcc22 | 97 | chipEnable(); |
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0:cc8118fdcc22 | 98 | this->writeSPI(WRITE_DATA); |
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0:cc8118fdcc22 | 99 | this->writeSPI((addr & ADDR_BMASK2) >> ADDR_BSHIFT2); |
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0:cc8118fdcc22 | 100 | this->writeSPI((addr & ADDR_BMASK1) >> ADDR_BSHIFT1); |
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0:cc8118fdcc22 | 101 | this->writeSPI((addr & ADDR_BMASK0) >> ADDR_BSHIFT0); |
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0:cc8118fdcc22 | 102 | |
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0:cc8118fdcc22 | 103 | for (int i = 0; i < count; i++) { |
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0:cc8118fdcc22 | 104 | this->writeSPI(buf[i]); |
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0:cc8118fdcc22 | 105 | } |
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0:cc8118fdcc22 | 106 | |
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0:cc8118fdcc22 | 107 | chipDisable(); |
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0:cc8118fdcc22 | 108 | writeDisable(); |
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0:cc8118fdcc22 | 109 | thread_sleep_for(WAIT_TIME); |
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0:cc8118fdcc22 | 110 | } |
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0:cc8118fdcc22 | 111 | |
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0:cc8118fdcc22 | 112 | void W25Q80BV::chipErase() |
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0:cc8118fdcc22 | 113 | { |
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0:cc8118fdcc22 | 114 | writeEnable(); |
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0:cc8118fdcc22 | 115 | chipEnable(); |
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0:cc8118fdcc22 | 116 | this->writeSPI(CHIP_ERASE); |
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0:cc8118fdcc22 | 117 | chipDisable(); |
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0:cc8118fdcc22 | 118 | writeDisable(); |
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0:cc8118fdcc22 | 119 | thread_sleep_for(WAIT_TIME); |
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0:cc8118fdcc22 | 120 | } |
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0:cc8118fdcc22 | 121 | |
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0:cc8118fdcc22 | 122 | void W25Q80BV::writeEnable() |
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0:cc8118fdcc22 | 123 | { |
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0:cc8118fdcc22 | 124 | chipEnable(); |
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0:cc8118fdcc22 | 125 | this->writeSPI(WRITE_ENABLE); |
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0:cc8118fdcc22 | 126 | chipDisable(); |
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0:cc8118fdcc22 | 127 | } |
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0:cc8118fdcc22 | 128 | |
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0:cc8118fdcc22 | 129 | void W25Q80BV::writeDisable() |
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0:cc8118fdcc22 | 130 | { |
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0:cc8118fdcc22 | 131 | chipEnable(); |
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0:cc8118fdcc22 | 132 | this->writeSPI(WRITE_DISABLE); |
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0:cc8118fdcc22 | 133 | chipDisable(); |
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0:cc8118fdcc22 | 134 | } |
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0:cc8118fdcc22 | 135 | |
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0:cc8118fdcc22 | 136 | void W25Q80BV::chipEnable() |
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0:cc8118fdcc22 | 137 | { |
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0:cc8118fdcc22 | 138 | _cs = 0; |
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0:cc8118fdcc22 | 139 | } |
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0:cc8118fdcc22 | 140 | |
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0:cc8118fdcc22 | 141 | void W25Q80BV::chipDisable() |
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0:cc8118fdcc22 | 142 | { |
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0:cc8118fdcc22 | 143 | _cs = 1; |
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0:cc8118fdcc22 | 144 | } |
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0:cc8118fdcc22 | 145 | |
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0:cc8118fdcc22 | 146 | // Sends and receives 1 byte of SPI data MSB endianness |
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0:cc8118fdcc22 | 147 | int W25Q80BV::writeSPI(int data){ |
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0:cc8118fdcc22 | 148 | int i; |
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0:cc8118fdcc22 | 149 | int aux = 0; |
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0:cc8118fdcc22 | 150 | int aux2 = 0; |
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0:cc8118fdcc22 | 151 | int read = 0; |
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0:cc8118fdcc22 | 152 | |
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0:cc8118fdcc22 | 153 | for (i = 0; i<8; i++) { |
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0:cc8118fdcc22 | 154 | _sclk = 0; |
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0:cc8118fdcc22 | 155 | aux = data&0x80; |
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0:cc8118fdcc22 | 156 | aux >>= 7; |
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0:cc8118fdcc22 | 157 | _mosi = aux; |
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0:cc8118fdcc22 | 158 | data <<= 1; |
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0:cc8118fdcc22 | 159 | |
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0:cc8118fdcc22 | 160 | // input |
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0:cc8118fdcc22 | 161 | _sclk = 1; |
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0:cc8118fdcc22 | 162 | |
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0:cc8118fdcc22 | 163 | read <<= 1; |
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0:cc8118fdcc22 | 164 | aux2 = _miso; |
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0:cc8118fdcc22 | 165 | read |= aux2; |
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0:cc8118fdcc22 | 166 | } |
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0:cc8118fdcc22 | 167 | |
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0:cc8118fdcc22 | 168 | _sclk = 0; |
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0:cc8118fdcc22 | 169 | return read; |
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0:cc8118fdcc22 | 170 | } |