tc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_TC_COMPONENT_
00031 #define _SAM3U_TC_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Timer Counter */
00035 /* ============================================================================= */
00036 /** \addtogroup SAM3U_TC Timer Counter */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief TcChannel hardware registers */
00041 typedef struct {
00042   RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
00043   RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
00044   RoReg      Reserved1[2];
00045   RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
00046   RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
00047   RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
00048   RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
00049   RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
00050   RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
00051   RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
00052   RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
00053   RoReg      Reserved2[4];
00054 } TcChannel;
00055 /** \brief Tc hardware registers */
00056 #define TCCHANNEL_NUMBER 3
00057 typedef struct {
00058   TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
00059   WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
00060   RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
00061   WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
00062   WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
00063   RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
00064   RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
00065 } Tc;
00066 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00067 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
00068 #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
00069 #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
00070 #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
00071 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
00072 #define TC_CMR_TCCLKS_Pos 0
00073 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
00074 #define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
00075 #define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
00076 #define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
00077 #define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
00078 #define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
00079 #define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
00080 #define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
00081 #define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
00082 #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
00083 #define TC_CMR_BURST_Pos 4
00084 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
00085 #define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
00086 #define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
00087 #define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
00088 #define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
00089 #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
00090 #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
00091 #define TC_CMR_ETRGEDG_Pos 8
00092 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
00093 #define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
00094 #define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
00095 #define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
00096 #define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
00097 #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
00098 #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
00099 #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
00100 #define TC_CMR_LDRA_Pos 16
00101 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
00102 #define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
00103 #define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
00104 #define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
00105 #define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
00106 #define TC_CMR_LDRB_Pos 18
00107 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
00108 #define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
00109 #define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
00110 #define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
00111 #define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
00112 #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
00113 #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
00114 #define TC_CMR_EEVTEDG_Pos 8
00115 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
00116 #define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
00117 #define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
00118 #define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
00119 #define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
00120 #define TC_CMR_EEVT_Pos 10
00121 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
00122 #define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
00123 #define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
00124 #define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
00125 #define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
00126 #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
00127 #define TC_CMR_WAVSEL_Pos 13
00128 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
00129 #define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
00130 #define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
00131 #define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
00132 #define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
00133 #define TC_CMR_ACPA_Pos 16
00134 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
00135 #define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
00136 #define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
00137 #define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
00138 #define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
00139 #define TC_CMR_ACPC_Pos 18
00140 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
00141 #define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
00142 #define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
00143 #define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
00144 #define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
00145 #define TC_CMR_AEEVT_Pos 20
00146 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
00147 #define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
00148 #define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
00149 #define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
00150 #define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
00151 #define TC_CMR_ASWTRG_Pos 22
00152 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
00153 #define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
00154 #define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
00155 #define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
00156 #define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
00157 #define TC_CMR_BCPB_Pos 24
00158 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
00159 #define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
00160 #define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
00161 #define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
00162 #define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
00163 #define TC_CMR_BCPC_Pos 26
00164 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
00165 #define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
00166 #define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
00167 #define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
00168 #define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
00169 #define TC_CMR_BEEVT_Pos 28
00170 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
00171 #define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
00172 #define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
00173 #define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
00174 #define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
00175 #define TC_CMR_BSWTRG_Pos 30
00176 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
00177 #define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
00178 #define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
00179 #define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
00180 #define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
00181 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
00182 #define TC_CV_CV_Pos 0
00183 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
00184 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */
00185 #define TC_RA_RA_Pos 0
00186 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
00187 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
00188 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */
00189 #define TC_RB_RB_Pos 0
00190 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
00191 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
00192 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */
00193 #define TC_RC_RC_Pos 0
00194 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
00195 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
00196 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
00197 #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
00198 #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
00199 #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
00200 #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
00201 #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
00202 #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
00203 #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
00204 #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
00205 #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
00206 #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
00207 #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
00208 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
00209 #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
00210 #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
00211 #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
00212 #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
00213 #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
00214 #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
00215 #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
00216 #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
00217 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
00218 #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
00219 #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
00220 #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
00221 #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
00222 #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
00223 #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
00224 #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
00225 #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
00226 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
00227 #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
00228 #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
00229 #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
00230 #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
00231 #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
00232 #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
00233 #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
00234 #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
00235 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
00236 #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
00237 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
00238 #define TC_BMR_TC0XC0S_Pos 0
00239 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
00240 #define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
00241 #define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
00242 #define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
00243 #define TC_BMR_TC1XC1S_Pos 2
00244 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
00245 #define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
00246 #define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
00247 #define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
00248 #define TC_BMR_TC2XC2S_Pos 4
00249 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
00250 #define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
00251 #define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
00252 #define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
00253 #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
00254 #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
00255 #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
00256 #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
00257 #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
00258 #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
00259 #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
00260 #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
00261 #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
00262 #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
00263 #define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
00264 #define TC_BMR_MAXFILT_Pos 20
00265 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
00266 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
00267 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
00268 #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
00269 #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
00270 #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
00271 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
00272 #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
00273 #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
00274 #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
00275 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
00276 #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
00277 #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
00278 #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
00279 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
00280 #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
00281 #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
00282 #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
00283 #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */
00284 
00285 /*@}*/
00286 
00287 
00288 #endif /* _SAM3U_TC_COMPONENT_ */