system_MK20D5.c

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           ARM Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manuals:   K20P64M50SF0RM Rev. 1, Oct 2011
00009 **                          K20P32M50SF0RM Rev. 1, Oct 2011
00010 **                          K20P48M50SF0RM Rev. 1, Oct 2011
00011 **
00012 **     Version:             rev. 1.0, 2011-12-15
00013 **
00014 **     Abstract:
00015 **         Provides a system configuration function and a global variable that
00016 **         contains the system frequency. It configures the device and initializes
00017 **         the oscillator (PLL) that is part of the microcontroller device.
00018 **
00019 **     Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
00020 **
00021 **     http:                 www.freescale.com
00022 **     mail:                 support@freescale.com
00023 **
00024 **     Revisions:
00025 **     - rev. 1.0 (2011-12-15)
00026 **         Initial version
00027 **
00028 ** ###################################################################
00029 */
00030 
00031 /**
00032  * @file MK20D5
00033  * @version 1.0
00034  * @date 2011-12-15
00035  * @brief Device specific configuration file for MK20D5 (implementation file)
00036  *
00037  * Provides a system configuration function and a global variable that contains
00038  * the system frequency. It configures the device and initializes the oscillator
00039  * (PLL) that is part of the microcontroller device.
00040  */
00041 
00042 #include "stdint.h"
00043 #include "MK20D5.h"
00044 
00045 #define DISABLE_WDOG    1
00046 
00047 #define CLOCK_SETUP     1
00048 /* Predefined clock setups
00049    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
00050          Reference clock source for MCG module is the slow internal clock source 32.768kHz
00051          Core clock = 41.94MHz, BusClock = 41.94MHz
00052    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
00053          Reference clock source for MCG module is an external crystal 8MHz
00054          Core clock = 48MHz, BusClock = 48MHz
00055    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
00056          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
00057          Core clock = 8MHz, BusClock = 8MHz
00058 */
00059 
00060 /*----------------------------------------------------------------------------
00061   Define clock source values
00062  *----------------------------------------------------------------------------*/
00063 #if (CLOCK_SETUP == 0)
00064     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00065     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
00066     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00067     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00068     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
00069 #elif (CLOCK_SETUP == 1)
00070     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00071     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
00072     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00073     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00074     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
00075 #elif (CLOCK_SETUP == 2)
00076     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00077     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
00078     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00079     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00080     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
00081 #endif /* (CLOCK_SETUP == 2) */
00082 
00083 
00084 /* ----------------------------------------------------------------------------
00085    -- Core clock
00086    ---------------------------------------------------------------------------- */
00087 
00088 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00089 
00090 /* ----------------------------------------------------------------------------
00091    -- SystemInit()
00092    ---------------------------------------------------------------------------- */
00093 
00094 void SystemInit (void) {
00095 #if (DISABLE_WDOG)
00096   /* Disable the WDOG module */
00097   /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
00098   WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
00099   /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
00100   WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
00101   /* WDOG_STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
00102   WDOG->STCTRLH = (uint16_t)0x01D2u;
00103 #endif /* (DISABLE_WDOG) */
00104 #if (CLOCK_SETUP == 0)
00105   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
00106   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
00107   /* Switch to FEI Mode */
00108   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00109   MCG->C1 = (uint8_t)0x06u;
00110   /* MCG->C2: ?=0,?=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
00111   MCG->C2 = (uint8_t)0x00u;
00112   /* MCG_C4: DMX32=0,DRST_DRS=1 */
00113   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
00114   /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
00115   MCG->C5 = (uint8_t)0x00u;
00116   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
00117   MCG->C6 = (uint8_t)0x00u;
00118   while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
00119   }
00120   while((MCG->S & 0x0Cu) != 0x00u) {    /* Wait until output of the FLL is selected */
00121   }
00122 #elif (CLOCK_SETUP == 1)
00123   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
00124   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
00125   /* Switch to FBE Mode */
00126   /* OSC0->CR: ERCLKEN=0,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00127   OSC0->CR = (uint8_t)0x00u;
00128   /* MCG->C7: OSCSEL=0 */
00129   MCG->C7 = (uint8_t)0x00u;
00130   /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
00131   MCG->C2 = (uint8_t)0x24u;
00132   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00133   MCG->C1 = (uint8_t)0x9Au;
00134   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00135   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
00136   /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
00137   MCG->C5 = (uint8_t)0x03u;
00138   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
00139   MCG->C6 = (uint8_t)0x00u;
00140   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
00141   }
00142 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
00143   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
00144   }
00145 #endif
00146   while((MCG->S & 0x0Cu) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
00147   }
00148   /* Switch to PBE Mode */
00149   /* MCG_C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
00150   MCG->C5 = (uint8_t)0x03u;
00151   /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
00152   MCG->C6 = (uint8_t)0x40u;
00153   while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
00154   }
00155   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
00156   }
00157   /* Switch to PEE Mode */
00158   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00159   MCG->C1 = (uint8_t)0x1Au;
00160   while((MCG->S & 0x0Cu) != 0x0Cu) {    /* Wait until output of the PLL is selected */
00161   }
00162   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
00163   }
00164 #elif (CLOCK_SETUP == 2)
00165   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
00166   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
00167   /* Switch to FBE Mode */
00168   /* OSC0->CR: ERCLKEN=0,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00169   OSC0->CR = (uint8_t)0x00u;
00170   /* MCG->C7: OSCSEL=0 */
00171   MCG->C7 = (uint8_t)0x00u;
00172   /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
00173   MCG->C2 = (uint8_t)0x24u;
00174   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00175   MCG->C1 = (uint8_t)0x9Au;
00176   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00177   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
00178   /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
00179   MCG->C5 = (uint8_t)0x00u;
00180   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
00181   MCG->C6 = (uint8_t)0x00u;
00182   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
00183   }
00184 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
00185   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
00186   }
00187 #endif
00188   while((MCG->S & 0x0CU) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
00189   }
00190   /* Switch to BLPE Mode */
00191   /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
00192   MCG->C2 = (uint8_t)0x24u;
00193 #endif /* (CLOCK_SETUP == 2) */
00194 
00195 #if defined(OFFSET_VTABLE_32K)
00196   SCB->VTOR = 0x8000u;
00197 #elif defined(OFFSET_VTABLE_20K)
00198   SCB->VTOR = 0x5000u;
00199 #endif
00200 }
00201 
00202 /* ----------------------------------------------------------------------------
00203    -- SystemCoreClockUpdate()
00204    ---------------------------------------------------------------------------- */
00205 
00206 void SystemCoreClockUpdate (void) {
00207   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
00208   uint8_t Divider;
00209 
00210   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
00211     /* Output of FLL or PLL is selected */
00212     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
00213       /* FLL is selected */
00214       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
00215         /* External reference clock is selected */
00216         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
00217           MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
00218         } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
00219           MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
00220         } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
00221         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00222         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
00223         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
00224           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
00225         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
00226       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00227         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
00228       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00229       /* Select correct multiplier to calculate the MCG output clock  */
00230       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
00231         case 0x0u:
00232           MCGOUTClock *= 640u;
00233           break;
00234         case 0x20u:
00235           MCGOUTClock *= 1280u;
00236           break;
00237         case 0x40u:
00238           MCGOUTClock *= 1920u;
00239           break;
00240         case 0x60u:
00241           MCGOUTClock *= 2560u;
00242           break;
00243         case 0x80u:
00244           MCGOUTClock *= 732u;
00245           break;
00246         case 0xA0u:
00247           MCGOUTClock *= 1464u;
00248           break;
00249         case 0xC0u:
00250           MCGOUTClock *= 2197u;
00251           break;
00252         case 0xE0u:
00253           MCGOUTClock *= 2929u;
00254           break;
00255         default:
00256           break;
00257       }
00258     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00259       /* PLL is selected */
00260       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
00261       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
00262       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
00263       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
00264     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00265   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
00266     /* Internal reference clock is selected */
00267     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
00268       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
00269     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00270       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
00271     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00272   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
00273     /* External reference clock is selected */
00274     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
00275       MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
00276     } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
00277       MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
00278     } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
00279   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00280     /* Reserved value */
00281     return;
00282   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00283   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
00284 }