Data Fields |
| __IO uint32_t | PWD |
| | USB PHY Power-Down Register, offset: 0x0.
|
| __IO uint32_t | PWD_SET |
| | USB PHY Power-Down Register, offset: 0x4.
|
| __IO uint32_t | PWD_CLR |
| | USB PHY Power-Down Register, offset: 0x8.
|
| __IO uint32_t | PWD_TOG |
| | USB PHY Power-Down Register, offset: 0xC.
|
| __IO uint32_t | TX |
| | USB PHY Transmitter Control Register, offset: 0x10.
|
| __IO uint32_t | TX_SET |
| | USB PHY Transmitter Control Register, offset: 0x14.
|
| __IO uint32_t | TX_CLR |
| | USB PHY Transmitter Control Register, offset: 0x18.
|
| __IO uint32_t | TX_TOG |
| | USB PHY Transmitter Control Register, offset: 0x1C.
|
| __IO uint32_t | RX |
| | USB PHY Receiver Control Register, offset: 0x20.
|
| __IO uint32_t | RX_SET |
| | USB PHY Receiver Control Register, offset: 0x24.
|
| __IO uint32_t | RX_CLR |
| | USB PHY Receiver Control Register, offset: 0x28.
|
| __IO uint32_t | RX_TOG |
| | USB PHY Receiver Control Register, offset: 0x2C.
|
| __IO uint32_t | CTRL |
| | USB PHY General Control Register, offset: 0x30.
|
| __IO uint32_t | CTRL_SET |
| | USB PHY General Control Register, offset: 0x34.
|
| __IO uint32_t | CTRL_CLR |
| | USB PHY General Control Register, offset: 0x38.
|
| __IO uint32_t | CTRL_TOG |
| | USB PHY General Control Register, offset: 0x3C.
|
| __IO uint32_t | STATUS |
| | USB PHY Status Register, offset: 0x40.
|
| __IO uint32_t | DEBUGr |
| | USB PHY Debug Register, offset: 0x50.
|
| __IO uint32_t | DEBUG_SET |
| | USB PHY Debug Register, offset: 0x54.
|
| __IO uint32_t | DEBUG_CLR |
| | USB PHY Debug Register, offset: 0x58.
|
| __IO uint32_t | DEBUG_TOG |
| | USB PHY Debug Register, offset: 0x5C.
|
| __I uint32_t | DEBUG0_STATUS |
| | UTMI Debug Status Register 0, offset: 0x60.
|
| __IO uint32_t | DEBUG1 |
| | UTMI Debug Status Register 1, offset: 0x70.
|
| __IO uint32_t | DEBUG1_SET |
| | UTMI Debug Status Register 1, offset: 0x74.
|
| __IO uint32_t | DEBUG1_CLR |
| | UTMI Debug Status Register 1, offset: 0x78.
|
| __IO uint32_t | DEBUG1_TOG |
| | UTMI Debug Status Register 1, offset: 0x7C.
|
| __I uint32_t | VERSION |
| | UTMI RTL Version, offset: 0x80.
|
| __IO uint32_t | PLL_SIC |
| | USB PHY PLL Control/Status Register, offset: 0xA0.
|
| __IO uint32_t | PLL_SIC_SET |
| | USB PHY PLL Control/Status Register, offset: 0xA4.
|
| __IO uint32_t | PLL_SIC_CLR |
| | USB PHY PLL Control/Status Register, offset: 0xA8.
|
| __IO uint32_t | PLL_SIC_TOG |
| | USB PHY PLL Control/Status Register, offset: 0xAC.
|
| __IO uint32_t | USB1_VBUS_DETECT |
| | USB PHY VBUS Detect Control Register, offset: 0xC0.
|
| __IO uint32_t | USB1_VBUS_DETECT_SET |
| | USB PHY VBUS Detect Control Register, offset: 0xC4.
|
| __IO uint32_t | USB1_VBUS_DETECT_CLR |
| | USB PHY VBUS Detect Control Register, offset: 0xC8.
|
| __IO uint32_t | USB1_VBUS_DETECT_TOG |
| | USB PHY VBUS Detect Control Register, offset: 0xCC.
|
| __I uint32_t | USB1_VBUS_DET_STAT |
| | USB PHY VBUS Detector Status Register, offset: 0xD0.
|
| __I uint32_t | USB1_CHRG_DET_STAT |
| | USB PHY Charger Detect Status Register, offset: 0xF0.
|
| __IO uint32_t | ANACTRL |
| | USB PHY Analog Control Register, offset: 0x100.
|
| __IO uint32_t | ANACTRL_SET |
| | USB PHY Analog Control Register, offset: 0x104.
|
| __IO uint32_t | ANACTRL_CLR |
| | USB PHY Analog Control Register, offset: 0x108.
|
| __IO uint32_t | ANACTRL_TOG |
| | USB PHY Analog Control Register, offset: 0x10C.
|
| __IO uint32_t | USB1_LOOPBACK |
| | USB PHY Loopback Control/Status Register, offset: 0x110.
|
| __IO uint32_t | USB1_LOOPBACK_SET |
| | USB PHY Loopback Control/Status Register, offset: 0x114.
|
| __IO uint32_t | USB1_LOOPBACK_CLR |
| | USB PHY Loopback Control/Status Register, offset: 0x118.
|
| __IO uint32_t | USB1_LOOPBACK_TOG |
| | USB PHY Loopback Control/Status Register, offset: 0x11C.
|
| __IO uint32_t | USB1_LOOPBACK_HSFSCNT |
| | USB PHY Loopback Packet Number Select Register, offset: 0x120.
|
| __IO uint32_t | USB1_LOOPBACK_HSFSCNT_SET |
| | USB PHY Loopback Packet Number Select Register, offset: 0x124.
|
| __IO uint32_t | USB1_LOOPBACK_HSFSCNT_CLR |
| | USB PHY Loopback Packet Number Select Register, offset: 0x128.
|
| __IO uint32_t | USB1_LOOPBACK_HSFSCNT_TOG |
| | USB PHY Loopback Packet Number Select Register, offset: 0x12C.
|
| __IO uint32_t | TRIM_OVERRIDE_EN |
| | USB PHY Trim Override Enable Register, offset: 0x130.
|
| __IO uint32_t | TRIM_OVERRIDE_EN_SET |
| | USB PHY Trim Override Enable Register, offset: 0x134.
|
| __IO uint32_t | TRIM_OVERRIDE_EN_CLR |
| | USB PHY Trim Override Enable Register, offset: 0x138.
|
| __IO uint32_t | TRIM_OVERRIDE_EN_TOG |
| | USB PHY Trim Override Enable Register, offset: 0x13C.
|
USBPHY - Register Layout Typedef.
1.7.2