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Ssc Struct Reference
[Synchronous Serial Controller]
Ssc hardware registers. More...
#include <ssc.h>
Data Fields | |
| WoReg | SSC_CR |
| (Ssc Offset: 0x0) Control Register | |
| RwReg | SSC_CMR |
| (Ssc Offset: 0x4) Clock Mode Register | |
| RwReg | SSC_RCMR |
| (Ssc Offset: 0x10) Receive Clock Mode Register | |
| RwReg | SSC_RFMR |
| (Ssc Offset: 0x14) Receive Frame Mode Register | |
| RwReg | SSC_TCMR |
| (Ssc Offset: 0x18) Transmit Clock Mode Register | |
| RwReg | SSC_TFMR |
| (Ssc Offset: 0x1C) Transmit Frame Mode Register | |
| RoReg | SSC_RHR |
| (Ssc Offset: 0x20) Receive Holding Register | |
| WoReg | SSC_THR |
| (Ssc Offset: 0x24) Transmit Holding Register | |
| RoReg | SSC_RSHR |
| (Ssc Offset: 0x30) Receive Sync. | |
| RwReg | SSC_TSHR |
| (Ssc Offset: 0x34) Transmit Sync. | |
| RwReg | SSC_RC0R |
| (Ssc Offset: 0x38) Receive Compare 0 Register | |
| RwReg | SSC_RC1R |
| (Ssc Offset: 0x3C) Receive Compare 1 Register | |
| RoReg | SSC_SR |
| (Ssc Offset: 0x40) Status Register | |
| WoReg | SSC_IER |
| (Ssc Offset: 0x44) Interrupt Enable Register | |
| WoReg | SSC_IDR |
| (Ssc Offset: 0x48) Interrupt Disable Register | |
| RoReg | SSC_IMR |
| (Ssc Offset: 0x4C) Interrupt Mask Register | |
| RwReg | SSC_WPMR |
| (Ssc Offset: 0xE4) Write Protect Mode Register | |
| RoReg | SSC_WPSR |
| (Ssc Offset: 0xE8) Write Protect Status Register | |
Detailed Description
Ssc hardware registers.
Definition at line 41 of file component/ssc.h.
Field Documentation
(Ssc Offset: 0x4) Clock Mode Register
Definition at line 43 of file component/ssc.h.
(Ssc Offset: 0x0) Control Register
Definition at line 42 of file component/ssc.h.
(Ssc Offset: 0x48) Interrupt Disable Register
Definition at line 58 of file component/ssc.h.
(Ssc Offset: 0x44) Interrupt Enable Register
Definition at line 57 of file component/ssc.h.
(Ssc Offset: 0x4C) Interrupt Mask Register
Definition at line 59 of file component/ssc.h.
(Ssc Offset: 0x38) Receive Compare 0 Register
Definition at line 54 of file component/ssc.h.
(Ssc Offset: 0x3C) Receive Compare 1 Register
Definition at line 55 of file component/ssc.h.
(Ssc Offset: 0x10) Receive Clock Mode Register
Definition at line 45 of file component/ssc.h.
(Ssc Offset: 0x14) Receive Frame Mode Register
Definition at line 46 of file component/ssc.h.
(Ssc Offset: 0x20) Receive Holding Register
Definition at line 49 of file component/ssc.h.
(Ssc Offset: 0x40) Status Register
Definition at line 56 of file component/ssc.h.
(Ssc Offset: 0x18) Transmit Clock Mode Register
Definition at line 47 of file component/ssc.h.
(Ssc Offset: 0x1C) Transmit Frame Mode Register
Definition at line 48 of file component/ssc.h.
(Ssc Offset: 0x24) Transmit Holding Register
Definition at line 50 of file component/ssc.h.
(Ssc Offset: 0xE4) Write Protect Mode Register
Definition at line 61 of file component/ssc.h.
(Ssc Offset: 0xE8) Write Protect Status Register
Definition at line 62 of file component/ssc.h.
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