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SDHC_Type Struct Reference
SDHC - Register Layout Typedef.
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#include <MK26F18.h >
__IO uint32_t DSADDR DMA System Address register, offset: 0x0. __IO uint32_t BLKATTR Block Attributes register, offset: 0x4. __IO uint32_t CMDARG Command Argument register, offset: 0x8. __IO uint32_t XFERTYP Transfer Type register, offset: 0xC. __I uint32_t CMDRSP [4] Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4. __IO uint32_t DATPORT Buffer Data Port register, offset: 0x20. __I uint32_t PRSSTAT Present State register, offset: 0x24. __IO uint32_t PROCTL Protocol Control register, offset: 0x28. __IO uint32_t SYSCTL System Control register, offset: 0x2C. __IO uint32_t IRQSTAT Interrupt Status register, offset: 0x30. __IO uint32_t IRQSTATEN Interrupt Status Enable register, offset: 0x34. __IO uint32_t IRQSIGEN Interrupt Signal Enable register, offset: 0x38. __I uint32_t AC12ERR Auto CMD12 Error Status Register, offset: 0x3C. __I uint32_t HTCAPBLT Host Controller Capabilities, offset: 0x40. __IO uint32_t WML Watermark Level Register, offset: 0x44. __O uint32_t FEVT Force Event register, offset: 0x50. __I uint32_t ADMAES ADMA Error Status register, offset: 0x54. __IO uint32_t ADSADDR ADMA System Addressregister, offset: 0x58. __IO uint32_t VENDOR Vendor Specific register, offset: 0xC0. __IO uint32_t MMCBOOT MMC Boot register, offset: 0xC4. __I uint32_t HOSTVER Host Controller Version, offset: 0xFC.
Detailed Description
SDHC - Register Layout Typedef.
Definition at line 18634 of file MK26F18.h .
Field Documentation
Auto CMD12 Error Status Register, offset: 0x3C.
Definition at line 18647 of file MK26F18.h .
ADMA Error Status register, offset: 0x54.
Definition at line 18652 of file MK26F18.h .
ADMA System Addressregister, offset: 0x58.
Definition at line 18653 of file MK26F18.h .
Block Attributes register, offset: 0x4.
Definition at line 18636 of file MK26F18.h .
Command Argument register, offset: 0x8.
Definition at line 18637 of file MK26F18.h .
Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4.
Definition at line 18639 of file MK26F18.h .
Buffer Data Port register, offset: 0x20.
Definition at line 18640 of file MK26F18.h .
DMA System Address register, offset: 0x0.
Definition at line 18635 of file MK26F18.h .
Force Event register, offset: 0x50.
Definition at line 18651 of file MK26F18.h .
Host Controller Version, offset: 0xFC.
Definition at line 18658 of file MK26F18.h .
Host Controller Capabilities, offset: 0x40.
Definition at line 18648 of file MK26F18.h .
Interrupt Signal Enable register, offset: 0x38.
Definition at line 18646 of file MK26F18.h .
Interrupt Status register, offset: 0x30.
Definition at line 18644 of file MK26F18.h .
Interrupt Status Enable register, offset: 0x34.
Definition at line 18645 of file MK26F18.h .
MMC Boot register, offset: 0xC4.
Definition at line 18656 of file MK26F18.h .
Protocol Control register, offset: 0x28.
Definition at line 18642 of file MK26F18.h .
Present State register, offset: 0x24.
Definition at line 18641 of file MK26F18.h .
System Control register, offset: 0x2C.
Definition at line 18643 of file MK26F18.h .
Vendor Specific register, offset: 0xC0.
Definition at line 18655 of file MK26F18.h .
Watermark Level Register, offset: 0x44.
Definition at line 18649 of file MK26F18.h .
Transfer Type register, offset: 0xC.
Definition at line 18638 of file MK26F18.h .
1.7.2