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Pmc Struct Reference

Pmc Struct Reference
[Power Management Controller]

Pmc hardware registers. More...

#include <pmc.h>

Data Fields

WoReg PMC_SCER
 (Pmc Offset: 0x0000) System Clock Enable Register
WoReg PMC_SCDR
 (Pmc Offset: 0x0004) System Clock Disable Register
RoReg PMC_SCSR
 (Pmc Offset: 0x0008) System Clock Status Register
WoReg PMC_PCER0
 (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0
WoReg PMC_PCDR0
 (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0
RoReg PMC_PCSR0
 (Pmc Offset: 0x0018) Peripheral Clock Status Register 0
RwReg CKGR_UCKR
 (Pmc Offset: 0x001C) UTMI Clock Register
RwReg CKGR_MOR
 (Pmc Offset: 0x0020) Main Oscillator Register
RoReg CKGR_MCFR
 (Pmc Offset: 0x0024) Main Clock Frequency Register
RwReg CKGR_PLLAR
 (Pmc Offset: 0x0028) PLLA Register
RwReg PMC_MCKR
 (Pmc Offset: 0x0030) Master Clock Register
RwReg PMC_PCK [3]
 (Pmc Offset: 0x0040) Programmable Clock 0 Register
WoReg PMC_IER
 (Pmc Offset: 0x0060) Interrupt Enable Register
WoReg PMC_IDR
 (Pmc Offset: 0x0064) Interrupt Disable Register
RoReg PMC_SR
 (Pmc Offset: 0x0068) Status Register
RoReg PMC_IMR
 (Pmc Offset: 0x006C) Interrupt Mask Register
RwReg PMC_FSMR
 (Pmc Offset: 0x0070) Fast Startup Mode Register
RwReg PMC_FSPR
 (Pmc Offset: 0x0074) Fast Startup Polarity Register
WoReg PMC_FOCR
 (Pmc Offset: 0x0078) Fault Output Clear Register
RwReg PMC_WPMR
 (Pmc Offset: 0x00E4) Write Protect Mode Register
RoReg PMC_WPSR
 (Pmc Offset: 0x00E8) Write Protect Status Register

Detailed Description

Pmc hardware registers.

Definition at line 41 of file component/pmc.h.


Field Documentation

(Pmc Offset: 0x0024) Main Clock Frequency Register

Definition at line 51 of file component/pmc.h.

(Pmc Offset: 0x0020) Main Oscillator Register

Definition at line 50 of file component/pmc.h.

(Pmc Offset: 0x0028) PLLA Register

Definition at line 52 of file component/pmc.h.

(Pmc Offset: 0x001C) UTMI Clock Register

Definition at line 49 of file component/pmc.h.

(Pmc Offset: 0x0078) Fault Output Clear Register

Definition at line 64 of file component/pmc.h.

(Pmc Offset: 0x0070) Fast Startup Mode Register

Definition at line 62 of file component/pmc.h.

(Pmc Offset: 0x0074) Fast Startup Polarity Register

Definition at line 63 of file component/pmc.h.

(Pmc Offset: 0x0064) Interrupt Disable Register

Definition at line 59 of file component/pmc.h.

(Pmc Offset: 0x0060) Interrupt Enable Register

Definition at line 58 of file component/pmc.h.

(Pmc Offset: 0x006C) Interrupt Mask Register

Definition at line 61 of file component/pmc.h.

(Pmc Offset: 0x0030) Master Clock Register

Definition at line 54 of file component/pmc.h.

(Pmc Offset: 0x0014) Peripheral Clock Disable Register 0

Definition at line 47 of file component/pmc.h.

(Pmc Offset: 0x0010) Peripheral Clock Enable Register 0

Definition at line 46 of file component/pmc.h.

(Pmc Offset: 0x0040) Programmable Clock 0 Register

Definition at line 56 of file component/pmc.h.

(Pmc Offset: 0x0018) Peripheral Clock Status Register 0

Definition at line 48 of file component/pmc.h.

(Pmc Offset: 0x0004) System Clock Disable Register

Definition at line 43 of file component/pmc.h.

(Pmc Offset: 0x0000) System Clock Enable Register

Definition at line 42 of file component/pmc.h.

(Pmc Offset: 0x0008) System Clock Status Register

Definition at line 44 of file component/pmc.h.

(Pmc Offset: 0x0068) Status Register

Definition at line 60 of file component/pmc.h.

(Pmc Offset: 0x00E4) Write Protect Mode Register

Definition at line 66 of file component/pmc.h.

(Pmc Offset: 0x00E8) Write Protect Status Register

Definition at line 67 of file component/pmc.h.