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Hsmci Struct Reference
[High Speed MultiMedia Card Interface]
Hsmci hardware registers. More...
#include <hsmci.h>
Data Fields | |
| WoReg | HSMCI_CR |
| (Hsmci Offset: 0x00) Control Register | |
| RwReg | HSMCI_MR |
| (Hsmci Offset: 0x04) Mode Register | |
| RwReg | HSMCI_DTOR |
| (Hsmci Offset: 0x08) Data Timeout Register | |
| RwReg | HSMCI_SDCR |
| (Hsmci Offset: 0x0C) SD/SDIO Card Register | |
| RwReg | HSMCI_ARGR |
| (Hsmci Offset: 0x10) Argument Register | |
| WoReg | HSMCI_CMDR |
| (Hsmci Offset: 0x14) Command Register | |
| RwReg | HSMCI_BLKR |
| (Hsmci Offset: 0x18) Block Register | |
| RwReg | HSMCI_CSTOR |
| (Hsmci Offset: 0x1C) Completion Signal Timeout Register | |
| RoReg | HSMCI_RSPR [4] |
| (Hsmci Offset: 0x20) Response Register | |
| RoReg | HSMCI_RDR |
| (Hsmci Offset: 0x30) Receive Data Register | |
| WoReg | HSMCI_TDR |
| (Hsmci Offset: 0x34) Transmit Data Register | |
| RoReg | HSMCI_SR |
| (Hsmci Offset: 0x40) Status Register | |
| WoReg | HSMCI_IER |
| (Hsmci Offset: 0x44) Interrupt Enable Register | |
| WoReg | HSMCI_IDR |
| (Hsmci Offset: 0x48) Interrupt Disable Register | |
| RoReg | HSMCI_IMR |
| (Hsmci Offset: 0x4C) Interrupt Mask Register | |
| RwReg | HSMCI_DMA |
| (Hsmci Offset: 0x50) DMA Configuration Register | |
| RwReg | HSMCI_CFG |
| (Hsmci Offset: 0x54) Configuration Register | |
| RwReg | HSMCI_WPMR |
| (Hsmci Offset: 0xE4) Write Protection Mode Register | |
| RoReg | HSMCI_WPSR |
| (Hsmci Offset: 0xE8) Write Protection Status Register | |
| RwReg | HSMCI_FIFO [256] |
| (Hsmci Offset: 0x200) FIFO Memory Aperture0 | |
Detailed Description
Hsmci hardware registers.
Definition at line 41 of file component/hsmci.h.
Field Documentation
(Hsmci Offset: 0x10) Argument Register
Definition at line 46 of file component/hsmci.h.
(Hsmci Offset: 0x18) Block Register
Definition at line 48 of file component/hsmci.h.
(Hsmci Offset: 0x54) Configuration Register
Definition at line 59 of file component/hsmci.h.
(Hsmci Offset: 0x14) Command Register
Definition at line 47 of file component/hsmci.h.
(Hsmci Offset: 0x00) Control Register
Definition at line 42 of file component/hsmci.h.
(Hsmci Offset: 0x1C) Completion Signal Timeout Register
Definition at line 49 of file component/hsmci.h.
(Hsmci Offset: 0x50) DMA Configuration Register
Definition at line 58 of file component/hsmci.h.
(Hsmci Offset: 0x08) Data Timeout Register
Definition at line 44 of file component/hsmci.h.
| RwReg HSMCI_FIFO[256] |
(Hsmci Offset: 0x200) FIFO Memory Aperture0
Definition at line 64 of file component/hsmci.h.
(Hsmci Offset: 0x48) Interrupt Disable Register
Definition at line 56 of file component/hsmci.h.
(Hsmci Offset: 0x44) Interrupt Enable Register
Definition at line 55 of file component/hsmci.h.
(Hsmci Offset: 0x4C) Interrupt Mask Register
Definition at line 57 of file component/hsmci.h.
(Hsmci Offset: 0x04) Mode Register
Definition at line 43 of file component/hsmci.h.
(Hsmci Offset: 0x30) Receive Data Register
Definition at line 51 of file component/hsmci.h.
| RoReg HSMCI_RSPR[4] |
(Hsmci Offset: 0x20) Response Register
Definition at line 50 of file component/hsmci.h.
(Hsmci Offset: 0x0C) SD/SDIO Card Register
Definition at line 45 of file component/hsmci.h.
(Hsmci Offset: 0x40) Status Register
Definition at line 54 of file component/hsmci.h.
(Hsmci Offset: 0x34) Transmit Data Register
Definition at line 52 of file component/hsmci.h.
(Hsmci Offset: 0xE4) Write Protection Mode Register
Definition at line 61 of file component/hsmci.h.
(Hsmci Offset: 0xE8) Write Protection Status Register
Definition at line 62 of file component/hsmci.h.
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