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Adc Struct Reference
[Analog-to-Digital Converter]
Adc hardware registers. More...
#include <adc.h>
Data Fields | |
| WoReg | ADC_CR |
| (Adc Offset: 0x00) Control Register | |
| RwReg | ADC_MR |
| (Adc Offset: 0x04) Mode Register | |
| WoReg | ADC_CHER |
| (Adc Offset: 0x10) Channel Enable Register | |
| WoReg | ADC_CHDR |
| (Adc Offset: 0x14) Channel Disable Register | |
| RoReg | ADC_CHSR |
| (Adc Offset: 0x18) Channel Status Register | |
| RoReg | ADC_SR |
| (Adc Offset: 0x1C) Status Register | |
| RoReg | ADC_LCDR |
| (Adc Offset: 0x20) Last Converted Data Register | |
| WoReg | ADC_IER |
| (Adc Offset: 0x24) Interrupt Enable Register | |
| WoReg | ADC_IDR |
| (Adc Offset: 0x28) Interrupt Disable Register | |
| RoReg | ADC_IMR |
| (Adc Offset: 0x2C) Interrupt Mask Register | |
| RoReg | ADC_CDR [8] |
| (Adc Offset: 0x30) Channel Data Register | |
| RwReg | ADC_RPR |
| (Adc Offset: 0x100) Receive Pointer Register | |
| RwReg | ADC_RCR |
| (Adc Offset: 0x104) Receive Counter Register | |
| RwReg | ADC_RNPR |
| (Adc Offset: 0x110) Receive Next Pointer Register | |
| RwReg | ADC_RNCR |
| (Adc Offset: 0x114) Receive Next Counter Register | |
| WoReg | ADC_PTCR |
| (Adc Offset: 0x120) Transfer Control Register | |
| RoReg | ADC_PTSR |
| (Adc Offset: 0x124) Transfer Status Register | |
Detailed Description
Adc hardware registers.
Definition at line 41 of file component/adc.h.
Field Documentation
(Adc Offset: 0x30) Channel Data Register
Definition at line 53 of file component/adc.h.
(Adc Offset: 0x14) Channel Disable Register
Definition at line 46 of file component/adc.h.
(Adc Offset: 0x10) Channel Enable Register
Definition at line 45 of file component/adc.h.
(Adc Offset: 0x18) Channel Status Register
Definition at line 47 of file component/adc.h.
(Adc Offset: 0x00) Control Register
Definition at line 42 of file component/adc.h.
(Adc Offset: 0x28) Interrupt Disable Register
Definition at line 51 of file component/adc.h.
(Adc Offset: 0x24) Interrupt Enable Register
Definition at line 50 of file component/adc.h.
(Adc Offset: 0x2C) Interrupt Mask Register
Definition at line 52 of file component/adc.h.
(Adc Offset: 0x20) Last Converted Data Register
Definition at line 49 of file component/adc.h.
(Adc Offset: 0x04) Mode Register
Definition at line 43 of file component/adc.h.
(Adc Offset: 0x120) Transfer Control Register
Definition at line 61 of file component/adc.h.
(Adc Offset: 0x124) Transfer Status Register
Definition at line 62 of file component/adc.h.
(Adc Offset: 0x104) Receive Counter Register
Definition at line 56 of file component/adc.h.
(Adc Offset: 0x114) Receive Next Counter Register
Definition at line 59 of file component/adc.h.
(Adc Offset: 0x110) Receive Next Pointer Register
Definition at line 58 of file component/adc.h.
(Adc Offset: 0x100) Receive Pointer Register
Definition at line 55 of file component/adc.h.
(Adc Offset: 0x1C) Status Register
Definition at line 48 of file component/adc.h.
Generated on Tue Jul 12 2022 15:37:36 by
1.7.2