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stm32f1xx_hal_tim.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_tim.h 00004 * @author MCD Application Team 00005 * @version V1.0.4 00006 * @date 29-April-2016 00007 * @brief Header file of TIM HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32F1xx_HAL_TIM_H 00040 #define __STM32F1xx_HAL_TIM_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f1xx_hal_def.h" 00048 00049 /** @addtogroup STM32F1xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup TIM 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup TIM_Exported_Types TIM Exported Types 00059 * @{ 00060 */ 00061 /** 00062 * @brief TIM Time base Configuration Structure definition 00063 */ 00064 typedef struct 00065 { 00066 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00067 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00068 00069 uint32_t CounterMode; /*!< Specifies the counter mode. 00070 This parameter can be a value of @ref TIM_Counter_Mode */ 00071 00072 uint32_t Period; /*!< Specifies the period value to be loaded into the active 00073 Auto-Reload Register at the next update event. 00074 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 00075 00076 uint32_t ClockDivision; /*!< Specifies the clock division. 00077 This parameter can be a value of @ref TIM_ClockDivision */ 00078 00079 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00080 reaches zero, an update event is generated and counting restarts 00081 from the RCR value (N). 00082 This means in PWM mode that (N+1) corresponds to: 00083 - the number of PWM periods in edge-aligned mode 00084 - the number of half PWM period in center-aligned mode 00085 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00086 @note This parameter is valid only for TIM1 and TIM8. */ 00087 } TIM_Base_InitTypeDef; 00088 00089 /** 00090 * @brief TIM Output Compare Configuration Structure definition 00091 */ 00092 typedef struct 00093 { 00094 uint32_t OCMode; /*!< Specifies the TIM mode. 00095 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00096 00097 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00098 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00099 00100 uint32_t OCPolarity; /*!< Specifies the output polarity. 00101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00102 00103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00105 @note This parameter is valid only for TIM1 and TIM8. */ 00106 00107 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 00108 This parameter can be a value of @ref TIM_Output_Fast_State 00109 @note This parameter is valid only in PWM1 and PWM2 mode. */ 00110 00111 00112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00114 @note This parameter is valid only for TIM1 and TIM8. */ 00115 00116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00118 @note This parameter is valid only for TIM1 and TIM8. */ 00119 } TIM_OC_InitTypeDef; 00120 00121 /** 00122 * @brief TIM One Pulse Mode Configuration Structure definition 00123 */ 00124 typedef struct 00125 { 00126 uint32_t OCMode; /*!< Specifies the TIM mode. 00127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00128 00129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00130 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00131 00132 uint32_t OCPolarity; /*!< Specifies the output polarity. 00133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00134 00135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00137 @note This parameter is valid only for TIM1 and TIM8. */ 00138 00139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00141 @note This parameter is valid only for TIM1 and TIM8. */ 00142 00143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00145 @note This parameter is valid only for TIM1 and TIM8. */ 00146 00147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00149 00150 uint32_t ICSelection; /*!< Specifies the input. 00151 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00152 00153 uint32_t ICFilter; /*!< Specifies the input capture filter. 00154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00155 } TIM_OnePulse_InitTypeDef; 00156 00157 00158 /** 00159 * @brief TIM Input Capture Configuration Structure definition 00160 */ 00161 typedef struct 00162 { 00163 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00164 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00165 00166 uint32_t ICSelection; /*!< Specifies the input. 00167 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00168 00169 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00170 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00171 00172 uint32_t ICFilter; /*!< Specifies the input capture filter. 00173 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00174 } TIM_IC_InitTypeDef; 00175 00176 /** 00177 * @brief TIM Encoder Configuration Structure definition 00178 */ 00179 typedef struct 00180 { 00181 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 00182 This parameter can be a value of @ref TIM_Encoder_Mode */ 00183 00184 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 00185 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00186 00187 uint32_t IC1Selection; /*!< Specifies the input. 00188 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00189 00190 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 00191 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00192 00193 uint32_t IC1Filter; /*!< Specifies the input capture filter. 00194 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00195 00196 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 00197 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00198 00199 uint32_t IC2Selection; /*!< Specifies the input. 00200 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00201 00202 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 00203 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00204 00205 uint32_t IC2Filter; /*!< Specifies the input capture filter. 00206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00207 } TIM_Encoder_InitTypeDef; 00208 00209 00210 /** 00211 * @brief TIM Clock Configuration Handle Structure definition 00212 */ 00213 typedef struct 00214 { 00215 uint32_t ClockSource; /*!< TIM clock sources 00216 This parameter can be a value of @ref TIM_Clock_Source */ 00217 uint32_t ClockPolarity; /*!< TIM clock polarity 00218 This parameter can be a value of @ref TIM_Clock_Polarity */ 00219 uint32_t ClockPrescaler; /*!< TIM clock prescaler 00220 This parameter can be a value of @ref TIM_Clock_Prescaler */ 00221 uint32_t ClockFilter; /*!< TIM clock filter 00222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00223 }TIM_ClockConfigTypeDef; 00224 00225 /** 00226 * @brief TIM Clear Input Configuration Handle Structure definition 00227 */ 00228 typedef struct 00229 { 00230 uint32_t ClearInputState; /*!< TIM clear Input state 00231 This parameter can be ENABLE or DISABLE */ 00232 uint32_t ClearInputSource; /*!< TIM clear Input sources 00233 This parameter can be a value of @ref TIM_ClearInput_Source */ 00234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 00235 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 00236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 00237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ 00238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 00239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00240 }TIM_ClearInputConfigTypeDef; 00241 00242 /** 00243 * @brief TIM Slave configuration Structure definition 00244 */ 00245 typedef struct { 00246 uint32_t SlaveMode; /*!< Slave mode selection 00247 This parameter can be a value of @ref TIM_Slave_Mode */ 00248 uint32_t InputTrigger; /*!< Input Trigger source 00249 This parameter can be a value of @ref TIM_Trigger_Selection */ 00250 uint32_t TriggerPolarity; /*!< Input Trigger polarity 00251 This parameter can be a value of @ref TIM_Trigger_Polarity */ 00252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 00253 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 00254 uint32_t TriggerFilter; /*!< Input trigger filter 00255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00256 00257 }TIM_SlaveConfigTypeDef; 00258 00259 /** 00260 * @brief HAL State structures definition 00261 */ 00262 typedef enum 00263 { 00264 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ 00265 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ 00266 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ 00267 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ 00268 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ 00269 }HAL_TIM_StateTypeDef; 00270 00271 /** 00272 * @brief HAL Active channel structures definition 00273 */ 00274 typedef enum 00275 { 00276 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ 00277 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ 00278 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ 00279 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ 00280 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ 00281 }HAL_TIM_ActiveChannel; 00282 00283 /** 00284 * @brief TIM Time Base Handle Structure definition 00285 */ 00286 typedef struct 00287 { 00288 TIM_TypeDef *Instance; /*!< Register base address */ 00289 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 00290 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 00291 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 00292 This array is accessed by a @ref TIM_DMA_Handle_index */ 00293 HAL_LockTypeDef Lock; /*!< Locking object */ 00294 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 00295 }TIM_HandleTypeDef; 00296 00297 /** 00298 * @} 00299 */ 00300 00301 /* Exported constants --------------------------------------------------------*/ 00302 /** @defgroup TIM_Exported_Constants TIM Exported Constants 00303 * @{ 00304 */ 00305 00306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity 00307 * @{ 00308 */ 00309 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ 00310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ 00311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 00317 * @{ 00318 */ 00319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ 00320 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 00326 * @{ 00327 */ 00328 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ 00329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ 00330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ 00331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup TIM_Counter_Mode TIM Counter Mode 00337 * @{ 00338 */ 00339 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) 00340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR 00341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 00342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 00343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup TIM_ClockDivision TIM ClockDivision 00349 * @{ 00350 */ 00351 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) 00352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) 00353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes 00359 * @{ 00360 */ 00361 #define TIM_OCMODE_TIMING ((uint32_t)0x0000) 00362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) 00363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) 00364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) 00365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) 00366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) 00367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) 00368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 00374 * @{ 00375 */ 00376 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) 00377 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) 00378 /** 00379 * @} 00380 */ 00381 00382 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 00383 * @{ 00384 */ 00385 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) 00386 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) 00387 /** 00388 * @} 00389 */ 00390 00391 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 00392 * @{ 00393 */ 00394 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) 00395 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) 00396 /** 00397 * @} 00398 */ 00399 00400 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 00401 * @{ 00402 */ 00403 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) 00404 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 00410 * @{ 00411 */ 00412 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) 00413 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 00419 * @{ 00420 */ 00421 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) 00422 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) 00423 /** 00424 * @} 00425 */ 00426 00427 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 00428 * @{ 00429 */ 00430 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) 00431 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup TIM_Channel TIM Channel 00437 * @{ 00438 */ 00439 #define TIM_CHANNEL_1 ((uint32_t)0x0000) 00440 #define TIM_CHANNEL_2 ((uint32_t)0x0004) 00441 #define TIM_CHANNEL_3 ((uint32_t)0x0008) 00442 #define TIM_CHANNEL_4 ((uint32_t)0x000C) 00443 #define TIM_CHANNEL_ALL ((uint32_t)0x0018) 00444 /** 00445 * @} 00446 */ 00447 00448 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 00449 * @{ 00450 */ 00451 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 00452 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 00453 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 00454 /** 00455 * @} 00456 */ 00457 00458 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 00459 * @{ 00460 */ 00461 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00462 connected to IC1, IC2, IC3 or IC4, respectively */ 00463 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00464 connected to IC2, IC1, IC4 or IC3, respectively */ 00465 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 00466 /** 00467 * @} 00468 */ 00469 00470 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 00471 * @{ 00472 */ 00473 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ 00474 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ 00475 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ 00476 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ 00477 /** 00478 * @} 00479 */ 00480 00481 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 00482 * @{ 00483 */ 00484 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) 00485 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) 00486 /** 00487 * @} 00488 */ 00489 00490 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 00491 * @{ 00492 */ 00493 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) 00494 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) 00495 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) 00496 /** 00497 * @} 00498 */ 00499 00500 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition 00501 * @{ 00502 */ 00503 #define TIM_IT_UPDATE (TIM_DIER_UIE) 00504 #define TIM_IT_CC1 (TIM_DIER_CC1IE) 00505 #define TIM_IT_CC2 (TIM_DIER_CC2IE) 00506 #define TIM_IT_CC3 (TIM_DIER_CC3IE) 00507 #define TIM_IT_CC4 (TIM_DIER_CC4IE) 00508 #define TIM_IT_COM (TIM_DIER_COMIE) 00509 #define TIM_IT_TRIGGER (TIM_DIER_TIE) 00510 #define TIM_IT_BREAK (TIM_DIER_BIE) 00511 /** 00512 * @} 00513 */ 00514 00515 /** @defgroup TIM_Commutation_Source TIM Commutation Source 00516 * @{ 00517 */ 00518 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) 00519 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) 00520 00521 /** 00522 * @} 00523 */ 00524 00525 /** @defgroup TIM_DMA_sources TIM DMA Sources 00526 * @{ 00527 */ 00528 #define TIM_DMA_UPDATE (TIM_DIER_UDE) 00529 #define TIM_DMA_CC1 (TIM_DIER_CC1DE) 00530 #define TIM_DMA_CC2 (TIM_DIER_CC2DE) 00531 #define TIM_DMA_CC3 (TIM_DIER_CC3DE) 00532 #define TIM_DMA_CC4 (TIM_DIER_CC4DE) 00533 #define TIM_DMA_COM (TIM_DIER_COMDE) 00534 #define TIM_DMA_TRIGGER (TIM_DIER_TDE) 00535 /** 00536 * @} 00537 */ 00538 00539 /** @defgroup TIM_Event_Source TIM Event Source 00540 * @{ 00541 */ 00542 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG 00543 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G 00544 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G 00545 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G 00546 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G 00547 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG 00548 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG 00549 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG 00550 /** 00551 * @} 00552 */ 00553 00554 /** @defgroup TIM_Flag_definition TIM Flag Definition 00555 * @{ 00556 */ 00557 #define TIM_FLAG_UPDATE (TIM_SR_UIF) 00558 #define TIM_FLAG_CC1 (TIM_SR_CC1IF) 00559 #define TIM_FLAG_CC2 (TIM_SR_CC2IF) 00560 #define TIM_FLAG_CC3 (TIM_SR_CC3IF) 00561 #define TIM_FLAG_CC4 (TIM_SR_CC4IF) 00562 #define TIM_FLAG_COM (TIM_SR_COMIF) 00563 #define TIM_FLAG_TRIGGER (TIM_SR_TIF) 00564 #define TIM_FLAG_BREAK (TIM_SR_BIF) 00565 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) 00566 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) 00567 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) 00568 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) 00569 /** 00570 * @} 00571 */ 00572 00573 /** @defgroup TIM_Clock_Source TIM Clock Source 00574 * @{ 00575 */ 00576 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) 00577 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) 00578 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) 00579 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) 00580 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) 00581 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) 00582 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) 00583 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) 00584 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) 00585 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) 00586 /** 00587 * @} 00588 */ 00589 00590 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 00591 * @{ 00592 */ 00593 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 00594 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 00595 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 00596 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 00597 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 00598 /** 00599 * @} 00600 */ 00601 00602 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 00603 * @{ 00604 */ 00605 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00606 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 00607 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 00608 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source 00614 * @{ 00615 */ 00616 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) 00617 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) 00618 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) 00619 /** 00620 * @} 00621 */ 00622 00623 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 00624 * @{ 00625 */ 00626 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 00627 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 00628 /** 00629 * @} 00630 */ 00631 00632 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 00633 * @{ 00634 */ 00635 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00636 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 00637 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 00638 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 00639 /** 00640 * @} 00641 */ 00642 00643 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state 00644 * @{ 00645 */ 00646 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) 00647 #define TIM_OSSR_DISABLE ((uint32_t)0x0000) 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state 00653 * @{ 00654 */ 00655 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) 00656 #define TIM_OSSI_DISABLE ((uint32_t)0x0000) 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup TIM_Lock_level TIM Lock level 00662 * @{ 00663 */ 00664 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) 00665 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) 00666 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) 00667 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) 00668 /** 00669 * @} 00670 */ 00671 00672 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable 00673 * @{ 00674 */ 00675 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) 00676 #define TIM_BREAK_DISABLE ((uint32_t)0x0000) 00677 /** 00678 * @} 00679 */ 00680 00681 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 00682 * @{ 00683 */ 00684 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) 00685 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) 00686 /** 00687 * @} 00688 */ 00689 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 00690 * @{ 00691 */ 00692 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) 00693 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) 00694 /** 00695 * @} 00696 */ 00697 00698 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 00699 * @{ 00700 */ 00701 #define TIM_TRGO_RESET ((uint32_t)0x0000) 00702 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) 00703 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) 00704 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 00705 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) 00706 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) 00707 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) 00708 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup TIM_Slave_Mode TIM Slave Mode 00714 * @{ 00715 */ 00716 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) 00717 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) 00718 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) 00719 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) 00720 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode 00726 * @{ 00727 */ 00728 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) 00729 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 00735 * @{ 00736 */ 00737 #define TIM_TS_ITR0 ((uint32_t)0x0000) 00738 #define TIM_TS_ITR1 ((uint32_t)0x0010) 00739 #define TIM_TS_ITR2 ((uint32_t)0x0020) 00740 #define TIM_TS_ITR3 ((uint32_t)0x0030) 00741 #define TIM_TS_TI1F_ED ((uint32_t)0x0040) 00742 #define TIM_TS_TI1FP1 ((uint32_t)0x0050) 00743 #define TIM_TS_TI2FP2 ((uint32_t)0x0060) 00744 #define TIM_TS_ETRF ((uint32_t)0x0070) 00745 #define TIM_TS_NONE ((uint32_t)0xFFFF) 00746 /** 00747 * @} 00748 */ 00749 00750 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 00751 * @{ 00752 */ 00753 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 00754 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 00755 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00756 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00757 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00758 /** 00759 * @} 00760 */ 00761 00762 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 00763 * @{ 00764 */ 00765 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00766 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 00767 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 00768 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 00769 /** 00770 * @} 00771 */ 00772 00773 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 00774 * @{ 00775 */ 00776 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) 00777 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) 00778 /** 00779 * @} 00780 */ 00781 00782 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 00783 * @{ 00784 */ 00785 #define TIM_DMABASE_CR1 (0x00000000) 00786 #define TIM_DMABASE_CR2 (0x00000001) 00787 #define TIM_DMABASE_SMCR (0x00000002) 00788 #define TIM_DMABASE_DIER (0x00000003) 00789 #define TIM_DMABASE_SR (0x00000004) 00790 #define TIM_DMABASE_EGR (0x00000005) 00791 #define TIM_DMABASE_CCMR1 (0x00000006) 00792 #define TIM_DMABASE_CCMR2 (0x00000007) 00793 #define TIM_DMABASE_CCER (0x00000008) 00794 #define TIM_DMABASE_CNT (0x00000009) 00795 #define TIM_DMABASE_PSC (0x0000000A) 00796 #define TIM_DMABASE_ARR (0x0000000B) 00797 #define TIM_DMABASE_RCR (0x0000000C) 00798 #define TIM_DMABASE_CCR1 (0x0000000D) 00799 #define TIM_DMABASE_CCR2 (0x0000000E) 00800 #define TIM_DMABASE_CCR3 (0x0000000F) 00801 #define TIM_DMABASE_CCR4 (0x00000010) 00802 #define TIM_DMABASE_BDTR (0x00000011) 00803 #define TIM_DMABASE_DCR (0x00000012) 00804 /** 00805 * @} 00806 */ 00807 00808 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 00809 * @{ 00810 */ 00811 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) 00812 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) 00813 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) 00814 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) 00815 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) 00816 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) 00817 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) 00818 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) 00819 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) 00820 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) 00821 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) 00822 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) 00823 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) 00824 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) 00825 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) 00826 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) 00827 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) 00828 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index 00834 * @{ 00835 */ 00836 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ 00837 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 00838 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 00839 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 00840 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 00841 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ 00842 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ 00843 /** 00844 * @} 00845 */ 00846 00847 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State 00848 * @{ 00849 */ 00850 #define TIM_CCx_ENABLE ((uint32_t)0x0001) 00851 #define TIM_CCx_DISABLE ((uint32_t)0x0000) 00852 #define TIM_CCxN_ENABLE ((uint32_t)0x0004) 00853 #define TIM_CCxN_DISABLE ((uint32_t)0x0000) 00854 /** 00855 * @} 00856 */ 00857 00858 /** 00859 * @} 00860 */ 00861 00862 /* Private Constants -----------------------------------------------------------*/ 00863 /** @defgroup TIM_Private_Constants TIM Private Constants 00864 * @{ 00865 */ 00866 00867 /* The counter of a timer instance is disabled only if all the CCx and CCxN 00868 channels have been disabled */ 00869 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 00870 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 00871 00872 /** 00873 * @} 00874 */ 00875 00876 /* Private Macros -----------------------------------------------------------*/ 00877 /** @defgroup TIM_Private_Macros TIM Private Macros 00878 * @{ 00879 */ 00880 00881 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ 00882 ((MODE) == TIM_COUNTERMODE_DOWN) || \ 00883 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 00884 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 00885 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) 00886 00887 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ 00888 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ 00889 ((DIV) == TIM_CLOCKDIVISION_DIV4)) 00890 00891 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ 00892 ((MODE) == TIM_OCMODE_PWM2)) 00893 00894 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ 00895 ((MODE) == TIM_OCMODE_ACTIVE) || \ 00896 ((MODE) == TIM_OCMODE_INACTIVE) || \ 00897 ((MODE) == TIM_OCMODE_TOGGLE) || \ 00898 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ 00899 ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) 00900 00901 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ 00902 ((STATE) == TIM_OCFAST_ENABLE)) 00903 00904 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ 00905 ((POLARITY) == TIM_OCPOLARITY_LOW)) 00906 00907 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ 00908 ((POLARITY) == TIM_OCNPOLARITY_LOW)) 00909 00910 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ 00911 ((STATE) == TIM_OCIDLESTATE_RESET)) 00912 00913 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ 00914 ((STATE) == TIM_OCNIDLESTATE_RESET)) 00915 00916 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 00917 ((CHANNEL) == TIM_CHANNEL_2) || \ 00918 ((CHANNEL) == TIM_CHANNEL_3) || \ 00919 ((CHANNEL) == TIM_CHANNEL_4) || \ 00920 ((CHANNEL) == TIM_CHANNEL_ALL)) 00921 00922 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 00923 ((CHANNEL) == TIM_CHANNEL_2)) 00924 00925 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 00926 ((CHANNEL) == TIM_CHANNEL_2) || \ 00927 ((CHANNEL) == TIM_CHANNEL_3)) 00928 00929 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ 00930 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ 00931 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) 00932 00933 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ 00934 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ 00935 ((SELECTION) == TIM_ICSELECTION_TRC)) 00936 00937 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 00938 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 00939 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 00940 ((PRESCALER) == TIM_ICPSC_DIV8)) 00941 00942 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ 00943 ((MODE) == TIM_OPMODE_REPETITIVE)) 00944 00945 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ 00946 ((MODE) == TIM_ENCODERMODE_TI2) || \ 00947 ((MODE) == TIM_ENCODERMODE_TI12)) 00948 00949 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) 00950 00951 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) 00952 00953 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ 00954 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ 00955 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ 00956 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ 00957 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ 00958 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ 00959 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ 00960 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ 00961 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ 00962 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) 00963 00964 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ 00965 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 00966 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ 00967 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ 00968 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) 00969 00970 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ 00971 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ 00972 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ 00973 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) 00974 00975 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) 00976 00977 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ 00978 ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ 00979 ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) 00980 00981 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 00982 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 00983 00984 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 00985 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 00986 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 00987 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) 00988 00989 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 00990 00991 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ 00992 ((STATE) == TIM_OSSR_DISABLE)) 00993 00994 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ 00995 ((STATE) == TIM_OSSI_DISABLE)) 00996 00997 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ 00998 ((LEVEL) == TIM_LOCKLEVEL_1) || \ 00999 ((LEVEL) == TIM_LOCKLEVEL_2) || \ 01000 ((LEVEL) == TIM_LOCKLEVEL_3)) 01001 01002 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ 01003 ((STATE) == TIM_BREAK_DISABLE)) 01004 01005 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ 01006 ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) 01007 01008 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 01009 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) 01010 01011 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ 01012 ((SOURCE) == TIM_TRGO_ENABLE) || \ 01013 ((SOURCE) == TIM_TRGO_UPDATE) || \ 01014 ((SOURCE) == TIM_TRGO_OC1) || \ 01015 ((SOURCE) == TIM_TRGO_OC1REF) || \ 01016 ((SOURCE) == TIM_TRGO_OC2REF) || \ 01017 ((SOURCE) == TIM_TRGO_OC3REF) || \ 01018 ((SOURCE) == TIM_TRGO_OC4REF)) 01019 01020 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ 01021 ((MODE) == TIM_SLAVEMODE_GATED) || \ 01022 ((MODE) == TIM_SLAVEMODE_RESET) || \ 01023 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ 01024 ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) 01025 01026 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ 01027 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) 01028 01029 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 01030 ((SELECTION) == TIM_TS_ITR1) || \ 01031 ((SELECTION) == TIM_TS_ITR2) || \ 01032 ((SELECTION) == TIM_TS_ITR3) || \ 01033 ((SELECTION) == TIM_TS_TI1F_ED) || \ 01034 ((SELECTION) == TIM_TS_TI1FP1) || \ 01035 ((SELECTION) == TIM_TS_TI2FP2) || \ 01036 ((SELECTION) == TIM_TS_ETRF)) 01037 01038 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 01039 ((SELECTION) == TIM_TS_ITR1) || \ 01040 ((SELECTION) == TIM_TS_ITR2) || \ 01041 ((SELECTION) == TIM_TS_ITR3) || \ 01042 ((SELECTION) == TIM_TS_NONE)) 01043 01044 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 01045 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 01046 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ 01047 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ 01048 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 01049 01050 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ 01051 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ 01052 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ 01053 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) 01054 01055 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) 01056 01057 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ 01058 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) 01059 01060 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ 01061 ((BASE) == TIM_DMABASE_CR2) || \ 01062 ((BASE) == TIM_DMABASE_SMCR) || \ 01063 ((BASE) == TIM_DMABASE_DIER) || \ 01064 ((BASE) == TIM_DMABASE_SR) || \ 01065 ((BASE) == TIM_DMABASE_EGR) || \ 01066 ((BASE) == TIM_DMABASE_CCMR1) || \ 01067 ((BASE) == TIM_DMABASE_CCMR2) || \ 01068 ((BASE) == TIM_DMABASE_CCER) || \ 01069 ((BASE) == TIM_DMABASE_CNT) || \ 01070 ((BASE) == TIM_DMABASE_PSC) || \ 01071 ((BASE) == TIM_DMABASE_ARR) || \ 01072 ((BASE) == TIM_DMABASE_RCR) || \ 01073 ((BASE) == TIM_DMABASE_CCR1) || \ 01074 ((BASE) == TIM_DMABASE_CCR2) || \ 01075 ((BASE) == TIM_DMABASE_CCR3) || \ 01076 ((BASE) == TIM_DMABASE_CCR4) || \ 01077 ((BASE) == TIM_DMABASE_BDTR) || \ 01078 ((BASE) == TIM_DMABASE_DCR)) 01079 01080 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 01081 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 01082 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 01083 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 01084 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 01085 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 01086 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 01087 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 01088 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 01089 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 01090 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 01091 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 01092 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 01093 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 01094 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 01095 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 01096 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 01097 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) 01098 01099 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 01100 01101 /** @brief Set TIM IC prescaler 01102 * @param __HANDLE__: TIM handle 01103 * @param __CHANNEL__: specifies TIM Channel 01104 * @param __ICPSC__: specifies the prescaler value. 01105 * @retval None 01106 */ 01107 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01108 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 01109 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ 01110 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 01111 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) 01112 01113 /** @brief Reset TIM IC prescaler 01114 * @param __HANDLE__: TIM handle 01115 * @param __CHANNEL__: specifies TIM Channel 01116 * @retval None 01117 */ 01118 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 01119 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 01120 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 01121 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 01122 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 01123 01124 01125 /** @brief Set TIM IC polarity 01126 * @param __HANDLE__: TIM handle 01127 * @param __CHANNEL__: specifies TIM Channel 01128 * @param __POLARITY__: specifies TIM Channel Polarity 01129 * @retval None 01130 */ 01131 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01132 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 01133 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ 01134 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ 01135 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) 01136 01137 /** @brief Reset TIM IC polarity 01138 * @param __HANDLE__: TIM handle 01139 * @param __CHANNEL__: specifies TIM Channel 01140 * @retval None 01141 */ 01142 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 01143 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 01144 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 01145 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 01146 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) 01147 01148 /** 01149 * @} 01150 */ 01151 01152 /* Private Functions --------------------------------------------------------*/ 01153 /** @addtogroup TIM_Private_Functions 01154 * @{ 01155 */ 01156 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 01157 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 01158 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 01159 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 01160 void TIM_DMAError(DMA_HandleTypeDef *hdma); 01161 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 01162 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); 01163 /** 01164 * @} 01165 */ 01166 01167 /* Exported macros -----------------------------------------------------------*/ 01168 /** @defgroup TIM_Exported_Macros TIM Exported Macros 01169 * @{ 01170 */ 01171 01172 /** @brief Reset TIM handle state 01173 * @param __HANDLE__: TIM handle. 01174 * @retval None 01175 */ 01176 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 01177 01178 /** 01179 * @brief Enable the TIM peripheral. 01180 * @param __HANDLE__: TIM handle 01181 * @retval None 01182 */ 01183 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 01184 01185 /** 01186 * @brief Enable the TIM main Output. 01187 * @param __HANDLE__: TIM handle 01188 * @retval None 01189 */ 01190 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 01191 01192 /** 01193 * @brief Disable the TIM peripheral. 01194 * @param __HANDLE__: TIM handle 01195 * @retval None 01196 */ 01197 #define __HAL_TIM_DISABLE(__HANDLE__) \ 01198 do { \ 01199 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ 01200 { \ 01201 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ 01202 { \ 01203 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 01204 } \ 01205 } \ 01206 } while(0) 01207 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN 01208 channels have been disabled */ 01209 /** 01210 * @brief Disable the TIM main Output. 01211 * @param __HANDLE__: TIM handle 01212 * @retval None 01213 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 01214 */ 01215 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 01216 do { \ 01217 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ 01218 { \ 01219 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ 01220 { \ 01221 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 01222 } \ 01223 } \ 01224 } while(0) 01225 01226 /** 01227 * @brief Enables the specified TIM interrupt. 01228 * @param __HANDLE__: specifies the TIM Handle. 01229 * @param __INTERRUPT__: specifies the TIM interrupt source to enable. 01230 * This parameter can be one of the following values: 01231 * @arg TIM_IT_UPDATE: Update interrupt 01232 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01233 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01234 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01235 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01236 * @arg TIM_IT_COM: Commutation interrupt 01237 * @arg TIM_IT_TRIGGER: Trigger interrupt 01238 * @arg TIM_IT_BREAK: Break interrupt 01239 * @retval None 01240 */ 01241 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 01242 01243 /** 01244 * @brief Disables the specified TIM interrupt. 01245 * @param __HANDLE__: specifies the TIM Handle. 01246 * @param __INTERRUPT__: specifies the TIM interrupt source to disable. 01247 * This parameter can be one of the following values: 01248 * @arg TIM_IT_UPDATE: Update interrupt 01249 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01250 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01251 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01252 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01253 * @arg TIM_IT_COM: Commutation interrupt 01254 * @arg TIM_IT_TRIGGER: Trigger interrupt 01255 * @arg TIM_IT_BREAK: Break interrupt 01256 * @retval None 01257 */ 01258 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 01259 01260 /** 01261 * @brief Enables the specified DMA request. 01262 * @param __HANDLE__: specifies the TIM Handle. 01263 * @param __DMA__: specifies the TIM DMA request to enable. 01264 * This parameter can be one of the following values: 01265 * @arg TIM_DMA_UPDATE: Update DMA request 01266 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01267 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01268 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01269 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01270 * @arg TIM_DMA_COM: Commutation DMA request 01271 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01272 * @retval None 01273 */ 01274 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 01275 01276 /** 01277 * @brief Disables the specified DMA request. 01278 * @param __HANDLE__: specifies the TIM Handle. 01279 * @param __DMA__: specifies the TIM DMA request to disable. 01280 * This parameter can be one of the following values: 01281 * @arg TIM_DMA_UPDATE: Update DMA request 01282 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01283 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01284 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01285 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01286 * @arg TIM_DMA_COM: Commutation DMA request 01287 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01288 * @retval None 01289 */ 01290 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 01291 01292 /** 01293 * @brief Checks whether the specified TIM interrupt flag is set or not. 01294 * @param __HANDLE__: specifies the TIM Handle. 01295 * @param __FLAG__: specifies the TIM interrupt flag to check. 01296 * This parameter can be one of the following values: 01297 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01298 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01299 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01300 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01301 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01302 * @arg TIM_FLAG_COM: Commutation interrupt flag 01303 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01304 * @arg TIM_FLAG_BREAK: Break interrupt flag 01305 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01306 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01307 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01308 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01309 * @retval The new state of __FLAG__ (TRUE or FALSE). 01310 */ 01311 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 01312 01313 /** 01314 * @brief Clears the specified TIM interrupt flag. 01315 * @param __HANDLE__: specifies the TIM Handle. 01316 * @param __FLAG__: specifies the TIM interrupt flag to clear. 01317 * This parameter can be one of the following values: 01318 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01319 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01320 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01321 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01322 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01323 * @arg TIM_FLAG_COM: Commutation interrupt flag 01324 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01325 * @arg TIM_FLAG_BREAK: Break interrupt flag 01326 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01327 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01328 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01329 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01330 * @retval The new state of __FLAG__ (TRUE or FALSE). 01331 */ 01332 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 01333 01334 /** 01335 * @brief Checks whether the specified TIM interrupt has occurred or not. 01336 * @param __HANDLE__: TIM handle 01337 * @param __INTERRUPT__: specifies the TIM interrupt source to check. 01338 * @retval The state of TIM_IT (SET or RESET). 01339 */ 01340 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 01341 01342 /** 01343 * @brief Clear the TIM interrupt pending bits 01344 * @param __HANDLE__: TIM handle 01345 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 01346 * @retval None 01347 */ 01348 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 01349 01350 /** 01351 * @brief Indicates whether or not the TIM Counter is used as downcounter 01352 * @param __HANDLE__: TIM handle. 01353 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 01354 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder 01355 mode. 01356 */ 01357 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) 01358 01359 /** 01360 * @brief Sets the TIM active prescaler register value on update event. 01361 * @param __HANDLE__: TIM handle. 01362 * @param __PRESC__: specifies the active prescaler register new value. 01363 * @retval None 01364 */ 01365 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 01366 01367 /** 01368 * @brief Sets the TIM Capture Compare Register value on runtime without 01369 * calling another time ConfigChannel function. 01370 * @param __HANDLE__: TIM handle. 01371 * @param __CHANNEL__ : TIM Channels to be configured. 01372 * This parameter can be one of the following values: 01373 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01374 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01375 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01376 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01377 * @param __COMPARE__: specifies the Capture Compare register new value. 01378 * @retval None 01379 */ 01380 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 01381 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) 01382 01383 /** 01384 * @brief Gets the TIM Capture Compare Register value on runtime 01385 * @param __HANDLE__: TIM handle. 01386 * @param __CHANNEL__ : TIM Channel associated with the capture compare register 01387 * This parameter can be one of the following values: 01388 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 01389 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 01390 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 01391 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 01392 * @retval None 01393 */ 01394 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 01395 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) 01396 01397 /** 01398 * @brief Sets the TIM Counter Register value on runtime. 01399 * @param __HANDLE__: TIM handle. 01400 * @param __COUNTER__: specifies the Counter register new value. 01401 * @retval None 01402 */ 01403 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 01404 01405 /** 01406 * @brief Gets the TIM Counter Register value on runtime. 01407 * @param __HANDLE__: TIM handle. 01408 * @retval None 01409 */ 01410 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ 01411 ((__HANDLE__)->Instance->CNT) 01412 01413 /** 01414 * @brief Sets the TIM Autoreload Register value on runtime without calling 01415 * another time any Init function. 01416 * @param __HANDLE__: TIM handle. 01417 * @param __AUTORELOAD__: specifies the Counter register new value. 01418 * @retval None 01419 */ 01420 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 01421 do{ \ 01422 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 01423 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 01424 } while(0) 01425 01426 /** 01427 * @brief Gets the TIM Autoreload Register value on runtime 01428 * @param __HANDLE__: TIM handle. 01429 * @retval None 01430 */ 01431 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ 01432 ((__HANDLE__)->Instance->ARR) 01433 01434 /** 01435 * @brief Sets the TIM Clock Division value on runtime without calling 01436 * another time any Init function. 01437 * @param __HANDLE__: TIM handle. 01438 * @param __CKD__: specifies the clock division value. 01439 * This parameter can be one of the following value: 01440 * @arg TIM_CLOCKDIVISION_DIV1 01441 * @arg TIM_CLOCKDIVISION_DIV2 01442 * @arg TIM_CLOCKDIVISION_DIV4 01443 * @retval None 01444 */ 01445 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 01446 do{ \ 01447 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ 01448 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 01449 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 01450 } while(0) 01451 01452 /** 01453 * @brief Gets the TIM Clock Division value on runtime 01454 * @param __HANDLE__: TIM handle. 01455 * @retval None 01456 */ 01457 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ 01458 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 01459 01460 /** 01461 * @brief Sets the TIM Input Capture prescaler on runtime without calling 01462 * another time HAL_TIM_IC_ConfigChannel() function. 01463 * @param __HANDLE__: TIM handle. 01464 * @param __CHANNEL__ : TIM Channels to be configured. 01465 * This parameter can be one of the following values: 01466 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01467 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01468 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01469 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01470 * @param __ICPSC__: specifies the Input Capture4 prescaler new value. 01471 * This parameter can be one of the following values: 01472 * @arg TIM_ICPSC_DIV1: no prescaler 01473 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01474 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01475 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01476 * @retval None 01477 */ 01478 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01479 do{ \ 01480 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 01481 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 01482 } while(0) 01483 01484 /** 01485 * @brief Gets the TIM Input Capture prescaler on runtime 01486 * @param __HANDLE__: TIM handle. 01487 * @param __CHANNEL__: TIM Channels to be configured. 01488 * This parameter can be one of the following values: 01489 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 01490 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 01491 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 01492 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 01493 * @retval None 01494 */ 01495 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 01496 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 01497 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ 01498 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 01499 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) 01500 01501 /** 01502 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register 01503 * @param __HANDLE__: TIM handle. 01504 * @note When the USR bit of the TIMx_CR1 register is set, only counter 01505 * overflow/underflow generates an update interrupt or DMA request (if 01506 * enabled) 01507 * @retval None 01508 */ 01509 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 01510 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) 01511 01512 /** 01513 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register 01514 * @param __HANDLE__: TIM handle. 01515 * @note When the USR bit of the TIMx_CR1 register is reset, any of the 01516 * following events generate an update interrupt or DMA request (if 01517 * enabled): 01518 * (+) Counter overflow/underflow 01519 * (+) Setting the UG bit 01520 * (+) Update generation through the slave mode controller 01521 * @retval None 01522 */ 01523 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 01524 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) 01525 01526 /** 01527 * @brief Sets the TIM Capture x input polarity on runtime. 01528 * @param __HANDLE__: TIM handle. 01529 * @param __CHANNEL__: TIM Channels to be configured. 01530 * This parameter can be one of the following values: 01531 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01532 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01533 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01534 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01535 * @param __POLARITY__: Polarity for TIx source 01536 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 01537 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 01538 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 01539 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. 01540 * @retval None 01541 */ 01542 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01543 do{ \ 01544 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 01545 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 01546 }while(0) 01547 01548 /** 01549 * @} 01550 */ 01551 01552 /* Include TIM HAL Extension module */ 01553 #include "stm32f1xx_hal_tim_ex.h" 01554 01555 /* Exported functions --------------------------------------------------------*/ 01556 /** @addtogroup TIM_Exported_Functions 01557 * @{ 01558 */ 01559 01560 /** @addtogroup TIM_Exported_Functions_Group1 01561 * @{ 01562 */ 01563 /* Time Base functions ********************************************************/ 01564 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 01565 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 01566 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 01567 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 01568 /* Blocking mode: Polling */ 01569 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 01570 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 01571 /* Non-Blocking mode: Interrupt */ 01572 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 01573 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 01574 /* Non-Blocking mode: DMA */ 01575 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 01576 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 01577 /** 01578 * @} 01579 */ 01580 01581 /** @addtogroup TIM_Exported_Functions_Group2 01582 * @{ 01583 */ 01584 /* Timer Output Compare functions **********************************************/ 01585 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 01586 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 01587 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 01588 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 01589 /* Blocking mode: Polling */ 01590 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01591 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01592 /* Non-Blocking mode: Interrupt */ 01593 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01594 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01595 /* Non-Blocking mode: DMA */ 01596 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01597 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01598 01599 /** 01600 * @} 01601 */ 01602 01603 /** @addtogroup TIM_Exported_Functions_Group3 01604 * @{ 01605 */ 01606 /* Timer PWM functions *********************************************************/ 01607 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 01608 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 01609 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 01610 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 01611 /* Blocking mode: Polling */ 01612 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01613 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01614 /* Non-Blocking mode: Interrupt */ 01615 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01616 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01617 /* Non-Blocking mode: DMA */ 01618 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01619 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01620 /** 01621 * @} 01622 */ 01623 01624 /** @addtogroup TIM_Exported_Functions_Group4 01625 * @{ 01626 */ 01627 /* Timer Input Capture functions ***********************************************/ 01628 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 01629 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 01630 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 01631 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 01632 /* Blocking mode: Polling */ 01633 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01634 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01635 /* Non-Blocking mode: Interrupt */ 01636 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01637 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01638 /* Non-Blocking mode: DMA */ 01639 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01640 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01641 /** 01642 * @} 01643 */ 01644 01645 /** @addtogroup TIM_Exported_Functions_Group5 01646 * @{ 01647 */ 01648 /* Timer One Pulse functions ***************************************************/ 01649 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 01650 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 01651 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 01652 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 01653 /* Blocking mode: Polling */ 01654 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01655 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01656 /* Non-Blocking mode: Interrupt */ 01657 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01658 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01659 /** 01660 * @} 01661 */ 01662 01663 /** @addtogroup TIM_Exported_Functions_Group6 01664 * @{ 01665 */ 01666 /* Timer Encoder functions *****************************************************/ 01667 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); 01668 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 01669 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 01670 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 01671 /* Blocking mode: Polling */ 01672 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01673 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01674 /* Non-Blocking mode: Interrupt */ 01675 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01676 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01677 /* Non-Blocking mode: DMA */ 01678 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 01679 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01680 01681 /** 01682 * @} 01683 */ 01684 01685 /** @addtogroup TIM_Exported_Functions_Group7 01686 * @{ 01687 */ 01688 /* Interrupt Handler functions **********************************************/ 01689 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 01690 /** 01691 * @} 01692 */ 01693 01694 /** @addtogroup TIM_Exported_Functions_Group8 01695 * @{ 01696 */ 01697 /* Control functions *********************************************************/ 01698 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 01699 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 01700 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); 01701 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); 01702 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); 01703 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); 01704 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 01705 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 01706 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 01707 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 01708 uint32_t *BurstBuffer, uint32_t BurstLength); 01709 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 01710 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 01711 uint32_t *BurstBuffer, uint32_t BurstLength); 01712 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 01713 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 01714 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 01715 01716 /** 01717 * @} 01718 */ 01719 01720 /** @addtogroup TIM_Exported_Functions_Group9 01721 * @{ 01722 */ 01723 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 01724 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 01725 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 01726 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 01727 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 01728 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 01729 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 01730 /** 01731 * @} 01732 */ 01733 01734 /** @addtogroup TIM_Exported_Functions_Group10 01735 * @{ 01736 */ 01737 /* Peripheral State functions **************************************************/ 01738 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 01739 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 01740 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 01741 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 01742 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 01743 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 01744 01745 /** 01746 * @} 01747 */ 01748 01749 /** 01750 * @} 01751 */ 01752 01753 /** 01754 * @} 01755 */ 01756 01757 /** 01758 * @} 01759 */ 01760 01761 #ifdef __cplusplus 01762 } 01763 #endif 01764 01765 #endif /* __STM32F1xx_HAL_TIM_H */ 01766 01767 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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