stm32f1xx_hal_tim.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   TIM HAL module driver
00008   *          This file provides firmware functions to manage the following 
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption 
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start 
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIMER Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output 
00047 
00048             ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions 
00052          depending from feature used :
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059 
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064              __HAL_RCC_GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066 
00067      (#) The external Clock can be configured, if needed (the default clock is the 
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before 
00070          any start function.
00071 
00072      (#) Configure the TIM in the desired functioning mode using one of the 
00073        Initialization function of this driver:
00074        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00075        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 
00076             Output Compare signal.
00077        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 
00078             PWM signal.
00079        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 
00080             external signal.
00081          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 
00082               in One Pulse Mode.
00083        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00084 
00085      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00086            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00087            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00088            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00089            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00090            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00091            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00092 
00093      (#) The DMA Burst is managed with the two following functions:
00094          HAL_TIM_DMABurst_WriteStart()
00095          HAL_TIM_DMABurst_ReadStart()
00096 
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127 
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32f1xx_hal.h"
00130 
00131 /** @addtogroup STM32F1xx_HAL_Driver
00132   * @{
00133   */
00134 
00135 /** @defgroup TIM TIM
00136   * @brief TIM HAL module driver
00137   * @{
00138   */
00139 
00140 #ifdef HAL_TIM_MODULE_ENABLED
00141 
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /* Private macro -------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /* Private function prototypes -----------------------------------------------*/
00147 /** @defgroup TIM_Private_Functions TIM Private Functions
00148   * @{
00149   */
00150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00153 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00154 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00155                        uint32_t TIM_ICFilter);
00156 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00157 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00158                        uint32_t TIM_ICFilter);
00159 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00160                        uint32_t TIM_ICFilter);
00161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
00162                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
00163 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
00164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00167                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00168 
00169 /**
00170   * @}
00171   */
00172 
00173 /* Exported functions ---------------------------------------------------------*/
00174 
00175 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00176   * @{
00177   */
00178 
00179 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions 
00180  *  @brief    Time Base functions 
00181  *
00182 @verbatim 
00183   ==============================================================================
00184               ##### Time Base functions #####
00185   ==============================================================================
00186   [..]
00187     This section provides functions allowing to:
00188     (+) Initialize and configure the TIM base.
00189     (+) De-initialize the TIM base.
00190     (+) Start the Time Base.
00191     (+) Stop the Time Base.
00192     (+) Start the Time Base and enable interrupt.
00193     (+) Stop the Time Base and disable interrupt.
00194     (+) Start the Time Base and enable DMA transfer.
00195     (+) Stop the Time Base and disable DMA transfer.
00196 
00197 @endverbatim
00198   * @{
00199   */
00200 /**
00201   * @brief  Initializes the TIM Time base Unit according to the specified
00202   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00203   * @param  htim : TIM Base handle
00204   * @retval HAL status
00205   */
00206 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00207 {
00208   /* Check the TIM handle allocation */
00209   if(htim == NULL)
00210   {
00211     return HAL_ERROR;
00212   }
00213 
00214   /* Check the parameters */
00215   assert_param(IS_TIM_INSTANCE(htim->Instance));
00216   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00217   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00218 
00219   if(htim->State == HAL_TIM_STATE_RESET)
00220   {
00221     /* Allocate lock resource and initialize it */
00222     htim->Lock = HAL_UNLOCKED;
00223     
00224     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00225     HAL_TIM_Base_MspInit(htim);
00226   }
00227 
00228   /* Set the TIM state */
00229   htim->State= HAL_TIM_STATE_BUSY;
00230 
00231   /* Set the Time Base configuration */
00232   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00233 
00234   /* Initialize the TIM state*/
00235   htim->State= HAL_TIM_STATE_READY;
00236 
00237   return HAL_OK;
00238 }
00239 
00240 /**
00241   * @brief  DeInitializes the TIM Base peripheral 
00242   * @param  htim : TIM Base handle
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00246 {
00247   /* Check the parameters */
00248   assert_param(IS_TIM_INSTANCE(htim->Instance));
00249 
00250   htim->State = HAL_TIM_STATE_BUSY;
00251 
00252   /* Disable the TIM Peripheral Clock */
00253   __HAL_TIM_DISABLE(htim);
00254 
00255   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00256   HAL_TIM_Base_MspDeInit(htim);
00257 
00258   /* Change TIM state */
00259   htim->State = HAL_TIM_STATE_RESET;
00260 
00261   /* Release Lock */
00262   __HAL_UNLOCK(htim);
00263 
00264   return HAL_OK;
00265 }
00266 
00267 /**
00268   * @brief  Initializes the TIM Base MSP.
00269   * @param  htim : TIM handle
00270   * @retval None
00271   */
00272 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(htim);
00276   /* NOTE : This function Should not be modified, when the callback is needed,
00277             the HAL_TIM_Base_MspInit could be implemented in the user file
00278    */
00279 }
00280 
00281 /**
00282   * @brief  DeInitializes TIM Base MSP.
00283   * @param  htim : TIM handle
00284   * @retval None
00285   */
00286 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00287 {
00288   /* Prevent unused argument(s) compilation warning */
00289   UNUSED(htim);
00290   /* NOTE : This function Should not be modified, when the callback is needed,
00291             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00292    */
00293 }
00294 
00295 
00296 /**
00297   * @brief  Starts the TIM Base generation.
00298   * @param  htim : TIM handle
00299   * @retval HAL status
00300 */
00301 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00302 {
00303   /* Check the parameters */
00304   assert_param(IS_TIM_INSTANCE(htim->Instance));
00305 
00306   /* Set the TIM state */
00307   htim->State= HAL_TIM_STATE_BUSY;
00308 
00309   /* Enable the Peripheral */
00310   __HAL_TIM_ENABLE(htim);
00311 
00312   /* Change the TIM state*/
00313   htim->State= HAL_TIM_STATE_READY;
00314 
00315   /* Return function status */
00316   return HAL_OK;
00317 }
00318 
00319 /**
00320   * @brief  Stops the TIM Base generation.
00321   * @param  htim : TIM handle
00322   * @retval HAL status
00323 */
00324 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00325 {
00326   /* Check the parameters */
00327   assert_param(IS_TIM_INSTANCE(htim->Instance));
00328 
00329   /* Set the TIM state */
00330   htim->State= HAL_TIM_STATE_BUSY;
00331 
00332   /* Disable the Peripheral */
00333   __HAL_TIM_DISABLE(htim);
00334 
00335   /* Change the TIM state*/
00336   htim->State= HAL_TIM_STATE_READY;
00337 
00338   /* Return function status */
00339   return HAL_OK;
00340 }
00341 
00342 /**
00343   * @brief  Starts the TIM Base generation in interrupt mode.
00344   * @param  htim : TIM handle
00345   * @retval HAL status
00346 */
00347 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00348 {
00349   /* Check the parameters */
00350   assert_param(IS_TIM_INSTANCE(htim->Instance));
00351 
00352    /* Enable the TIM Update interrupt */
00353    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00354 
00355    /* Enable the Peripheral */
00356   __HAL_TIM_ENABLE(htim);
00357 
00358   /* Return function status */
00359   return HAL_OK;
00360 }
00361 
00362 /**
00363   * @brief  Stops the TIM Base generation in interrupt mode.
00364   * @param  htim : TIM handle
00365   * @retval HAL status
00366 */
00367 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00368 {
00369   /* Check the parameters */
00370   assert_param(IS_TIM_INSTANCE(htim->Instance));
00371   /* Disable the TIM Update interrupt */
00372   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00373 
00374   /* Disable the Peripheral */
00375   __HAL_TIM_DISABLE(htim);
00376 
00377   /* Return function status */
00378   return HAL_OK;
00379 }
00380 
00381 /**
00382   * @brief  Starts the TIM Base generation in DMA mode.
00383   * @param  htim : TIM handle
00384   * @param  pData : The source Buffer address.
00385   * @param  Length : The length of data to be transferred from memory to peripheral.
00386   * @retval HAL status
00387 */
00388 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00389 {
00390   /* Check the parameters */
00391   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00392 
00393   if((htim->State == HAL_TIM_STATE_BUSY))
00394   {
00395      return HAL_BUSY;
00396   }
00397   else if((htim->State == HAL_TIM_STATE_READY))
00398   {
00399     if((pData == 0 ) && (Length > 0))
00400     {
00401       return HAL_ERROR;
00402     }
00403     else
00404     {
00405       htim->State = HAL_TIM_STATE_BUSY;
00406     }
00407   }
00408   /* Set the DMA Period elapsed callback */
00409   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00410 
00411   /* Set the DMA error callback */
00412   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00413 
00414   /* Enable the DMA channel */
00415   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00416 
00417   /* Enable the TIM Update DMA request */
00418   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00419 
00420   /* Enable the Peripheral */
00421   __HAL_TIM_ENABLE(htim);
00422 
00423   /* Return function status */
00424   return HAL_OK;
00425 }
00426 
00427 /**
00428   * @brief  Stops the TIM Base generation in DMA mode.
00429   * @param  htim : TIM handle
00430   * @retval HAL status
00431 */
00432 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00433 {
00434   /* Check the parameters */
00435   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00436 
00437   /* Disable the TIM Update DMA request */
00438   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00439 
00440   /* Disable the Peripheral */
00441   __HAL_TIM_DISABLE(htim);
00442 
00443   /* Change the htim state */
00444   htim->State = HAL_TIM_STATE_READY;
00445 
00446   /* Return function status */
00447   return HAL_OK;
00448 }
00449 
00450 /**
00451   * @}
00452   */
00453 
00454 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 
00455  *  @brief    Time Output Compare functions 
00456  *
00457 @verbatim 
00458   ==============================================================================
00459                   ##### Time Output Compare functions #####
00460   ==============================================================================
00461   [..]
00462     This section provides functions allowing to:
00463     (+) Initialize and configure the TIM Output Compare.
00464     (+) De-initialize the TIM Output Compare.
00465     (+) Start the Time Output Compare.
00466     (+) Stop the Time Output Compare.
00467     (+) Start the Time Output Compare and enable interrupt.
00468     (+) Stop the Time Output Compare and disable interrupt.
00469     (+) Start the Time Output Compare and enable DMA transfer.
00470     (+) Stop the Time Output Compare and disable DMA transfer.
00471 
00472 @endverbatim
00473   * @{
00474   */
00475 /**
00476   * @brief  Initializes the TIM Output Compare according to the specified
00477   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00478   * @param  htim : TIM Output Compare handle
00479   * @retval HAL status
00480   */
00481 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00482 {
00483   /* Check the TIM handle allocation */
00484   if(htim == NULL)
00485   {
00486     return HAL_ERROR;
00487   }
00488 
00489   /* Check the parameters */
00490   assert_param(IS_TIM_INSTANCE(htim->Instance));
00491   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00492   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00493 
00494   if(htim->State == HAL_TIM_STATE_RESET)
00495   {
00496     /* Allocate lock resource and initialize it */
00497     htim->Lock = HAL_UNLOCKED;
00498     
00499     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00500     HAL_TIM_OC_MspInit(htim);
00501   }
00502 
00503   /* Set the TIM state */
00504   htim->State= HAL_TIM_STATE_BUSY;
00505 
00506   /* Init the base time for the Output Compare */
00507   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00508 
00509   /* Initialize the TIM state*/
00510   htim->State= HAL_TIM_STATE_READY;
00511 
00512   return HAL_OK;
00513 }
00514 
00515 /**
00516   * @brief  DeInitializes the TIM peripheral 
00517   * @param  htim : TIM Output Compare handle
00518   * @retval HAL status
00519   */
00520 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00521 {
00522   /* Check the parameters */
00523   assert_param(IS_TIM_INSTANCE(htim->Instance));
00524 
00525    htim->State = HAL_TIM_STATE_BUSY;
00526 
00527   /* Disable the TIM Peripheral Clock */
00528   __HAL_TIM_DISABLE(htim);
00529 
00530   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00531   HAL_TIM_OC_MspDeInit(htim);
00532 
00533   /* Change TIM state */
00534   htim->State = HAL_TIM_STATE_RESET;
00535 
00536   /* Release Lock */
00537   __HAL_UNLOCK(htim);
00538 
00539   return HAL_OK;
00540 }
00541 
00542 /**
00543   * @brief  Initializes the TIM Output Compare MSP.
00544   * @param  htim : TIM handle
00545   * @retval None
00546   */
00547 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00548 {
00549   /* Prevent unused argument(s) compilation warning */
00550   UNUSED(htim);
00551   /* NOTE : This function Should not be modified, when the callback is needed,
00552             the HAL_TIM_OC_MspInit could be implemented in the user file
00553    */
00554 }
00555 
00556 /**
00557   * @brief  DeInitializes TIM Output Compare MSP.
00558   * @param  htim : TIM handle
00559   * @retval None
00560   */
00561 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00562 {
00563   /* Prevent unused argument(s) compilation warning */
00564   UNUSED(htim);
00565   /* NOTE : This function Should not be modified, when the callback is needed,
00566             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00567    */
00568 }
00569 
00570 /**
00571   * @brief  Starts the TIM Output Compare signal generation.
00572   * @param  htim : TIM Output Compare handle 
00573   * @param  Channel : TIM Channel to be enabled
00574   *          This parameter can be one of the following values:
00575   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00576   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00577   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00578   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
00579   * @retval HAL status
00580 */
00581 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00582 {
00583   /* Check the parameters */
00584   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00585 
00586   /* Enable the Output compare channel */
00587   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00588 
00589   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00590   {
00591     /* Enable the main output */
00592     __HAL_TIM_MOE_ENABLE(htim);
00593   }
00594 
00595   /* Enable the Peripheral */
00596   __HAL_TIM_ENABLE(htim);
00597 
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601 
00602 /**
00603   * @brief  Stops the TIM Output Compare signal generation.
00604   * @param  htim : TIM handle
00605   * @param  Channel : TIM Channel to be disabled
00606   *          This parameter can be one of the following values:
00607   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00608   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00609   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00610   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00611   * @retval HAL status
00612 */
00613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00617 
00618   /* Disable the Output compare channel */
00619   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00620 
00621   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00622   {
00623     /* Disable the Main Ouput */
00624     __HAL_TIM_MOE_DISABLE(htim);
00625   }
00626 
00627   /* Disable the Peripheral */
00628   __HAL_TIM_DISABLE(htim);
00629 
00630   /* Return function status */
00631   return HAL_OK;
00632 }
00633 
00634 /**
00635   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00636   * @param  htim : TIM OC handle
00637   * @param  Channel : TIM Channel to be enabled
00638   *          This parameter can be one of the following values:
00639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00641   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00642   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00643   * @retval HAL status
00644 */
00645 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00646 {
00647   /* Check the parameters */
00648   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00649 
00650   switch (Channel)
00651   {
00652     case TIM_CHANNEL_1:
00653     {
00654       /* Enable the TIM Capture/Compare 1 interrupt */
00655       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00656     }
00657     break;
00658 
00659     case TIM_CHANNEL_2:
00660     {
00661       /* Enable the TIM Capture/Compare 2 interrupt */
00662       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00663     }
00664     break;
00665 
00666     case TIM_CHANNEL_3:
00667     {
00668       /* Enable the TIM Capture/Compare 3 interrupt */
00669       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00670     }
00671     break;
00672 
00673     case TIM_CHANNEL_4:
00674     {
00675       /* Enable the TIM Capture/Compare 4 interrupt */
00676       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00677     }
00678     break;
00679 
00680     default:
00681     break;
00682   }
00683 
00684   /* Enable the Output compare channel */
00685   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00686 
00687   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00688   {
00689     /* Enable the main output */
00690     __HAL_TIM_MOE_ENABLE(htim);
00691   }
00692 
00693   /* Enable the Peripheral */
00694   __HAL_TIM_ENABLE(htim);
00695 
00696   /* Return function status */
00697   return HAL_OK;
00698 }
00699 
00700 /**
00701   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00702   * @param  htim : TIM Output Compare handle
00703   * @param  Channel : TIM Channel to be disabled
00704   *          This parameter can be one of the following values:
00705   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00706   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00707   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00708   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00709   * @retval HAL status
00710 */
00711 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00712 {
00713   /* Check the parameters */
00714   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00715 
00716   switch (Channel)
00717   {
00718     case TIM_CHANNEL_1:
00719     {
00720       /* Disable the TIM Capture/Compare 1 interrupt */
00721       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00722     }
00723     break;
00724 
00725     case TIM_CHANNEL_2:
00726     {
00727       /* Disable the TIM Capture/Compare 2 interrupt */
00728       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00729     }
00730     break;
00731 
00732     case TIM_CHANNEL_3:
00733     {
00734       /* Disable the TIM Capture/Compare 3 interrupt */
00735       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00736     }
00737     break;
00738 
00739     case TIM_CHANNEL_4:
00740     {
00741       /* Disable the TIM Capture/Compare 4 interrupt */
00742       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00743     }
00744     break;
00745 
00746     default:
00747     break;
00748   }
00749 
00750   /* Disable the Output compare channel */
00751   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00752 
00753   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00754   {
00755     /* Disable the Main Ouput */
00756     __HAL_TIM_MOE_DISABLE(htim);
00757   }
00758 
00759   /* Disable the Peripheral */
00760   __HAL_TIM_DISABLE(htim);
00761 
00762   /* Return function status */
00763   return HAL_OK;
00764 }
00765 
00766 /**
00767   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00768   * @param  htim : TIM Output Compare handle
00769   * @param  Channel : TIM Channel to be enabled
00770   *          This parameter can be one of the following values:
00771   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00772   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00773   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00774   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00775   * @param  pData : The source Buffer address.
00776   * @param  Length : The length of data to be transferred from memory to TIM peripheral
00777   * @retval HAL status
00778 */
00779 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00783 
00784   if((htim->State == HAL_TIM_STATE_BUSY))
00785   {
00786      return HAL_BUSY;
00787   }
00788   else if((htim->State == HAL_TIM_STATE_READY))
00789   {
00790     if(((uint32_t)pData == 0 ) && (Length > 0))
00791     {
00792       return HAL_ERROR;
00793     }
00794     else
00795     {
00796       htim->State = HAL_TIM_STATE_BUSY;
00797     }
00798   }
00799   switch (Channel)
00800   {
00801     case TIM_CHANNEL_1:
00802     {
00803       /* Set the DMA Period elapsed callback */
00804       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00805 
00806       /* Set the DMA error callback */
00807       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00808 
00809       /* Enable the DMA channel */
00810       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00811 
00812       /* Enable the TIM Capture/Compare 1 DMA request */
00813       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00814     }
00815     break;
00816 
00817     case TIM_CHANNEL_2:
00818     {
00819       /* Set the DMA Period elapsed callback */
00820       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00821 
00822       /* Set the DMA error callback */
00823       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00824 
00825       /* Enable the DMA channel */
00826       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00827 
00828       /* Enable the TIM Capture/Compare 2 DMA request */
00829       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00830     }
00831     break;
00832 
00833     case TIM_CHANNEL_3:
00834     {
00835       /* Set the DMA Period elapsed callback */
00836       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00837 
00838       /* Set the DMA error callback */
00839       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00840 
00841       /* Enable the DMA channel */
00842       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00843 
00844       /* Enable the TIM Capture/Compare 3 DMA request */
00845       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00846     }
00847     break;
00848 
00849     case TIM_CHANNEL_4:
00850     {
00851      /* Set the DMA Period elapsed callback */
00852       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00853 
00854       /* Set the DMA error callback */
00855       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00856 
00857       /* Enable the DMA channel */
00858       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00859 
00860       /* Enable the TIM Capture/Compare 4 DMA request */
00861       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00862     }
00863     break;
00864 
00865     default:
00866     break;
00867   }
00868 
00869   /* Enable the Output compare channel */
00870   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00871 
00872   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00873   {
00874     /* Enable the main output */
00875     __HAL_TIM_MOE_ENABLE(htim);
00876   }
00877 
00878   /* Enable the Peripheral */
00879   __HAL_TIM_ENABLE(htim);
00880 
00881   /* Return function status */
00882   return HAL_OK;
00883 }
00884 
00885 /**
00886   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00887   * @param  htim : TIM Output Compare handle
00888   * @param  Channel : TIM Channel to be disabled
00889   *          This parameter can be one of the following values:
00890   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00891   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00892   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00893   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00894   * @retval HAL status
00895 */
00896 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00897 {
00898   /* Check the parameters */
00899   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00900 
00901   switch (Channel)
00902   {
00903     case TIM_CHANNEL_1:
00904     {
00905       /* Disable the TIM Capture/Compare 1 DMA request */
00906       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00907     }
00908     break;
00909 
00910     case TIM_CHANNEL_2:
00911     {
00912       /* Disable the TIM Capture/Compare 2 DMA request */
00913       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00914     }
00915     break;
00916 
00917     case TIM_CHANNEL_3:
00918     {
00919       /* Disable the TIM Capture/Compare 3 DMA request */
00920       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00921     }
00922     break;
00923 
00924     case TIM_CHANNEL_4:
00925     {
00926       /* Disable the TIM Capture/Compare 4 interrupt */
00927       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00928     }
00929     break;
00930 
00931     default:
00932     break;
00933   }
00934 
00935   /* Disable the Output compare channel */
00936   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00937 
00938   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00939   {
00940     /* Disable the Main Ouput */
00941     __HAL_TIM_MOE_DISABLE(htim);
00942   }
00943 
00944   /* Disable the Peripheral */
00945   __HAL_TIM_DISABLE(htim);
00946 
00947   /* Change the htim state */
00948   htim->State = HAL_TIM_STATE_READY;
00949 
00950   /* Return function status */
00951   return HAL_OK;
00952 }
00953 
00954 /**
00955   * @}
00956   */
00957 
00958 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 
00959  *  @brief    Time PWM functions 
00960  *
00961 @verbatim 
00962   ==============================================================================
00963                           ##### Time PWM functions #####
00964   ==============================================================================
00965   [..]
00966     This section provides functions allowing to:
00967     (+) Initialize and configure the TIM PWM.
00968     (+) De-initialize the TIM PWM.
00969     (+) Start the Time PWM.
00970     (+) Stop the Time PWM.
00971     (+) Start the Time PWM and enable interrupt.
00972     (+) Stop the Time PWM and disable interrupt.
00973     (+) Start the Time PWM and enable DMA transfer.
00974     (+) Stop the Time PWM and disable DMA transfer.
00975 
00976 @endverbatim
00977   * @{
00978   */
00979 /**
00980   * @brief  Initializes the TIM PWM Time Base according to the specified
00981   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00982   * @param  htim : TIM handle
00983   * @retval HAL status
00984   */
00985 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
00986 {
00987   /* Check the TIM handle allocation */
00988   if(htim == NULL)
00989   {
00990     return HAL_ERROR;
00991   }
00992 
00993   /* Check the parameters */
00994   assert_param(IS_TIM_INSTANCE(htim->Instance));
00995   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00996   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00997 
00998   if(htim->State == HAL_TIM_STATE_RESET)
00999   {
01000     /* Allocate lock resource and initialize it */
01001     htim->Lock = HAL_UNLOCKED;
01002     
01003     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01004     HAL_TIM_PWM_MspInit(htim);
01005   }
01006 
01007   /* Set the TIM state */
01008   htim->State= HAL_TIM_STATE_BUSY;
01009 
01010   /* Init the base time for the PWM */
01011   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01012 
01013   /* Initialize the TIM state*/
01014   htim->State= HAL_TIM_STATE_READY;
01015 
01016   return HAL_OK;
01017 }
01018 
01019 /**
01020   * @brief  DeInitializes the TIM peripheral 
01021   * @param  htim : TIM handle
01022   * @retval HAL status
01023   */
01024 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01025 {
01026   /* Check the parameters */
01027   assert_param(IS_TIM_INSTANCE(htim->Instance));
01028 
01029   htim->State = HAL_TIM_STATE_BUSY;
01030 
01031   /* Disable the TIM Peripheral Clock */
01032   __HAL_TIM_DISABLE(htim);
01033 
01034   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01035   HAL_TIM_PWM_MspDeInit(htim);
01036 
01037   /* Change TIM state */
01038   htim->State = HAL_TIM_STATE_RESET;
01039 
01040   /* Release Lock */
01041   __HAL_UNLOCK(htim);
01042 
01043   return HAL_OK;
01044 }
01045 
01046 /**
01047   * @brief  Initializes the TIM PWM MSP.
01048   * @param  htim : TIM handle
01049   * @retval None
01050   */
01051 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01052 {
01053   /* Prevent unused argument(s) compilation warning */
01054   UNUSED(htim);
01055   /* NOTE : This function Should not be modified, when the callback is needed,
01056             the HAL_TIM_PWM_MspInit could be implemented in the user file
01057    */
01058 }
01059 
01060 /**
01061   * @brief  DeInitializes TIM PWM MSP.
01062   * @param  htim : TIM handle
01063   * @retval None
01064   */
01065 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01066 {
01067   /* Prevent unused argument(s) compilation warning */
01068   UNUSED(htim);
01069   /* NOTE : This function Should not be modified, when the callback is needed,
01070             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01071    */
01072 }
01073 
01074 /**
01075   * @brief  Starts the PWM signal generation.
01076   * @param  htim : TIM handle
01077   * @param  Channel : TIM Channels to be enabled
01078   *          This parameter can be one of the following values:
01079   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01080   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01081   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01082   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01083   * @retval HAL status
01084 */
01085 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01086 {
01087   /* Check the parameters */
01088   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01089 
01090   /* Enable the Capture compare channel */
01091   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01092 
01093   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01094   {
01095     /* Enable the main output */
01096     __HAL_TIM_MOE_ENABLE(htim);
01097   }
01098 
01099   /* Enable the Peripheral */
01100   __HAL_TIM_ENABLE(htim);
01101 
01102   /* Return function status */
01103   return HAL_OK;
01104 }
01105 
01106 /**
01107   * @brief  Stops the PWM signal generation.
01108   * @param  htim : TIM handle
01109   * @param  Channel : TIM Channels to be disabled
01110   *          This parameter can be one of the following values:
01111   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01112   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01113   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01114   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01115   * @retval HAL status
01116 */
01117 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01118 {
01119   /* Check the parameters */
01120   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01121 
01122   /* Disable the Capture compare channel */
01123   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01124 
01125   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01126   {
01127     /* Disable the Main Ouput */
01128     __HAL_TIM_MOE_DISABLE(htim);
01129   }
01130 
01131   /* Disable the Peripheral */
01132   __HAL_TIM_DISABLE(htim);
01133 
01134   /* Change the htim state */
01135   htim->State = HAL_TIM_STATE_READY;
01136 
01137   /* Return function status */
01138   return HAL_OK;
01139 }
01140 
01141 /**
01142   * @brief  Starts the PWM signal generation in interrupt mode.
01143   * @param  htim : TIM handle
01144   * @param  Channel : TIM Channel to be disabled
01145   *          This parameter can be one of the following values:
01146   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01147   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01148   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01149   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01150   * @retval HAL status
01151 */
01152 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01153 {
01154   /* Check the parameters */
01155   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01156 
01157   switch (Channel)
01158   {
01159     case TIM_CHANNEL_1:
01160     {
01161       /* Enable the TIM Capture/Compare 1 interrupt */
01162       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01163     }
01164     break;
01165 
01166     case TIM_CHANNEL_2:
01167     {
01168       /* Enable the TIM Capture/Compare 2 interrupt */
01169       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01170     }
01171     break;
01172 
01173     case TIM_CHANNEL_3:
01174     {
01175       /* Enable the TIM Capture/Compare 3 interrupt */
01176       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01177     }
01178     break;
01179 
01180     case TIM_CHANNEL_4:
01181     {
01182       /* Enable the TIM Capture/Compare 4 interrupt */
01183       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01184     }
01185     break;
01186 
01187     default:
01188     break;
01189   }
01190 
01191   /* Enable the Capture compare channel */
01192   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01193 
01194   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01195   {
01196     /* Enable the main output */
01197     __HAL_TIM_MOE_ENABLE(htim);
01198   }
01199 
01200   /* Enable the Peripheral */
01201   __HAL_TIM_ENABLE(htim);
01202 
01203   /* Return function status */
01204   return HAL_OK;
01205 }
01206 
01207 /**
01208   * @brief  Stops the PWM signal generation in interrupt mode.
01209   * @param  htim : TIM handle
01210   * @param  Channel : TIM Channels to be disabled
01211   *          This parameter can be one of the following values:
01212   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01213   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01214   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01215   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01216   * @retval HAL status
01217 */
01218 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01219 {
01220   /* Check the parameters */
01221   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01222 
01223   switch (Channel)
01224   {
01225     case TIM_CHANNEL_1:
01226     {
01227       /* Disable the TIM Capture/Compare 1 interrupt */
01228       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01229     }
01230     break;
01231 
01232     case TIM_CHANNEL_2:
01233     {
01234       /* Disable the TIM Capture/Compare 2 interrupt */
01235       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01236     }
01237     break;
01238 
01239     case TIM_CHANNEL_3:
01240     {
01241       /* Disable the TIM Capture/Compare 3 interrupt */
01242       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01243     }
01244     break;
01245 
01246     case TIM_CHANNEL_4:
01247     {
01248       /* Disable the TIM Capture/Compare 4 interrupt */
01249       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01250     }
01251     break;
01252 
01253     default:
01254     break;
01255   }
01256 
01257   /* Disable the Capture compare channel */
01258   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01259 
01260   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01261   {
01262     /* Disable the Main Ouput */
01263     __HAL_TIM_MOE_DISABLE(htim);
01264   }
01265 
01266   /* Disable the Peripheral */
01267   __HAL_TIM_DISABLE(htim);
01268 
01269   /* Return function status */
01270   return HAL_OK;
01271 }
01272 
01273 /**
01274   * @brief  Starts the TIM PWM signal generation in DMA mode.
01275   * @param  htim : TIM handle
01276   * @param  Channel : TIM Channels to be enabled
01277   *          This parameter can be one of the following values:
01278   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01279   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01280   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01281   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01282   * @param  pData : The source Buffer address.
01283   * @param  Length : The length of data to be transferred from memory to TIM peripheral
01284   * @retval HAL status
01285 */
01286 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01287 {
01288   /* Check the parameters */
01289   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01290 
01291   if((htim->State == HAL_TIM_STATE_BUSY))
01292   {
01293      return HAL_BUSY;
01294   }
01295   else if((htim->State == HAL_TIM_STATE_READY))
01296   {
01297     if(((uint32_t)pData == 0 ) && (Length > 0))
01298     {
01299       return HAL_ERROR;
01300     }
01301     else
01302     {
01303       htim->State = HAL_TIM_STATE_BUSY;
01304     }
01305   }
01306   switch (Channel)
01307   {
01308     case TIM_CHANNEL_1:
01309     {
01310       /* Set the DMA Period elapsed callback */
01311       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01312 
01313       /* Set the DMA error callback */
01314       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01315 
01316       /* Enable the DMA channel */
01317       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01318 
01319       /* Enable the TIM Capture/Compare 1 DMA request */
01320       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01321     }
01322     break;
01323 
01324     case TIM_CHANNEL_2:
01325     {
01326       /* Set the DMA Period elapsed callback */
01327       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01328 
01329       /* Set the DMA error callback */
01330       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01331 
01332       /* Enable the DMA channel */
01333       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01334 
01335       /* Enable the TIM Capture/Compare 2 DMA request */
01336       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01337     }
01338     break;
01339 
01340     case TIM_CHANNEL_3:
01341     {
01342       /* Set the DMA Period elapsed callback */
01343       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01344 
01345       /* Set the DMA error callback */
01346       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01347 
01348       /* Enable the DMA channel */
01349       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01350 
01351       /* Enable the TIM Output Capture/Compare 3 request */
01352       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01353     }
01354     break;
01355 
01356     case TIM_CHANNEL_4:
01357     {
01358      /* Set the DMA Period elapsed callback */
01359       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01360 
01361       /* Set the DMA error callback */
01362       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01363 
01364       /* Enable the DMA channel */
01365       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01366 
01367       /* Enable the TIM Capture/Compare 4 DMA request */
01368       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01369     }
01370     break;
01371 
01372     default:
01373     break;
01374   }
01375 
01376   /* Enable the Capture compare channel */
01377   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01378 
01379   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01380   {
01381     /* Enable the main output */
01382     __HAL_TIM_MOE_ENABLE(htim);
01383   }
01384 
01385   /* Enable the Peripheral */
01386   __HAL_TIM_ENABLE(htim);
01387 
01388   /* Return function status */
01389   return HAL_OK;
01390 }
01391 
01392 /**
01393   * @brief  Stops the TIM PWM signal generation in DMA mode.
01394   * @param  htim : TIM handle
01395   * @param  Channel : TIM Channels to be disabled
01396   *          This parameter can be one of the following values:
01397   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01398   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01399   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01400   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01401   * @retval HAL status
01402 */
01403 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01404 {
01405   /* Check the parameters */
01406   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01407 
01408   switch (Channel)
01409   {
01410     case TIM_CHANNEL_1:
01411     {
01412       /* Disable the TIM Capture/Compare 1 DMA request */
01413       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01414     }
01415     break;
01416 
01417     case TIM_CHANNEL_2:
01418     {
01419       /* Disable the TIM Capture/Compare 2 DMA request */
01420       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01421     }
01422     break;
01423 
01424     case TIM_CHANNEL_3:
01425     {
01426       /* Disable the TIM Capture/Compare 3 DMA request */
01427       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01428     }
01429     break;
01430 
01431     case TIM_CHANNEL_4:
01432     {
01433       /* Disable the TIM Capture/Compare 4 interrupt */
01434       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01435     }
01436     break;
01437 
01438     default:
01439     break;
01440   }
01441 
01442   /* Disable the Capture compare channel */
01443   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01444 
01445   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01446   {
01447     /* Disable the Main Ouput */
01448     __HAL_TIM_MOE_DISABLE(htim);
01449   }
01450 
01451   /* Disable the Peripheral */
01452   __HAL_TIM_DISABLE(htim);
01453 
01454   /* Change the htim state */
01455   htim->State = HAL_TIM_STATE_READY;
01456 
01457   /* Return function status */
01458   return HAL_OK;
01459 }
01460 
01461 /**
01462   * @}
01463   */
01464 
01465 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 
01466  *  @brief    Time Input Capture functions 
01467  *
01468 @verbatim 
01469   ==============================================================================
01470               ##### Time Input Capture functions #####
01471   ==============================================================================
01472  [..]
01473    This section provides functions allowing to:
01474    (+) Initialize and configure the TIM Input Capture.
01475    (+) De-initialize the TIM Input Capture.
01476    (+) Start the Time Input Capture.
01477    (+) Stop the Time Input Capture.
01478    (+) Start the Time Input Capture and enable interrupt.
01479    (+) Stop the Time Input Capture and disable interrupt.
01480    (+) Start the Time Input Capture and enable DMA transfer.
01481    (+) Stop the Time Input Capture and disable DMA transfer.
01482 
01483 @endverbatim
01484   * @{
01485   */
01486 /**
01487   * @brief  Initializes the TIM Input Capture Time base according to the specified
01488   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01489   * @param  htim : TIM Input Capture handle
01490   * @retval HAL status
01491   */
01492 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01493 {
01494   /* Check the TIM handle allocation */
01495   if(htim == NULL)
01496   {
01497     return HAL_ERROR;
01498   }
01499 
01500   /* Check the parameters */
01501   assert_param(IS_TIM_INSTANCE(htim->Instance));
01502   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01503   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01504 
01505   if(htim->State == HAL_TIM_STATE_RESET)
01506   {
01507     /* Allocate lock resource and initialize it */
01508     htim->Lock = HAL_UNLOCKED;
01509     
01510     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01511     HAL_TIM_IC_MspInit(htim);
01512   }
01513 
01514   /* Set the TIM state */
01515   htim->State= HAL_TIM_STATE_BUSY;
01516 
01517   /* Init the base time for the input capture */
01518   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01519 
01520   /* Initialize the TIM state*/
01521   htim->State= HAL_TIM_STATE_READY;
01522 
01523   return HAL_OK;
01524 }
01525 
01526 /**
01527   * @brief  DeInitializes the TIM peripheral 
01528   * @param  htim : TIM Input Capture handle
01529   * @retval HAL status
01530   */
01531 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01532 {
01533   /* Check the parameters */
01534   assert_param(IS_TIM_INSTANCE(htim->Instance));
01535 
01536   htim->State = HAL_TIM_STATE_BUSY;
01537 
01538   /* Disable the TIM Peripheral Clock */
01539   __HAL_TIM_DISABLE(htim);
01540 
01541   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01542   HAL_TIM_IC_MspDeInit(htim);
01543 
01544   /* Change TIM state */
01545   htim->State = HAL_TIM_STATE_RESET;
01546 
01547   /* Release Lock */
01548   __HAL_UNLOCK(htim);
01549 
01550   return HAL_OK;
01551 }
01552 
01553 /**
01554   * @brief  Initializes the TIM Input Capture MSP.
01555   * @param  htim : TIM handle
01556   * @retval None
01557   */
01558 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01559 {
01560   /* Prevent unused argument(s) compilation warning */
01561   UNUSED(htim);
01562   /* NOTE : This function Should not be modified, when the callback is needed,
01563             the HAL_TIM_IC_MspInit could be implemented in the user file
01564    */
01565 }
01566 
01567 /**
01568   * @brief  DeInitializes TIM Input Capture MSP.
01569   * @param  htim : TIM handle
01570   * @retval None
01571   */
01572 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01573 {
01574   /* Prevent unused argument(s) compilation warning */
01575   UNUSED(htim);
01576   /* NOTE : This function Should not be modified, when the callback is needed,
01577             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01578    */
01579 }
01580 
01581 /**
01582   * @brief  Starts the TIM Input Capture measurement.
01583   * @param  htim : TIM Input Capture handle
01584   * @param  Channel : TIM Channels to be enabled
01585   *          This parameter can be one of the following values:
01586   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01587   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01588   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01589   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01590   * @retval HAL status
01591 */
01592 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01593 {
01594   /* Check the parameters */
01595   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01596 
01597   /* Enable the Input Capture channel */
01598   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01599 
01600   /* Enable the Peripheral */
01601   __HAL_TIM_ENABLE(htim);
01602 
01603   /* Return function status */
01604   return HAL_OK;
01605 }
01606 
01607 /**
01608   * @brief  Stops the TIM Input Capture measurement.
01609   * @param  htim : TIM handle
01610   * @param  Channel : TIM Channels to be disabled
01611   *          This parameter can be one of the following values:
01612   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01613   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01614   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01615   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01616   * @retval HAL status
01617 */
01618 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01619 {
01620   /* Check the parameters */
01621   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01622 
01623   /* Disable the Input Capture channel */
01624   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01625 
01626   /* Disable the Peripheral */
01627   __HAL_TIM_DISABLE(htim);
01628 
01629   /* Return function status */
01630   return HAL_OK;
01631 }
01632 
01633 /**
01634   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01635   * @param  htim : TIM Input Capture handle
01636   * @param  Channel : TIM Channels to be enabled
01637   *          This parameter can be one of the following values:
01638   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01639   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01640   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01641   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01642   * @retval HAL status
01643 */
01644 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01645 {
01646   /* Check the parameters */
01647   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01648 
01649   switch (Channel)
01650   {
01651     case TIM_CHANNEL_1:
01652     {
01653       /* Enable the TIM Capture/Compare 1 interrupt */
01654       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01655     }
01656     break;
01657 
01658     case TIM_CHANNEL_2:
01659     {
01660       /* Enable the TIM Capture/Compare 2 interrupt */
01661       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01662     }
01663     break;
01664 
01665     case TIM_CHANNEL_3:
01666     {
01667       /* Enable the TIM Capture/Compare 3 interrupt */
01668       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01669     }
01670     break;
01671 
01672     case TIM_CHANNEL_4:
01673     {
01674       /* Enable the TIM Capture/Compare 4 interrupt */
01675       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01676     }
01677     break;
01678 
01679     default:
01680     break;
01681   }
01682   /* Enable the Input Capture channel */
01683   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01684 
01685   /* Enable the Peripheral */
01686   __HAL_TIM_ENABLE(htim);
01687 
01688   /* Return function status */
01689   return HAL_OK;
01690 }
01691 
01692 /**
01693   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01694   * @param  htim : TIM handle
01695   * @param  Channel : TIM Channels to be disabled
01696   *          This parameter can be one of the following values:
01697   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01698   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01699   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01700   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01701   * @retval HAL status
01702 */
01703 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01704 {
01705   /* Check the parameters */
01706   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01707 
01708   switch (Channel)
01709   {
01710     case TIM_CHANNEL_1:
01711     {
01712       /* Disable the TIM Capture/Compare 1 interrupt */
01713       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01714     }
01715     break;
01716 
01717     case TIM_CHANNEL_2:
01718     {
01719       /* Disable the TIM Capture/Compare 2 interrupt */
01720       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01721     }
01722     break;
01723 
01724     case TIM_CHANNEL_3:
01725     {
01726       /* Disable the TIM Capture/Compare 3 interrupt */
01727       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01728     }
01729     break;
01730 
01731     case TIM_CHANNEL_4:
01732     {
01733       /* Disable the TIM Capture/Compare 4 interrupt */
01734       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01735     }
01736     break;
01737 
01738     default:
01739     break;
01740   }
01741 
01742   /* Disable the Input Capture channel */
01743   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01744 
01745   /* Disable the Peripheral */
01746   __HAL_TIM_DISABLE(htim);
01747 
01748   /* Return function status */
01749   return HAL_OK;
01750 }
01751 
01752 /**
01753   * @brief  Starts the TIM Input Capture measurement in DMA mode.
01754   * @param  htim : TIM Input Capture handle
01755   * @param  Channel : TIM Channels to be enabled
01756   *          This parameter can be one of the following values:
01757   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01758   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01759   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01760   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01761   * @param  pData : The destination Buffer address.
01762   * @param  Length : The length of data to be transferred from TIM peripheral to memory.
01763   * @retval HAL status
01764 */
01765 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01766 {
01767   /* Check the parameters */
01768   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01769   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01770 
01771   if((htim->State == HAL_TIM_STATE_BUSY))
01772   {
01773      return HAL_BUSY;
01774   }
01775   else if((htim->State == HAL_TIM_STATE_READY))
01776   {
01777     if((pData == 0 ) && (Length > 0))
01778     {
01779       return HAL_ERROR;
01780     }
01781     else
01782     {
01783       htim->State = HAL_TIM_STATE_BUSY;
01784     }
01785   }
01786 
01787   switch (Channel)
01788   {
01789     case TIM_CHANNEL_1:
01790     {
01791       /* Set the DMA Period elapsed callback */
01792       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
01793 
01794       /* Set the DMA error callback */
01795       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01796 
01797       /* Enable the DMA channel */
01798       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01799 
01800       /* Enable the TIM Capture/Compare 1 DMA request */
01801       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01802     }
01803     break;
01804 
01805     case TIM_CHANNEL_2:
01806     {
01807       /* Set the DMA Period elapsed callback */
01808       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
01809 
01810       /* Set the DMA error callback */
01811       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01812 
01813       /* Enable the DMA channel */
01814       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01815 
01816       /* Enable the TIM Capture/Compare 2  DMA request */
01817       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01818     }
01819     break;
01820 
01821     case TIM_CHANNEL_3:
01822     {
01823       /* Set the DMA Period elapsed callback */
01824       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
01825 
01826       /* Set the DMA error callback */
01827       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01828 
01829       /* Enable the DMA channel */
01830       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01831 
01832       /* Enable the TIM Capture/Compare 3  DMA request */
01833       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01834     }
01835     break;
01836 
01837     case TIM_CHANNEL_4:
01838     {
01839       /* Set the DMA Period elapsed callback */
01840       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
01841 
01842       /* Set the DMA error callback */
01843       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01844 
01845       /* Enable the DMA channel */
01846       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01847 
01848       /* Enable the TIM Capture/Compare 4  DMA request */
01849       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01850     }
01851     break;
01852 
01853     default:
01854     break;
01855   }
01856 
01857   /* Enable the Input Capture channel */
01858   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01859 
01860   /* Enable the Peripheral */
01861   __HAL_TIM_ENABLE(htim);
01862 
01863   /* Return function status */
01864   return HAL_OK;
01865 }
01866 
01867 /**
01868   * @brief  Stops the TIM Input Capture measurement in DMA mode.
01869   * @param  htim : TIM Input Capture handle
01870   * @param  Channel : TIM Channels to be disabled
01871   *          This parameter can be one of the following values:
01872   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01873   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01874   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01875   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01876   * @retval HAL status
01877 */
01878 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01879 {
01880   /* Check the parameters */
01881   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01882   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01883 
01884   switch (Channel)
01885   {
01886     case TIM_CHANNEL_1:
01887     {
01888       /* Disable the TIM Capture/Compare 1 DMA request */
01889       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01890     }
01891     break;
01892 
01893     case TIM_CHANNEL_2:
01894     {
01895       /* Disable the TIM Capture/Compare 2 DMA request */
01896       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01897     }
01898     break;
01899 
01900     case TIM_CHANNEL_3:
01901     {
01902       /* Disable the TIM Capture/Compare 3  DMA request */
01903       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01904     }
01905     break;
01906 
01907     case TIM_CHANNEL_4:
01908     {
01909       /* Disable the TIM Capture/Compare 4  DMA request */
01910       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01911     }
01912     break;
01913 
01914     default:
01915     break;
01916   }
01917 
01918   /* Disable the Input Capture channel */
01919   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01920 
01921   /* Disable the Peripheral */
01922   __HAL_TIM_DISABLE(htim);
01923 
01924   /* Change the htim state */
01925   htim->State = HAL_TIM_STATE_READY;
01926 
01927   /* Return function status */
01928   return HAL_OK;
01929 }
01930 /**
01931   * @}
01932   */
01933 
01934 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 
01935  *  @brief    Time One Pulse functions 
01936  *
01937 @verbatim 
01938   ==============================================================================
01939                         ##### Time One Pulse functions #####
01940   ==============================================================================
01941   [..]
01942     This section provides functions allowing to:
01943     (+) Initialize and configure the TIM One Pulse.
01944     (+) De-initialize the TIM One Pulse.
01945     (+) Start the Time One Pulse.
01946     (+) Stop the Time One Pulse.
01947     (+) Start the Time One Pulse and enable interrupt.
01948     (+) Stop the Time One Pulse and disable interrupt.
01949     (+) Start the Time One Pulse and enable DMA transfer.
01950     (+) Stop the Time One Pulse and disable DMA transfer.
01951 
01952 @endverbatim
01953   * @{
01954   */
01955 /**
01956   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01957   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01958   * @param  htim : TIM OnePulse handle
01959   * @param  OnePulseMode : Select the One pulse mode.
01960   *         This parameter can be one of the following values:
01961   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01962   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
01963   * @retval HAL status
01964   */
01965 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
01966 {
01967   /* Check the TIM handle allocation */
01968   if(htim == NULL)
01969   {
01970     return HAL_ERROR;
01971   }
01972 
01973   /* Check the parameters */
01974   assert_param(IS_TIM_INSTANCE(htim->Instance));
01975   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01976   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01977   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
01978 
01979   if(htim->State == HAL_TIM_STATE_RESET)
01980   {
01981     /* Allocate lock resource and initialize it */
01982     htim->Lock = HAL_UNLOCKED;
01983     
01984     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01985     HAL_TIM_OnePulse_MspInit(htim);
01986   }
01987 
01988   /* Set the TIM state */
01989   htim->State= HAL_TIM_STATE_BUSY;
01990 
01991   /* Configure the Time base in the One Pulse Mode */
01992   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01993 
01994   /* Reset the OPM Bit */
01995   htim->Instance->CR1 &= ~TIM_CR1_OPM;
01996 
01997   /* Configure the OPM Mode */
01998   htim->Instance->CR1 |= OnePulseMode;
01999 
02000   /* Initialize the TIM state*/
02001   htim->State= HAL_TIM_STATE_READY;
02002 
02003   return HAL_OK;
02004 }
02005 
02006 /**
02007   * @brief  DeInitializes the TIM One Pulse 
02008   * @param  htim : TIM One Pulse handle
02009   * @retval HAL status
02010   */
02011 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02012 {
02013   /* Check the parameters */
02014   assert_param(IS_TIM_INSTANCE(htim->Instance));
02015 
02016   htim->State = HAL_TIM_STATE_BUSY;
02017 
02018   /* Disable the TIM Peripheral Clock */
02019   __HAL_TIM_DISABLE(htim);
02020 
02021   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02022   HAL_TIM_OnePulse_MspDeInit(htim);
02023 
02024   /* Change TIM state */
02025   htim->State = HAL_TIM_STATE_RESET;
02026 
02027   /* Release Lock */
02028   __HAL_UNLOCK(htim);
02029 
02030   return HAL_OK;
02031 }
02032 
02033 /**
02034   * @brief  Initializes the TIM One Pulse MSP.
02035   * @param  htim : TIM handle
02036   * @retval None
02037   */
02038 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02039 {
02040   /* Prevent unused argument(s) compilation warning */
02041   UNUSED(htim);
02042   /* NOTE : This function Should not be modified, when the callback is needed,
02043             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02044    */
02045 }
02046 
02047 /**
02048   * @brief  DeInitializes TIM One Pulse MSP.
02049   * @param  htim : TIM handle
02050   * @retval None
02051   */
02052 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02053 {
02054   /* Prevent unused argument(s) compilation warning */
02055   UNUSED(htim);
02056   /* NOTE : This function Should not be modified, when the callback is needed,
02057             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02058    */
02059 }
02060 
02061 /**
02062   * @brief  Starts the TIM One Pulse signal generation.
02063   * @param  htim : TIM One Pulse handle
02064   * @param  OutputChannel : TIM Channels to be enabled
02065   *          This parameter can be one of the following values:
02066   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02067   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02068   * @retval HAL status
02069 */
02070 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02071 {
02072   /* Enable the Capture compare and the Input Capture channels 
02073     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02074     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02075     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
02076     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
02077 
02078     No need to enable the counter, it's enabled automatically by hardware 
02079     (the counter starts in response to a stimulus and generate a pulse */
02080 
02081   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02082   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02083 
02084   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02085   {
02086     /* Enable the main output */
02087     __HAL_TIM_MOE_ENABLE(htim);
02088   }
02089 
02090   /* Return function status */
02091   return HAL_OK;
02092 }
02093 
02094 /**
02095   * @brief  Stops the TIM One Pulse signal generation.
02096   * @param  htim : TIM One Pulse handle
02097   * @param  OutputChannel : TIM Channels to be disable
02098   *          This parameter can be one of the following values:
02099   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02100   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02101   * @retval HAL status
02102 */
02103 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02104 {
02105   /* Disable the Capture compare and the Input Capture channels
02106   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02107   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02108   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
02109   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02110 
02111   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02112   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02113 
02114   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02115   {
02116     /* Disable the Main Ouput */
02117     __HAL_TIM_MOE_DISABLE(htim);
02118   }
02119 
02120   /* Disable the Peripheral */
02121   __HAL_TIM_DISABLE(htim);
02122 
02123   /* Return function status */
02124   return HAL_OK;
02125 }
02126 
02127 /**
02128   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02129   * @param  htim : TIM One Pulse handle
02130   * @param  OutputChannel : TIM Channels to be enabled
02131   *          This parameter can be one of the following values:
02132   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02133   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02134   * @retval HAL status
02135 */
02136 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02137 {
02138   /* Enable the Capture compare and the Input Capture channels 
02139     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02140     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02141     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
02142     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
02143 
02144     No need to enable the counter, it's enabled automatically by hardware 
02145     (the counter starts in response to a stimulus and generate a pulse */
02146 
02147   /* Enable the TIM Capture/Compare 1 interrupt */
02148   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02149 
02150   /* Enable the TIM Capture/Compare 2 interrupt */
02151   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02152 
02153   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02154   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02155 
02156   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02157   {
02158     /* Enable the main output */
02159     __HAL_TIM_MOE_ENABLE(htim);
02160   }
02161 
02162   /* Return function status */
02163   return HAL_OK;
02164 }
02165 
02166 /**
02167   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02168   * @param  htim : TIM One Pulse handle
02169   * @param  OutputChannel : TIM Channels to be enabled
02170   *          This parameter can be one of the following values:
02171   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02172   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02173   * @retval HAL status
02174 */
02175 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02176 {
02177   /* Disable the TIM Capture/Compare 1 interrupt */
02178   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02179 
02180   /* Disable the TIM Capture/Compare 2 interrupt */
02181   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02182 
02183   /* Disable the Capture compare and the Input Capture channels 
02184   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02185   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02186   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
02187   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02188   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02189   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02190 
02191   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02192   {
02193     /* Disable the Main Ouput */
02194     __HAL_TIM_MOE_DISABLE(htim);
02195   }
02196 
02197   /* Disable the Peripheral */
02198    __HAL_TIM_DISABLE(htim);
02199 
02200   /* Return function status */
02201   return HAL_OK;
02202 }
02203 
02204 /**
02205   * @}
02206   */
02207 
02208 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 
02209  *  @brief    Time Encoder functions 
02210  *
02211 @verbatim 
02212   ==============================================================================
02213                           ##### Time Encoder functions #####
02214   ==============================================================================
02215   [..]
02216     This section provides functions allowing to:
02217     (+) Initialize and configure the TIM Encoder.
02218     (+) De-initialize the TIM Encoder.
02219     (+) Start the Time Encoder.
02220     (+) Stop the Time Encoder.
02221     (+) Start the Time Encoder and enable interrupt.
02222     (+) Stop the Time Encoder and disable interrupt.
02223     (+) Start the Time Encoder and enable DMA transfer.
02224     (+) Stop the Time Encoder and disable DMA transfer.
02225 
02226 @endverbatim
02227   * @{
02228   */
02229 /**
02230   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
02231   * @param  htim : TIM Encoder Interface handle
02232   * @param  sConfig : TIM Encoder Interface configuration structure
02233   * @retval HAL status
02234   */
02235 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02236 {
02237   uint32_t tmpsmcr = 0;
02238   uint32_t tmpccmr1 = 0;
02239   uint32_t tmpccer = 0;
02240 
02241   /* Check the TIM handle allocation */
02242   if(htim == NULL)
02243   {
02244     return HAL_ERROR;
02245   }
02246 
02247   /* Check the parameters */
02248   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02249   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02250   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02251   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02252   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02253   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02254   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02255   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02256   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02257   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02258 
02259   if(htim->State == HAL_TIM_STATE_RESET)
02260   {
02261     /* Allocate lock resource and initialize it */
02262     htim->Lock = HAL_UNLOCKED;
02263     
02264     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02265     HAL_TIM_Encoder_MspInit(htim);
02266   }
02267 
02268   /* Set the TIM state */
02269   htim->State= HAL_TIM_STATE_BUSY;
02270 
02271   /* Reset the SMS bits */
02272   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02273 
02274   /* Configure the Time base in the Encoder Mode */
02275   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02276 
02277   /* Get the TIMx SMCR register value */
02278   tmpsmcr = htim->Instance->SMCR;
02279 
02280   /* Get the TIMx CCMR1 register value */
02281   tmpccmr1 = htim->Instance->CCMR1;
02282 
02283   /* Get the TIMx CCER register value */
02284   tmpccer = htim->Instance->CCER;
02285 
02286   /* Set the encoder Mode */
02287   tmpsmcr |= sConfig->EncoderMode;
02288 
02289   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02290   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02291   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
02292 
02293   /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02294   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02295   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02296   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
02297   tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
02298 
02299   /* Set the TI1 and the TI2 Polarities */
02300   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02301   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02302   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
02303 
02304   /* Write to TIMx SMCR */
02305   htim->Instance->SMCR = tmpsmcr;
02306 
02307   /* Write to TIMx CCMR1 */
02308   htim->Instance->CCMR1 = tmpccmr1;
02309 
02310   /* Write to TIMx CCER */
02311   htim->Instance->CCER = tmpccer;
02312 
02313   /* Initialize the TIM state*/
02314   htim->State= HAL_TIM_STATE_READY;
02315 
02316   return HAL_OK;
02317 }
02318 
02319 
02320 /**
02321   * @brief  DeInitializes the TIM Encoder interface 
02322   * @param  htim : TIM Encoder handle
02323   * @retval HAL status
02324   */
02325 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02326 {
02327   /* Check the parameters */
02328   assert_param(IS_TIM_INSTANCE(htim->Instance));
02329 
02330   htim->State = HAL_TIM_STATE_BUSY;
02331 
02332   /* Disable the TIM Peripheral Clock */
02333   __HAL_TIM_DISABLE(htim);
02334 
02335   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02336   HAL_TIM_Encoder_MspDeInit(htim);
02337 
02338   /* Change TIM state */
02339   htim->State = HAL_TIM_STATE_RESET;
02340 
02341   /* Release Lock */
02342   __HAL_UNLOCK(htim);
02343 
02344   return HAL_OK;
02345 }
02346 
02347 /**
02348   * @brief  Initializes the TIM Encoder Interface MSP.
02349   * @param  htim : TIM handle
02350   * @retval None
02351   */
02352 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02353 {
02354   /* Prevent unused argument(s) compilation warning */
02355   UNUSED(htim);
02356   /* NOTE : This function Should not be modified, when the callback is needed,
02357             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02358    */
02359 }
02360 
02361 /**
02362   * @brief  DeInitializes TIM Encoder Interface MSP.
02363   * @param  htim : TIM handle
02364   * @retval None
02365   */
02366 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02367 {
02368   /* Prevent unused argument(s) compilation warning */
02369   UNUSED(htim);
02370   /* NOTE : This function Should not be modified, when the callback is needed,
02371             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02372    */
02373 }
02374 
02375 /**
02376   * @brief  Starts the TIM Encoder Interface.
02377   * @param  htim : TIM Encoder Interface handle
02378   * @param  Channel : TIM Channels to be enabled
02379   *          This parameter can be one of the following values:
02380   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02381   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02382   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02383   * @retval HAL status
02384 */
02385 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02386 {
02387   /* Check the parameters */
02388   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02389 
02390   /* Enable the encoder interface channels */
02391   switch (Channel)
02392   {
02393     case TIM_CHANNEL_1:
02394   {
02395     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02396       break;
02397   }
02398     case TIM_CHANNEL_2:
02399   {
02400     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02401       break;
02402   }
02403     default :
02404   {
02405      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02406      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02407      break;
02408     }
02409   }
02410   /* Enable the Peripheral */
02411   __HAL_TIM_ENABLE(htim);
02412 
02413   /* Return function status */
02414   return HAL_OK;
02415 }
02416 
02417 /**
02418   * @brief  Stops the TIM Encoder Interface.
02419   * @param  htim : TIM Encoder Interface handle
02420   * @param  Channel : TIM Channels to be disabled
02421   *          This parameter can be one of the following values:
02422   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02423   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02424   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02425   * @retval HAL status
02426 */
02427 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02428 {
02429   /* Check the parameters */
02430     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02431 
02432    /* Disable the Input Capture channels 1 and 2
02433     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02434   switch (Channel)
02435   {
02436     case TIM_CHANNEL_1:
02437   {
02438      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02439       break;
02440   }
02441     case TIM_CHANNEL_2:
02442   {
02443     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02444       break;
02445   }
02446     default :
02447   {
02448     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02449     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02450      break;
02451     }
02452   }
02453 
02454   /* Disable the Peripheral */
02455   __HAL_TIM_DISABLE(htim);
02456 
02457   /* Return function status */
02458   return HAL_OK;
02459 }
02460 
02461 /**
02462   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02463   * @param  htim : TIM Encoder Interface handle
02464   * @param  Channel : TIM Channels to be enabled
02465   *          This parameter can be one of the following values:
02466   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02467   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02468   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02469   * @retval HAL status
02470 */
02471 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02472 {
02473   /* Check the parameters */
02474   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02475 
02476   /* Enable the encoder interface channels */
02477   /* Enable the capture compare Interrupts 1 and/or 2 */
02478   switch (Channel)
02479   {
02480     case TIM_CHANNEL_1:
02481   {
02482     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02483     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02484       break;
02485   }
02486     case TIM_CHANNEL_2:
02487   {
02488     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02489     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02490       break;
02491   }
02492     default :
02493   {
02494      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02495      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02496      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02497      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02498      break;
02499     }
02500   }
02501 
02502   /* Enable the Peripheral */
02503   __HAL_TIM_ENABLE(htim);
02504 
02505   /* Return function status */
02506   return HAL_OK;
02507 }
02508 
02509 /**
02510   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02511   * @param  htim : TIM Encoder Interface handle
02512   * @param  Channel : TIM Channels to be disabled
02513   *          This parameter can be one of the following values:
02514   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02515   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02516   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02517   * @retval HAL status
02518 */
02519 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02520 {
02521   /* Check the parameters */
02522   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02523 
02524   /* Disable the Input Capture channels 1 and 2
02525     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02526   if(Channel == TIM_CHANNEL_1)
02527   {
02528     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02529 
02530     /* Disable the capture compare Interrupts 1 */
02531   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02532   }
02533   else if(Channel == TIM_CHANNEL_2)
02534   {
02535     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02536 
02537     /* Disable the capture compare Interrupts 2 */
02538   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02539   }
02540   else
02541   {
02542     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02543     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02544 
02545     /* Disable the capture compare Interrupts 1 and 2 */
02546     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02547     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02548   }
02549 
02550   /* Disable the Peripheral */
02551   __HAL_TIM_DISABLE(htim);
02552 
02553   /* Change the htim state */
02554   htim->State = HAL_TIM_STATE_READY;
02555 
02556   /* Return function status */
02557   return HAL_OK;
02558 }
02559 
02560 /**
02561   * @brief  Starts the TIM Encoder Interface in DMA mode.
02562   * @param  htim : TIM Encoder Interface handle
02563   * @param  Channel : TIM Channels to be enabled
02564   *          This parameter can be one of the following values:
02565   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02566   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02567   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02568   * @param  pData1 : The destination Buffer address for IC1.
02569   * @param  pData2 : The destination Buffer address for IC2.
02570   * @param  Length : The length of data to be transferred from TIM peripheral to memory.
02571   * @retval HAL status
02572 */
02573 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02574 {
02575   /* Check the parameters */
02576   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02577 
02578   if((htim->State == HAL_TIM_STATE_BUSY))
02579   {
02580      return HAL_BUSY;
02581   }
02582   else if((htim->State == HAL_TIM_STATE_READY))
02583   {
02584     if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
02585     {
02586       return HAL_ERROR;
02587     }
02588     else
02589     {
02590       htim->State = HAL_TIM_STATE_BUSY;
02591     }
02592   }
02593 
02594   switch (Channel)
02595   {
02596     case TIM_CHANNEL_1:
02597     {
02598       /* Set the DMA Period elapsed callback */
02599       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02600 
02601       /* Set the DMA error callback */
02602       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02603 
02604       /* Enable the DMA channel */
02605       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02606 
02607       /* Enable the TIM Input Capture DMA request */
02608       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02609 
02610       /* Enable the Peripheral */
02611       __HAL_TIM_ENABLE(htim);
02612 
02613       /* Enable the Capture compare channel */
02614       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02615     }
02616     break;
02617 
02618     case TIM_CHANNEL_2:
02619     {
02620       /* Set the DMA Period elapsed callback */
02621       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02622 
02623       /* Set the DMA error callback */
02624       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
02625       /* Enable the DMA channel */
02626       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02627 
02628       /* Enable the TIM Input Capture  DMA request */
02629       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02630 
02631       /* Enable the Peripheral */
02632       __HAL_TIM_ENABLE(htim);
02633 
02634       /* Enable the Capture compare channel */
02635       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02636     }
02637     break;
02638 
02639     case TIM_CHANNEL_ALL:
02640     {
02641       /* Set the DMA Period elapsed callback */
02642       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02643 
02644       /* Set the DMA error callback */
02645       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02646 
02647       /* Enable the DMA channel */
02648       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02649 
02650       /* Set the DMA Period elapsed callback */
02651       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02652 
02653       /* Set the DMA error callback */
02654       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02655 
02656       /* Enable the DMA channel */
02657       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02658 
02659      /* Enable the Peripheral */
02660       __HAL_TIM_ENABLE(htim);
02661 
02662       /* Enable the Capture compare channel */
02663       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02664       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02665 
02666       /* Enable the TIM Input Capture  DMA request */
02667       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02668       /* Enable the TIM Input Capture  DMA request */
02669       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02670     }
02671     break;
02672 
02673     default:
02674     break;
02675   }
02676   /* Return function status */
02677   return HAL_OK;
02678 }
02679 
02680 /**
02681   * @brief  Stops the TIM Encoder Interface in DMA mode.
02682   * @param  htim : TIM Encoder Interface handle
02683   * @param  Channel : TIM Channels to be enabled
02684   *          This parameter can be one of the following values:
02685   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02686   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02687   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02688   * @retval HAL status
02689 */
02690 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02691 {
02692   /* Check the parameters */
02693   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02694 
02695   /* Disable the Input Capture channels 1 and 2
02696     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02697   if(Channel == TIM_CHANNEL_1)
02698   {
02699     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02700 
02701     /* Disable the capture compare DMA Request 1 */
02702     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02703   }
02704   else if(Channel == TIM_CHANNEL_2)
02705   {
02706     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02707 
02708     /* Disable the capture compare DMA Request 2 */
02709     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02710   }
02711   else
02712   {
02713     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02714     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02715 
02716     /* Disable the capture compare DMA Request 1 and 2 */
02717     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02718     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02719   }
02720 
02721   /* Disable the Peripheral */
02722   __HAL_TIM_DISABLE(htim);
02723 
02724   /* Change the htim state */
02725   htim->State = HAL_TIM_STATE_READY;
02726 
02727   /* Return function status */
02728   return HAL_OK;
02729 }
02730 
02731 /**
02732   * @}
02733   */
02734 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 
02735  *  @brief    IRQ handler management 
02736  *
02737 @verbatim 
02738   ==============================================================================
02739                         ##### IRQ handler management #####
02740   ==============================================================================
02741   [..]
02742     This section provides Timer IRQ handler function.
02743 
02744 @endverbatim
02745   * @{
02746   */
02747 /**
02748   * @brief  This function handles TIM interrupts requests.
02749   * @param  htim : TIM  handle
02750   * @retval None
02751   */
02752 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02753 {
02754   /* Capture compare 1 event */
02755   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02756   {
02757     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02758     {
02759       {
02760         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02761         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02762 
02763         /* Input capture event */
02764         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
02765         {
02766           HAL_TIM_IC_CaptureCallback(htim);
02767         }
02768         /* Output compare event */
02769         else
02770         {
02771           HAL_TIM_OC_DelayElapsedCallback(htim);
02772           HAL_TIM_PWM_PulseFinishedCallback(htim);
02773         }
02774         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02775       }
02776     }
02777   }
02778   /* Capture compare 2 event */
02779   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02780   {
02781     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02782     {
02783       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02784       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02785       /* Input capture event */
02786       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
02787       {
02788         HAL_TIM_IC_CaptureCallback(htim);
02789       }
02790       /* Output compare event */
02791       else
02792       {
02793         HAL_TIM_OC_DelayElapsedCallback(htim);
02794         HAL_TIM_PWM_PulseFinishedCallback(htim);
02795       }
02796       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02797     }
02798   }
02799   /* Capture compare 3 event */
02800   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02801   {
02802     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02803     {
02804       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02805       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02806       /* Input capture event */
02807       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
02808       {
02809         HAL_TIM_IC_CaptureCallback(htim);
02810       }
02811       /* Output compare event */
02812       else
02813       {
02814         HAL_TIM_OC_DelayElapsedCallback(htim);
02815         HAL_TIM_PWM_PulseFinishedCallback(htim);
02816       }
02817       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02818     }
02819   }
02820   /* Capture compare 4 event */
02821   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02822   {
02823     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02824     {
02825       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02826       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02827       /* Input capture event */
02828       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
02829       {
02830         HAL_TIM_IC_CaptureCallback(htim);
02831       }
02832       /* Output compare event */
02833       else
02834       {
02835         HAL_TIM_OC_DelayElapsedCallback(htim);
02836         HAL_TIM_PWM_PulseFinishedCallback(htim);
02837       }
02838       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02839     }
02840   }
02841   /* TIM Update event */
02842   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02843   {
02844     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02845     {
02846       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02847       HAL_TIM_PeriodElapsedCallback(htim);
02848     }
02849   }
02850   /* TIM Break input event */
02851   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02852   {
02853     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02854     {
02855       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02856       HAL_TIMEx_BreakCallback(htim);
02857     }
02858   }
02859   /* TIM Trigger detection event */
02860   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02861   {
02862     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02863     {
02864       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02865       HAL_TIM_TriggerCallback(htim);
02866     }
02867   }
02868   /* TIM commutation event */
02869   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02870   {
02871     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02872     {
02873       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02874       HAL_TIMEx_CommutationCallback(htim);
02875     }
02876   }
02877 }
02878 
02879 /**
02880   * @}
02881   */
02882 
02883 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02884  *  @brief      Peripheral Control functions 
02885  *
02886 @verbatim 
02887   ==============================================================================
02888                    ##### Peripheral Control functions #####
02889   ==============================================================================
02890  [..]
02891    This section provides functions allowing to:
02892       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02893       (+) Configure External Clock source.
02894       (+) Configure Complementary channels, break features and dead time.
02895       (+) Configure Master and the Slave synchronization.
02896       (+) Configure the DMA Burst Mode.
02897 
02898 @endverbatim
02899   * @{
02900   */
02901 
02902 /**
02903   * @brief  Initializes the TIM Output Compare Channels according to the specified
02904   *         parameters in the TIM_OC_InitTypeDef.
02905   * @param  htim : TIM Output Compare handle
02906   * @param  sConfig : TIM Output Compare configuration structure
02907   * @param  Channel : TIM Channels to be enabled
02908   *          This parameter can be one of the following values:
02909   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02910   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02911   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02912   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
02913   * @retval HAL status
02914   */
02915 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
02916 {
02917   /* Check the parameters */
02918   assert_param(IS_TIM_CHANNELS(Channel));
02919   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02920   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02921 
02922   /* Check input state */
02923   __HAL_LOCK(htim);
02924 
02925   htim->State = HAL_TIM_STATE_BUSY;
02926 
02927   switch (Channel)
02928   {
02929     case TIM_CHANNEL_1:
02930     {
02931       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02932       /* Configure the TIM Channel 1 in Output Compare */
02933       TIM_OC1_SetConfig(htim->Instance, sConfig);
02934     }
02935     break;
02936 
02937     case TIM_CHANNEL_2:
02938     {
02939       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02940       /* Configure the TIM Channel 2 in Output Compare */
02941       TIM_OC2_SetConfig(htim->Instance, sConfig);
02942     }
02943     break;
02944 
02945     case TIM_CHANNEL_3:
02946     {
02947        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
02948       /* Configure the TIM Channel 3 in Output Compare */
02949       TIM_OC3_SetConfig(htim->Instance, sConfig);
02950     }
02951     break;
02952 
02953     case TIM_CHANNEL_4:
02954     {
02955       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
02956        /* Configure the TIM Channel 4 in Output Compare */
02957        TIM_OC4_SetConfig(htim->Instance, sConfig);
02958     }
02959     break;
02960 
02961     default:
02962     break;
02963   }
02964   htim->State = HAL_TIM_STATE_READY;
02965 
02966   __HAL_UNLOCK(htim);
02967 
02968   return HAL_OK;
02969 }
02970 
02971 /**
02972   * @brief  Initializes the TIM Input Capture Channels according to the specified
02973   *         parameters in the TIM_IC_InitTypeDef.
02974   * @param  htim : TIM IC handle
02975   * @param  sConfig : TIM Input Capture configuration structure
02976   * @param  Channel : TIM Channels to be enabled
02977   *          This parameter can be one of the following values:
02978   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02979   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02980   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02981   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
02982   * @retval HAL status
02983   */
02984 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
02985 {
02986   /* Check the parameters */
02987   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02988   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
02989   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
02990   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
02991   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
02992 
02993   __HAL_LOCK(htim);
02994 
02995   htim->State = HAL_TIM_STATE_BUSY;
02996 
02997   if (Channel == TIM_CHANNEL_1)
02998   {
02999     /* TI1 Configuration */
03000     TIM_TI1_SetConfig(htim->Instance,
03001                sConfig->ICPolarity,
03002                sConfig->ICSelection,
03003                sConfig->ICFilter);
03004 
03005     /* Reset the IC1PSC Bits */
03006     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03007 
03008     /* Set the IC1PSC value */
03009     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03010   }
03011   else if (Channel == TIM_CHANNEL_2)
03012   {
03013     /* TI2 Configuration */
03014     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03015 
03016     TIM_TI2_SetConfig(htim->Instance,
03017                       sConfig->ICPolarity,
03018                       sConfig->ICSelection,
03019                       sConfig->ICFilter);
03020 
03021     /* Reset the IC2PSC Bits */
03022     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03023 
03024     /* Set the IC2PSC value */
03025     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
03026   }
03027   else if (Channel == TIM_CHANNEL_3)
03028   {
03029     /* TI3 Configuration */
03030     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03031 
03032     TIM_TI3_SetConfig(htim->Instance,
03033                sConfig->ICPolarity,
03034                sConfig->ICSelection,
03035                sConfig->ICFilter);
03036 
03037     /* Reset the IC3PSC Bits */
03038     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03039 
03040     /* Set the IC3PSC value */
03041     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03042   }
03043   else
03044   {
03045     /* TI4 Configuration */
03046     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03047 
03048     TIM_TI4_SetConfig(htim->Instance,
03049                sConfig->ICPolarity,
03050                sConfig->ICSelection,
03051                sConfig->ICFilter);
03052 
03053     /* Reset the IC4PSC Bits */
03054     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03055 
03056     /* Set the IC4PSC value */
03057     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
03058   }
03059 
03060   htim->State = HAL_TIM_STATE_READY;
03061 
03062   __HAL_UNLOCK(htim);
03063 
03064   return HAL_OK;
03065 }
03066 
03067 /**
03068   * @brief  Initializes the TIM PWM  channels according to the specified
03069   *         parameters in the TIM_OC_InitTypeDef.
03070   * @param  htim : TIM handle
03071   * @param  sConfig : TIM PWM configuration structure
03072   * @param  Channel : TIM Channels to be enabled
03073   *          This parameter can be one of the following values:
03074   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03075   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03076   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03077   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03078   * @retval HAL status
03079   */
03080 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
03081 {
03082   __HAL_LOCK(htim);
03083 
03084   /* Check the parameters */
03085   assert_param(IS_TIM_CHANNELS(Channel));
03086   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03087   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03088   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03089 
03090   htim->State = HAL_TIM_STATE_BUSY;
03091 
03092   switch (Channel)
03093   {
03094     case TIM_CHANNEL_1:
03095     {
03096       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03097       /* Configure the Channel 1 in PWM mode */
03098       TIM_OC1_SetConfig(htim->Instance, sConfig);
03099 
03100       /* Set the Preload enable bit for channel1 */
03101       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03102 
03103       /* Configure the Output Fast mode */
03104       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03105       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03106     }
03107     break;
03108 
03109     case TIM_CHANNEL_2:
03110     {
03111       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03112       /* Configure the Channel 2 in PWM mode */
03113       TIM_OC2_SetConfig(htim->Instance, sConfig);
03114 
03115       /* Set the Preload enable bit for channel2 */
03116       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03117 
03118       /* Configure the Output Fast mode */
03119       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03120       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
03121     }
03122     break;
03123 
03124     case TIM_CHANNEL_3:
03125     {
03126       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03127       /* Configure the Channel 3 in PWM mode */
03128       TIM_OC3_SetConfig(htim->Instance, sConfig);
03129 
03130       /* Set the Preload enable bit for channel3 */
03131       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03132 
03133      /* Configure the Output Fast mode */
03134       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03135       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03136     }
03137     break;
03138 
03139     case TIM_CHANNEL_4:
03140     {
03141       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03142       /* Configure the Channel 4 in PWM mode */
03143       TIM_OC4_SetConfig(htim->Instance, sConfig);
03144 
03145       /* Set the Preload enable bit for channel4 */
03146       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03147 
03148      /* Configure the Output Fast mode */
03149       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03150       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
03151     }
03152     break;
03153 
03154     default:
03155     break;
03156   }
03157 
03158   htim->State = HAL_TIM_STATE_READY;
03159 
03160   __HAL_UNLOCK(htim);
03161 
03162   return HAL_OK;
03163 }
03164 
03165 /**
03166   * @brief  Initializes the TIM One Pulse Channels according to the specified
03167   *         parameters in the TIM_OnePulse_InitTypeDef.
03168   * @param  htim : TIM One Pulse handle
03169   * @param  sConfig : TIM One Pulse configuration structure
03170   * @param  OutputChannel : TIM Channels to be enabled
03171   *          This parameter can be one of the following values:
03172   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03173   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03174   * @param  InputChannel : TIM Channels to be enabled
03175   *          This parameter can be one of the following values:
03176   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03177   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03178   * @retval HAL status
03179   */
03180 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03181 {
03182   TIM_OC_InitTypeDef temp1;
03183 
03184   /* Check the parameters */
03185   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03186   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03187 
03188   if(OutputChannel != InputChannel)
03189   {
03190   __HAL_LOCK(htim);
03191 
03192   htim->State = HAL_TIM_STATE_BUSY;
03193 
03194   /* Extract the Ouput compare configuration from sConfig structure */
03195   temp1.OCMode = sConfig->OCMode;
03196   temp1.Pulse = sConfig->Pulse;
03197   temp1.OCPolarity = sConfig->OCPolarity;
03198   temp1.OCNPolarity = sConfig->OCNPolarity;
03199   temp1.OCIdleState = sConfig->OCIdleState;
03200   temp1.OCNIdleState = sConfig->OCNIdleState;
03201 
03202     switch (OutputChannel)
03203   {
03204     case TIM_CHANNEL_1:
03205     {
03206         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03207 
03208       TIM_OC1_SetConfig(htim->Instance, &temp1);
03209     }
03210     break;
03211     case TIM_CHANNEL_2:
03212     {
03213         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03214 
03215       TIM_OC2_SetConfig(htim->Instance, &temp1);
03216     }
03217     break;
03218     default:
03219     break;
03220   }
03221   switch (InputChannel)
03222   {
03223     case TIM_CHANNEL_1:
03224     {
03225       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03226 
03227       TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03228                         sConfig->ICSelection, sConfig->ICFilter);
03229 
03230       /* Reset the IC1PSC Bits */
03231     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03232 
03233       /* Select the Trigger source */
03234         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03235       htim->Instance->SMCR |= TIM_TS_TI1FP1;
03236 
03237       /* Select the Slave Mode */
03238         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03239       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03240     }
03241     break;
03242     case TIM_CHANNEL_2:
03243     {
03244       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03245 
03246       TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03247                  sConfig->ICSelection, sConfig->ICFilter);
03248 
03249       /* Reset the IC2PSC Bits */
03250         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03251 
03252       /* Select the Trigger source */
03253         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03254       htim->Instance->SMCR |= TIM_TS_TI2FP2;
03255 
03256       /* Select the Slave Mode */
03257         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03258       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03259     }
03260     break;
03261 
03262     default:
03263     break;
03264   }
03265 
03266   htim->State = HAL_TIM_STATE_READY;
03267 
03268   __HAL_UNLOCK(htim);
03269 
03270   return HAL_OK;
03271 }
03272   else
03273   {
03274     return HAL_ERROR;
03275   }
03276 }
03277 
03278 /**
03279   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 
03280   * @param  htim : TIM handle
03281   * @param  BurstBaseAddress : TIM Base address from where the DMA will start the Data write
03282   *         This parameter can be one of the following values:
03283   *            @arg TIM_DMABASE_CR1 
03284   *            @arg TIM_DMABASE_CR2
03285   *            @arg TIM_DMABASE_SMCR
03286   *            @arg TIM_DMABASE_DIER
03287   *            @arg TIM_DMABASE_SR
03288   *            @arg TIM_DMABASE_EGR
03289   *            @arg TIM_DMABASE_CCMR1
03290   *            @arg TIM_DMABASE_CCMR2
03291   *            @arg TIM_DMABASE_CCER
03292   *            @arg TIM_DMABASE_CNT 
03293   *            @arg TIM_DMABASE_PSC 
03294   *            @arg TIM_DMABASE_ARR
03295   *            @arg TIM_DMABASE_RCR
03296   *            @arg TIM_DMABASE_CCR1
03297   *            @arg TIM_DMABASE_CCR2
03298   *            @arg TIM_DMABASE_CCR3 
03299   *            @arg TIM_DMABASE_CCR4
03300   *            @arg TIM_DMABASE_BDTR
03301   *            @arg TIM_DMABASE_DCR
03302   * @param  BurstRequestSrc : TIM DMA Request sources
03303   *         This parameter can be one of the following values:
03304   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03305   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03306   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03307   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03308   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03309   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03310   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03311   * @param  BurstBuffer : The Buffer address.
03312   * @param  BurstLength : DMA Burst length. This parameter can be one value
03313   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03314   * @retval HAL status
03315   */
03316 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03317                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03318 {
03319   /* Check the parameters */
03320   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03321   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03322   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03323   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03324 
03325   if((htim->State == HAL_TIM_STATE_BUSY))
03326   {
03327      return HAL_BUSY;
03328   }
03329   else if((htim->State == HAL_TIM_STATE_READY))
03330   {
03331     if((BurstBuffer == 0 ) && (BurstLength > 0))
03332     {
03333       return HAL_ERROR;
03334     }
03335     else
03336     {
03337       htim->State = HAL_TIM_STATE_BUSY;
03338     }
03339   }
03340   switch(BurstRequestSrc)
03341   {
03342     case TIM_DMA_UPDATE:
03343     {
03344       /* Set the DMA Period elapsed callback */
03345       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03346 
03347       /* Set the DMA error callback */
03348       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03349 
03350       /* Enable the DMA channel */
03351       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03352     }
03353     break;
03354     case TIM_DMA_CC1:
03355     {
03356       /* Set the DMA Period elapsed callback */
03357       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03358 
03359       /* Set the DMA error callback */
03360       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03361 
03362       /* Enable the DMA channel */
03363       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03364     }
03365     break;
03366     case TIM_DMA_CC2:
03367     {
03368       /* Set the DMA Period elapsed callback */
03369       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03370 
03371       /* Set the DMA error callback */
03372       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03373 
03374       /* Enable the DMA channel */
03375       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03376     }
03377     break;
03378     case TIM_DMA_CC3:
03379     {
03380       /* Set the DMA Period elapsed callback */
03381       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03382 
03383       /* Set the DMA error callback */
03384       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03385 
03386       /* Enable the DMA channel */
03387       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03388     }
03389     break;
03390     case TIM_DMA_CC4:
03391     {
03392       /* Set the DMA Period elapsed callback */
03393       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03394 
03395       /* Set the DMA error callback */
03396       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03397 
03398       /* Enable the DMA channel */
03399       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03400     }
03401     break;
03402     case TIM_DMA_COM:
03403     {
03404       /* Set the DMA Period elapsed callback */
03405       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03406 
03407       /* Set the DMA error callback */
03408       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03409 
03410       /* Enable the DMA channel */
03411       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03412     }
03413     break;
03414     case TIM_DMA_TRIGGER:
03415     {
03416       /* Set the DMA Period elapsed callback */
03417       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03418 
03419       /* Set the DMA error callback */
03420       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03421 
03422       /* Enable the DMA channel */
03423       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03424     }
03425     break;
03426     default:
03427     break;
03428   }
03429    /* configure the DMA Burst Mode */
03430    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03431 
03432    /* Enable the TIM DMA Request */
03433    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03434 
03435    htim->State = HAL_TIM_STATE_READY;
03436 
03437   /* Return function status */
03438   return HAL_OK;
03439 }
03440 
03441 /**
03442   * @brief  Stops the TIM DMA Burst mode 
03443   * @param  htim : TIM handle
03444   * @param  BurstRequestSrc : TIM DMA Request sources to disable
03445   * @retval HAL status
03446   */
03447 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03448 {
03449   /* Check the parameters */
03450   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03451 
03452   /* Abort the DMA transfer (at least disable the DMA channel) */
03453   switch(BurstRequestSrc)
03454   {
03455     case TIM_DMA_UPDATE:
03456     {
03457       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03458     }
03459     break;
03460     case TIM_DMA_CC1:
03461     {
03462       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03463     }
03464     break;
03465     case TIM_DMA_CC2:
03466     {
03467       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03468     }
03469     break;
03470     case TIM_DMA_CC3:
03471     {
03472       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03473     }
03474     break;
03475     case TIM_DMA_CC4:
03476     {
03477       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03478     }
03479     break;
03480     case TIM_DMA_COM:
03481     {
03482       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03483     }
03484     break;
03485     case TIM_DMA_TRIGGER:
03486     {
03487       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03488     }
03489     break;
03490     default:
03491     break;
03492   }
03493 
03494   /* Disable the TIM Update DMA request */
03495   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03496 
03497   /* Return function status */
03498   return HAL_OK;
03499 }
03500 
03501 /**
03502   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 
03503   * @param  htim : TIM handle
03504   * @param  BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
03505   *         This parameter can be one of the following values:
03506   *            @arg TIM_DMABASE_CR1 
03507   *            @arg TIM_DMABASE_CR2
03508   *            @arg TIM_DMABASE_SMCR
03509   *            @arg TIM_DMABASE_DIER
03510   *            @arg TIM_DMABASE_SR
03511   *            @arg TIM_DMABASE_EGR
03512   *            @arg TIM_DMABASE_CCMR1
03513   *            @arg TIM_DMABASE_CCMR2
03514   *            @arg TIM_DMABASE_CCER
03515   *            @arg TIM_DMABASE_CNT 
03516   *            @arg TIM_DMABASE_PSC 
03517   *            @arg TIM_DMABASE_ARR
03518   *            @arg TIM_DMABASE_RCR
03519   *            @arg TIM_DMABASE_CCR1
03520   *            @arg TIM_DMABASE_CCR2
03521   *            @arg TIM_DMABASE_CCR3 
03522   *            @arg TIM_DMABASE_CCR4
03523   *            @arg TIM_DMABASE_BDTR
03524   *            @arg TIM_DMABASE_DCR
03525   * @param  BurstRequestSrc : TIM DMA Request sources
03526   *         This parameter can be one of the following values:
03527   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03528   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03529   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03530   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03531   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03532   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03533   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03534   * @param  BurstBuffer : The Buffer address.
03535   * @param  BurstLength : DMA Burst length. This parameter can be one value
03536   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03537   * @retval HAL status
03538   */
03539 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03540                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03541 {
03542   /* Check the parameters */
03543   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03544   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03545   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03546   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03547 
03548   if((htim->State == HAL_TIM_STATE_BUSY))
03549   {
03550      return HAL_BUSY;
03551   }
03552   else if((htim->State == HAL_TIM_STATE_READY))
03553   {
03554     if((BurstBuffer == 0 ) && (BurstLength > 0))
03555     {
03556       return HAL_ERROR;
03557     }
03558     else
03559     {
03560       htim->State = HAL_TIM_STATE_BUSY;
03561     }
03562   }
03563   switch(BurstRequestSrc)
03564   {
03565     case TIM_DMA_UPDATE:
03566     {
03567       /* Set the DMA Period elapsed callback */
03568       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03569 
03570       /* Set the DMA error callback */
03571       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03572 
03573       /* Enable the DMA channel */
03574        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03575     }
03576     break;
03577     case TIM_DMA_CC1:
03578     {
03579       /* Set the DMA Period elapsed callback */
03580       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
03581 
03582       /* Set the DMA error callback */
03583       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03584 
03585       /* Enable the DMA channel */
03586       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03587     }
03588     break;
03589     case TIM_DMA_CC2:
03590     {
03591       /* Set the DMA Period elapsed callback */
03592       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
03593 
03594       /* Set the DMA error callback */
03595       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03596 
03597       /* Enable the DMA channel */
03598       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03599     }
03600     break;
03601     case TIM_DMA_CC3:
03602     {
03603       /* Set the DMA Period elapsed callback */
03604       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
03605 
03606       /* Set the DMA error callback */
03607       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03608 
03609       /* Enable the DMA channel */
03610       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03611     }
03612     break;
03613     case TIM_DMA_CC4:
03614     {
03615       /* Set the DMA Period elapsed callback */
03616       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
03617 
03618       /* Set the DMA error callback */
03619       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03620 
03621       /* Enable the DMA channel */
03622       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03623     }
03624     break;
03625     case TIM_DMA_COM:
03626     {
03627       /* Set the DMA Period elapsed callback */
03628       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03629 
03630       /* Set the DMA error callback */
03631       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03632 
03633       /* Enable the DMA channel */
03634       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03635     }
03636     break;
03637     case TIM_DMA_TRIGGER:
03638     {
03639       /* Set the DMA Period elapsed callback */
03640       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03641 
03642       /* Set the DMA error callback */
03643       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03644 
03645       /* Enable the DMA channel */
03646       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03647     }
03648     break;
03649     default:
03650     break;
03651   }
03652 
03653   /* configure the DMA Burst Mode */
03654   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03655 
03656   /* Enable the TIM DMA Request */
03657   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03658 
03659   htim->State = HAL_TIM_STATE_READY;
03660 
03661   /* Return function status */
03662   return HAL_OK;
03663 }
03664 
03665 /**
03666   * @brief  Stop the DMA burst reading 
03667   * @param  htim : TIM handle
03668   * @param  BurstRequestSrc : TIM DMA Request sources to disable.
03669   * @retval HAL status
03670   */
03671 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03672 {
03673   /* Check the parameters */
03674   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03675 
03676   /* Abort the DMA transfer (at least disable the DMA channel) */
03677   switch(BurstRequestSrc)
03678   {
03679     case TIM_DMA_UPDATE:
03680     {
03681       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03682     }
03683     break;
03684     case TIM_DMA_CC1:
03685     {
03686       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03687     }
03688     break;
03689     case TIM_DMA_CC2:
03690     {
03691       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03692     }
03693     break;
03694     case TIM_DMA_CC3:
03695     {
03696       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03697     }
03698     break;
03699     case TIM_DMA_CC4:
03700     {
03701       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03702     }
03703     break;
03704     case TIM_DMA_COM:
03705     {
03706       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03707     }
03708     break;
03709     case TIM_DMA_TRIGGER:
03710     {
03711       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03712     }
03713     break;
03714     default:
03715     break;
03716   }
03717 
03718   /* Disable the TIM Update DMA request */
03719   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03720 
03721   /* Return function status */
03722   return HAL_OK;
03723 }
03724 
03725 /**
03726   * @brief  Generate a software event
03727   * @param  htim : TIM handle
03728   * @param  EventSource : specifies the event source.
03729   *          This parameter can be one of the following values:
03730   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03731   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03732   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03733   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03734   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03735   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source 
03736   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03737   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03738   * @note TIM6 and TIM7 can only generate an update event.
03739   * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
03740   * @retval HAL status
03741   */
03742 
03743 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03744 {
03745   /* Check the parameters */
03746   assert_param(IS_TIM_INSTANCE(htim->Instance));
03747   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03748 
03749   /* Process Locked */
03750   __HAL_LOCK(htim);
03751 
03752   /* Change the TIM state */
03753   htim->State = HAL_TIM_STATE_BUSY;
03754 
03755   /* Set the event sources */
03756   htim->Instance->EGR = EventSource;
03757 
03758   /* Change the TIM state */
03759   htim->State = HAL_TIM_STATE_READY;
03760 
03761   __HAL_UNLOCK(htim);
03762 
03763   /* Return function status */
03764   return HAL_OK;
03765 }
03766 
03767 /**
03768   * @brief  Configures the OCRef clear feature
03769   * @param  htim : TIM handle
03770   * @param  sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
03771   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03772   * @param  Channel : specifies the TIM Channel
03773   *          This parameter can be one of the following values:
03774   *            @arg TIM_CHANNEL_1: TIM Channel 1
03775   *            @arg TIM_CHANNEL_2: TIM Channel 2
03776   *            @arg TIM_CHANNEL_3: TIM Channel 3
03777   *            @arg TIM_CHANNEL_4: TIM Channel 4
03778   * @retval HAL status
03779   */ 
03780 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
03781 {
03782   uint32_t tmpsmcr = 0;
03783 
03784   /* Check the parameters */
03785   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
03786   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03787   assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03788   assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03789   assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03790 
03791   /* Process Locked */
03792   __HAL_LOCK(htim);
03793 
03794   htim->State = HAL_TIM_STATE_BUSY;
03795 
03796   switch (sClearInputConfig->ClearInputSource)
03797   {
03798     case TIM_CLEARINPUTSOURCE_NONE:
03799     {
03800       /* Clear the OCREF clear selection bit */
03801       tmpsmcr &= ~TIM_SMCR_OCCS;
03802 
03803       /* Clear the ETR Bits */
03804       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03805 
03806       /* Set TIMx_SMCR */
03807       htim->Instance->SMCR = tmpsmcr;
03808    }
03809     break;
03810 
03811     case TIM_CLEARINPUTSOURCE_ETR:
03812     {
03813       TIM_ETR_SetConfig(htim->Instance,
03814                         sClearInputConfig->ClearInputPrescaler,
03815                         sClearInputConfig->ClearInputPolarity,
03816                         sClearInputConfig->ClearInputFilter);
03817 
03818       /* Set the OCREF clear selection bit */
03819       htim->Instance->SMCR |= TIM_SMCR_OCCS;
03820     }
03821     break;
03822     default:
03823     break;
03824   }
03825 
03826   switch (Channel)
03827   {
03828     case TIM_CHANNEL_1:
03829       {
03830         if(sClearInputConfig->ClearInputState != RESET)
03831         {
03832           /* Enable the Ocref clear feature for Channel 1 */
03833           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03834         }
03835         else
03836         {
03837           /* Disable the Ocref clear feature for Channel 1 */
03838         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03839         }
03840       }
03841       break;
03842     case TIM_CHANNEL_2:
03843       {
03844         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03845         if(sClearInputConfig->ClearInputState != RESET)
03846         {
03847           /* Enable the Ocref clear feature for Channel 2 */
03848           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03849         }
03850         else
03851         {
03852           /* Disable the Ocref clear feature for Channel 2 */
03853           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03854         }
03855       }
03856     break;
03857     case TIM_CHANNEL_3:
03858       {
03859         assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03860         if(sClearInputConfig->ClearInputState != RESET)
03861         {
03862           /* Enable the Ocref clear feature for Channel 3 */
03863           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03864         }
03865         else
03866         {
03867           /* Disable the Ocref clear feature for Channel 3 */
03868         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
03869         }
03870       }
03871     break;
03872     case TIM_CHANNEL_4:
03873       {
03874         assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03875         if(sClearInputConfig->ClearInputState != RESET)
03876         {
03877           /* Enable the Ocref clear feature for Channel 4 */
03878           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
03879         }
03880         else
03881         {
03882           /* Disable the Ocref clear feature for Channel 4 */
03883         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
03884         }
03885       }
03886     break;
03887     default:
03888     break;
03889   }
03890 
03891   htim->State = HAL_TIM_STATE_READY;
03892 
03893   __HAL_UNLOCK(htim);
03894 
03895   return HAL_OK;
03896 }
03897 
03898 /**
03899   * @brief   Configures the clock source to be used
03900   * @param  htim : TIM handle
03901   * @param  sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
03902   *         contains the clock source information for the TIM peripheral.
03903   * @retval HAL status
03904   */ 
03905 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
03906 {
03907   uint32_t tmpsmcr = 0;
03908 
03909   /* Process Locked */
03910   __HAL_LOCK(htim);
03911 
03912   htim->State = HAL_TIM_STATE_BUSY;
03913 
03914   /* Check the parameters */
03915   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
03916 
03917   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
03918   tmpsmcr = htim->Instance->SMCR;
03919   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03920   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03921   htim->Instance->SMCR = tmpsmcr;
03922 
03923   switch (sClockSourceConfig->ClockSource)
03924   {
03925   case TIM_CLOCKSOURCE_INTERNAL:
03926     {
03927       assert_param(IS_TIM_INSTANCE(htim->Instance));
03928       /* Disable slave mode to clock the prescaler directly with the internal clock */
03929       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03930     }
03931     break;
03932 
03933   case TIM_CLOCKSOURCE_ETRMODE1:
03934     {
03935       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
03936       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
03937 
03938       /* Check ETR input conditioning related parameters */
03939       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03940       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03941       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03942       
03943       /* Configure the ETR Clock source */
03944       TIM_ETR_SetConfig(htim->Instance,
03945                         sClockSourceConfig->ClockPrescaler,
03946                         sClockSourceConfig->ClockPolarity,
03947                         sClockSourceConfig->ClockFilter);
03948       /* Get the TIMx SMCR register value */
03949       tmpsmcr = htim->Instance->SMCR;
03950       /* Reset the SMS and TS Bits */
03951       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03952       /* Select the External clock mode1 and the ETRF trigger */
03953       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
03954       /* Write to TIMx SMCR */
03955       htim->Instance->SMCR = tmpsmcr;
03956     }
03957     break;
03958 
03959   case TIM_CLOCKSOURCE_ETRMODE2:
03960     {
03961       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
03962       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
03963 
03964       /* Check ETR input conditioning related parameters */
03965       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03966       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03967       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03968       
03969       /* Configure the ETR Clock source */
03970       TIM_ETR_SetConfig(htim->Instance,
03971                         sClockSourceConfig->ClockPrescaler,
03972                         sClockSourceConfig->ClockPolarity,
03973                         sClockSourceConfig->ClockFilter);
03974       /* Enable the External clock mode2 */
03975       htim->Instance->SMCR |= TIM_SMCR_ECE;
03976     }
03977     break;
03978 
03979   case TIM_CLOCKSOURCE_TI1:
03980     {
03981       /* Check whether or not the timer instance supports external clock mode 1 */
03982       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
03983 
03984       /* Check TI1 input conditioning related parameters */
03985       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03986       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03987       
03988       TIM_TI1_ConfigInputStage(htim->Instance,
03989                                sClockSourceConfig->ClockPolarity,
03990                                sClockSourceConfig->ClockFilter);
03991       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
03992     }
03993     break;
03994   case TIM_CLOCKSOURCE_TI2:
03995     {
03996       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
03997       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
03998 
03999        /* Check TI2 input conditioning related parameters */
04000       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04001       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04002 
04003       TIM_TI2_ConfigInputStage(htim->Instance,
04004                                sClockSourceConfig->ClockPolarity,
04005                                sClockSourceConfig->ClockFilter);
04006       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04007     }
04008     break;
04009   case TIM_CLOCKSOURCE_TI1ED:
04010     {
04011       /* Check whether or not the timer instance supports external clock mode 1 */
04012       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04013 
04014       /* Check TI1 input conditioning related parameters */
04015       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04016       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04017 
04018       TIM_TI1_ConfigInputStage(htim->Instance,
04019                                sClockSourceConfig->ClockPolarity,
04020                                sClockSourceConfig->ClockFilter);
04021       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04022     }
04023     break;
04024   case TIM_CLOCKSOURCE_ITR0:
04025     {
04026       /* Check whether or not the timer instance supports external clock mode 1 */
04027       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04028 
04029       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04030     }
04031     break;
04032   case TIM_CLOCKSOURCE_ITR1:
04033     {
04034       /* Check whether or not the timer instance supports external clock mode 1 */
04035       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04036 
04037       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04038     }
04039     break;
04040   case TIM_CLOCKSOURCE_ITR2:
04041     {
04042       /* Check whether or not the timer instance supports external clock mode 1 */
04043       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04044 
04045       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04046     }
04047     break;
04048   case TIM_CLOCKSOURCE_ITR3:
04049     {
04050       /* Check whether or not the timer instance supports external clock mode 1 */
04051       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04052 
04053       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04054     }
04055     break;
04056 
04057   default:
04058     break;
04059   }
04060   htim->State = HAL_TIM_STATE_READY;
04061 
04062   __HAL_UNLOCK(htim);
04063 
04064   return HAL_OK;
04065 }
04066 
04067 /**
04068   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04069   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04070   * @param  htim : TIM handle.
04071   * @param  TI1_Selection : Indicate whether or not channel 1 is connected to the
04072   *         output of a XOR gate.
04073   *          This parameter can be one of the following values:
04074   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04075   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04076   *            pins are connected to the TI1 input (XOR combination)
04077   * @retval HAL status
04078   */
04079 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04080 {
04081   uint32_t tmpcr2 = 0;
04082 
04083   /* Check the parameters */
04084   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04085   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04086 
04087   /* Get the TIMx CR2 register value */
04088   tmpcr2 = htim->Instance->CR2;
04089 
04090   /* Reset the TI1 selection */
04091   tmpcr2 &= ~TIM_CR2_TI1S;
04092 
04093   /* Set the the TI1 selection */
04094   tmpcr2 |= TI1_Selection;
04095 
04096   /* Write to TIMxCR2 */
04097   htim->Instance->CR2 = tmpcr2;
04098 
04099   return HAL_OK;
04100 }
04101 
04102 /**
04103   * @brief  Configures the TIM in Slave mode
04104   * @param  htim : TIM handle.
04105   * @param  sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
04106   *         contains the selected trigger (internal trigger input, filtered
04107   *         timer input or external trigger input) and the ) and the Slave 
04108   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04109   * @retval HAL status
04110   */
04111 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04112 {
04113   /* Check the parameters */
04114   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04115   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04116   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04117 
04118   __HAL_LOCK(htim);
04119 
04120   htim->State = HAL_TIM_STATE_BUSY;
04121 
04122   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04123 
04124   /* Disable Trigger Interrupt */
04125   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04126 
04127   /* Disable Trigger DMA request */
04128   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04129 
04130   htim->State = HAL_TIM_STATE_READY;
04131 
04132   __HAL_UNLOCK(htim);
04133 
04134   return HAL_OK;
04135     }
04136 
04137 /**
04138   * @brief  Configures the TIM in Slave mode in interrupt mode
04139   * @param  htim: TIM handle.
04140   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04141   *         contains the selected trigger (internal trigger input, filtered
04142   *         timer input or external trigger input) and the ) and the Slave 
04143   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04144   * @retval HAL status
04145   */
04146 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04147                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04148     {
04149       /* Check the parameters */
04150   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04151   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04152   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04153 
04154   __HAL_LOCK(htim);
04155 
04156   htim->State = HAL_TIM_STATE_BUSY;
04157 
04158   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04159 
04160   /* Enable Trigger Interrupt */
04161   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04162 
04163   /* Disable Trigger DMA request */
04164   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04165 
04166   htim->State = HAL_TIM_STATE_READY;
04167 
04168   __HAL_UNLOCK(htim);
04169 
04170   return HAL_OK;
04171 }
04172 
04173 /**
04174   * @brief  Read the captured value from Capture Compare unit
04175   * @param  htim : TIM handle.
04176   * @param  Channel : TIM Channels to be enabled
04177   *          This parameter can be one of the following values:
04178   *            @arg TIM_CHANNEL_1 : TIM Channel 1 selected
04179   *            @arg TIM_CHANNEL_2 : TIM Channel 2 selected
04180   *            @arg TIM_CHANNEL_3 : TIM Channel 3 selected
04181   *            @arg TIM_CHANNEL_4 : TIM Channel 4 selected
04182   * @retval Captured value
04183   */
04184 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04185 {
04186   uint32_t tmpreg = 0;
04187 
04188   __HAL_LOCK(htim);
04189 
04190   switch (Channel)
04191   {
04192   case TIM_CHANNEL_1:
04193     {
04194       /* Check the parameters */
04195       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04196 
04197       /* Return the capture 1 value */
04198       tmpreg =  htim->Instance->CCR1;
04199 
04200       break;
04201     }
04202   case TIM_CHANNEL_2:
04203     {
04204       /* Check the parameters */
04205       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04206 
04207       /* Return the capture 2 value */
04208       tmpreg =   htim->Instance->CCR2;
04209 
04210       break;
04211     }
04212 
04213   case TIM_CHANNEL_3:
04214     {
04215       /* Check the parameters */
04216       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04217 
04218       /* Return the capture 3 value */
04219       tmpreg =   htim->Instance->CCR3;
04220 
04221       break;
04222     }
04223 
04224   case TIM_CHANNEL_4:
04225     {
04226       /* Check the parameters */
04227       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04228 
04229       /* Return the capture 4 value */
04230       tmpreg =   htim->Instance->CCR4;
04231 
04232       break;
04233     }
04234 
04235   default:
04236     break;
04237   }
04238 
04239   __HAL_UNLOCK(htim);
04240   return tmpreg;
04241 }
04242 
04243 /**
04244   * @}
04245   */
04246 
04247 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04248  *  @brief    TIM Callbacks functions 
04249  *
04250 @verbatim 
04251   ==============================================================================
04252                         ##### TIM Callbacks functions #####
04253   ==============================================================================
04254  [..]
04255    This section provides TIM callback functions:
04256    (+) Timer Period elapsed callback
04257    (+) Timer Output Compare callback
04258    (+) Timer Input capture callback
04259    (+) Timer Trigger callback
04260    (+) Timer Error callback
04261 
04262 @endverbatim
04263   * @{
04264   */
04265 
04266 /**
04267   * @brief  Period elapsed callback in non blocking mode 
04268   * @param  htim : TIM handle
04269   * @retval None
04270   */
04271 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04272 {
04273   /* Prevent unused argument(s) compilation warning */
04274   UNUSED(htim);
04275   /* NOTE : This function Should not be modified, when the callback is needed,
04276             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04277    */
04278 
04279 }
04280 /**
04281   * @brief  Output Compare callback in non blocking mode 
04282   * @param  htim : TIM OC handle
04283   * @retval None
04284   */
04285 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04286 {
04287   /* Prevent unused argument(s) compilation warning */
04288   UNUSED(htim);
04289   /* NOTE : This function Should not be modified, when the callback is needed,
04290             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04291    */
04292 }
04293 /**
04294   * @brief  Input Capture callback in non blocking mode 
04295   * @param  htim : TIM IC handle
04296   * @retval None
04297   */
04298 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04299 {
04300   /* Prevent unused argument(s) compilation warning */
04301   UNUSED(htim);
04302   /* NOTE : This function Should not be modified, when the callback is needed,
04303             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04304    */
04305 }
04306 
04307 /**
04308   * @brief  PWM Pulse finished callback in non blocking mode 
04309   * @param  htim : TIM handle
04310   * @retval None
04311   */
04312 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04313 {
04314   /* Prevent unused argument(s) compilation warning */
04315   UNUSED(htim);
04316   /* NOTE : This function Should not be modified, when the callback is needed,
04317             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04318    */
04319 }
04320 
04321 /**
04322   * @brief  Hall Trigger detection callback in non blocking mode 
04323   * @param  htim : TIM handle
04324   * @retval None
04325   */
04326 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04327 {
04328   /* Prevent unused argument(s) compilation warning */
04329   UNUSED(htim);
04330   /* NOTE : This function Should not be modified, when the callback is needed,
04331             the HAL_TIM_TriggerCallback could be implemented in the user file
04332    */
04333 }
04334 
04335 /**
04336   * @brief  Timer error callback in non blocking mode 
04337   * @param  htim : TIM handle
04338   * @retval None
04339   */
04340 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04341 {
04342   /* Prevent unused argument(s) compilation warning */
04343   UNUSED(htim);
04344   /* NOTE : This function Should not be modified, when the callback is needed,
04345             the HAL_TIM_ErrorCallback could be implemented in the user file
04346    */
04347 }
04348 
04349 /**
04350   * @}
04351   */
04352 
04353 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 
04354  *  @brief   Peripheral State functions 
04355  *
04356 @verbatim 
04357   ==============================================================================
04358                         ##### Peripheral State functions #####
04359   ==============================================================================
04360     [..]
04361     This subsection permit to get in run-time the status of the peripheral 
04362     and the data flow.
04363 
04364 @endverbatim
04365   * @{
04366   */
04367 
04368 /**
04369   * @brief  Return the TIM Base state
04370   * @param  htim : TIM Base handle
04371   * @retval HAL state
04372   */
04373 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04374 {
04375   return htim->State;
04376 }
04377 
04378 /**
04379   * @brief  Return the TIM OC state
04380   * @param  htim : TIM Ouput Compare handle
04381   * @retval HAL state
04382   */
04383 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04384 {
04385   return htim->State;
04386 }
04387 
04388 /**
04389   * @brief  Return the TIM PWM state
04390   * @param  htim : TIM handle
04391   * @retval HAL state
04392   */
04393 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04394 {
04395   return htim->State;
04396 }
04397 
04398 /**
04399   * @brief  Return the TIM Input Capture state
04400   * @param  htim : TIM IC handle
04401   * @retval HAL state
04402   */
04403 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04404 {
04405   return htim->State;
04406 }
04407 
04408 /**
04409   * @brief  Return the TIM One Pulse Mode state
04410   * @param  htim : TIM OPM handle
04411   * @retval HAL state
04412   */
04413 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04414 {
04415   return htim->State;
04416 }
04417 
04418 /**
04419   * @brief  Return the TIM Encoder Mode state
04420   * @param  htim : TIM Encoder handle
04421   * @retval HAL state
04422   */
04423 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04424 {
04425   return htim->State;
04426 }
04427 
04428 /**
04429   * @}
04430   */
04431 
04432 /**
04433   * @}
04434   */
04435 
04436 /** @addtogroup TIM_Private_Functions
04437   * @{
04438   */
04439 
04440 /**
04441   * @brief  TIM DMA error callback 
04442   * @param  hdma : pointer to DMA handle.
04443   * @retval None
04444   */
04445 void TIM_DMAError(DMA_HandleTypeDef *hdma)
04446 {
04447   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04448 
04449   htim->State= HAL_TIM_STATE_READY;
04450 
04451   HAL_TIM_ErrorCallback(htim);
04452 }
04453 
04454 /**
04455   * @brief  TIM DMA Delay Pulse complete callback.
04456   * @param  hdma : pointer to DMA handle.
04457   * @retval None
04458   */
04459 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04460 {
04461   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04462 
04463   htim->State= HAL_TIM_STATE_READY;
04464 
04465   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04466   {
04467     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04468   }
04469   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04470   {
04471     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04472   }
04473   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04474   {
04475     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04476   }
04477   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04478   {
04479     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04480   }
04481 
04482   HAL_TIM_PWM_PulseFinishedCallback(htim);
04483 
04484   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04485 }
04486 /**
04487   * @brief  TIM DMA Capture complete callback.
04488   * @param  hdma : pointer to DMA handle.
04489   * @retval None
04490   */
04491 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04492 {
04493   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04494 
04495   htim->State= HAL_TIM_STATE_READY;
04496 
04497   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04498   {
04499     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04500   }
04501   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04502   {
04503     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04504   }
04505   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04506   {
04507     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04508   }
04509   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04510   {
04511     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04512   }
04513 
04514   HAL_TIM_IC_CaptureCallback(htim);
04515 
04516   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04517 }
04518 
04519 /**
04520   * @brief  TIM DMA Period Elapse complete callback.
04521   * @param  hdma : pointer to DMA handle.
04522   * @retval None
04523   */
04524 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04525 {
04526   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04527 
04528   htim->State= HAL_TIM_STATE_READY;
04529 
04530   HAL_TIM_PeriodElapsedCallback(htim);
04531 }
04532 
04533 /**
04534   * @brief  TIM DMA Trigger callback.
04535   * @param  hdma : pointer to DMA handle.
04536   * @retval None
04537   */
04538 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04539 {
04540   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04541 
04542   htim->State= HAL_TIM_STATE_READY;
04543 
04544   HAL_TIM_TriggerCallback(htim);
04545 }
04546 
04547 /**
04548   * @brief  Time Base configuration
04549   * @param  TIMx : TIM periheral
04550   * @param  Structure : TIM Base configuration structure
04551   * @retval None
04552   */
04553 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04554 {
04555   uint32_t tmpcr1 = 0;
04556   tmpcr1 = TIMx->CR1 ;
04557 
04558   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04559   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
04560   {
04561     /* Select the Counter Mode */
04562     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04563     tmpcr1 |= Structure->CounterMode;
04564   }
04565 
04566   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
04567   {
04568     /* Set the clock division */
04569     tmpcr1 &= ~TIM_CR1_CKD;
04570     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04571   }
04572 
04573   TIMx->CR1  = tmpcr1;
04574 
04575   /* Set the Autoreload value */
04576   TIMx->ARR  = (uint32_t)Structure->Period ;
04577 
04578   /* Set the Prescaler value */
04579   TIMx->PSC  = (uint32_t)Structure->Prescaler;
04580 
04581   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
04582   {
04583     /* Set the Repetition Counter value */
04584     TIMx->RCR  = Structure->RepetitionCounter;
04585   }
04586 
04587   /* Generate an update event to reload the Prescaler 
04588      and the repetition counter(only for TIM1 and TIM8) value immediatly */
04589   TIMx->EGR  = TIM_EGR_UG;
04590 }
04591 
04592 /**
04593   * @brief  Time Ouput Compare 1 configuration
04594   * @param  TIMx to select the TIM peripheral
04595   * @param  OC_Config : The ouput configuration structure
04596   * @retval None
04597   */
04598 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04599 {
04600   uint32_t tmpccmrx = 0;
04601   uint32_t tmpccer = 0;
04602   uint32_t tmpcr2 = 0;
04603 
04604    /* Disable the Channel 1: Reset the CC1E Bit */
04605   TIMx->CCER  &= ~TIM_CCER_CC1E;
04606 
04607   /* Get the TIMx CCER register value */
04608   tmpccer = TIMx->CCER ;
04609   /* Get the TIMx CR2 register value */
04610   tmpcr2 =  TIMx->CR2 ;
04611 
04612   /* Get the TIMx CCMR1 register value */
04613   tmpccmrx = TIMx->CCMR1 ;
04614 
04615   /* Reset the Output Compare Mode Bits */
04616   tmpccmrx &= ~TIM_CCMR1_OC1M;
04617   tmpccmrx &= ~TIM_CCMR1_CC1S;
04618   /* Select the Output Compare Mode */
04619   tmpccmrx |= OC_Config->OCMode;
04620 
04621   /* Reset the Output Polarity level */
04622   tmpccer &= ~TIM_CCER_CC1P;
04623   /* Set the Output Compare Polarity */
04624   tmpccer |= OC_Config->OCPolarity;
04625 
04626   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
04627   {
04628     /* Check parameters */
04629     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04630 
04631     /* Reset the Output N Polarity level */
04632     tmpccer &= ~TIM_CCER_CC1NP;
04633     /* Set the Output N Polarity */
04634     tmpccer |= OC_Config->OCNPolarity;
04635     /* Reset the Output N State */
04636     tmpccer &= ~TIM_CCER_CC1NE;
04637   }
04638 
04639   if(IS_TIM_BREAK_INSTANCE(TIMx))
04640   {
04641     /* Check parameters */
04642     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04643     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04644 
04645     /* Reset the Output Compare and Output Compare N IDLE State */
04646     tmpcr2 &= ~TIM_CR2_OIS1;
04647     tmpcr2 &= ~TIM_CR2_OIS1N;
04648     /* Set the Output Idle state */
04649     tmpcr2 |= OC_Config->OCIdleState;
04650     /* Set the Output N Idle state */
04651     tmpcr2 |= OC_Config->OCNIdleState;
04652   }
04653   /* Write to TIMx CR2 */
04654   TIMx->CR2  = tmpcr2;
04655 
04656   /* Write to TIMx CCMR1 */
04657   TIMx->CCMR1  = tmpccmrx;
04658 
04659   /* Set the Capture Compare Register value */
04660   TIMx->CCR1  = OC_Config->Pulse;
04661 
04662   /* Write to TIMx CCER */
04663   TIMx->CCER  = tmpccer;
04664 }
04665 
04666 /**
04667   * @brief  Time Ouput Compare 2 configuration
04668   * @param  TIMx  to select the TIM peripheral
04669   * @param  OC_Config : The ouput configuration structure
04670   * @retval None
04671   */
04672 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04673 {
04674   uint32_t tmpccmrx = 0;
04675   uint32_t tmpccer = 0;
04676   uint32_t tmpcr2 = 0;
04677 
04678   /* Disable the Channel 2: Reset the CC2E Bit */
04679   TIMx->CCER  &= ~TIM_CCER_CC2E;
04680 
04681   /* Get the TIMx CCER register value */
04682   tmpccer = TIMx->CCER ;
04683   /* Get the TIMx CR2 register value */
04684   tmpcr2 =  TIMx->CR2 ;
04685 
04686   /* Get the TIMx CCMR1 register value */
04687   tmpccmrx = TIMx->CCMR1 ;
04688 
04689   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04690   tmpccmrx &= ~TIM_CCMR1_OC2M;
04691   tmpccmrx &= ~TIM_CCMR1_CC2S;
04692 
04693   /* Select the Output Compare Mode */
04694   tmpccmrx |= (OC_Config->OCMode << 8);
04695 
04696   /* Reset the Output Polarity level */
04697   tmpccer &= ~TIM_CCER_CC2P;
04698   /* Set the Output Compare Polarity */
04699   tmpccer |= (OC_Config->OCPolarity << 4);
04700 
04701   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
04702   {
04703     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04704 
04705     /* Reset the Output N Polarity level */
04706     tmpccer &= ~TIM_CCER_CC2NP;
04707     /* Set the Output N Polarity */
04708     tmpccer |= (OC_Config->OCNPolarity << 4);
04709     /* Reset the Output N State */
04710     tmpccer &= ~TIM_CCER_CC2NE;
04711 
04712   }
04713 
04714   if(IS_TIM_BREAK_INSTANCE(TIMx))
04715   {
04716     /* Check parameters */
04717     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04718     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04719 
04720     /* Reset the Output Compare and Output Compare N IDLE State */
04721     tmpcr2 &= ~TIM_CR2_OIS2;
04722     tmpcr2 &= ~TIM_CR2_OIS2N;
04723     /* Set the Output Idle state */
04724     tmpcr2 |= (OC_Config->OCIdleState << 2);
04725     /* Set the Output N Idle state */
04726     tmpcr2 |= (OC_Config->OCNIdleState << 2);
04727   }
04728 
04729   /* Write to TIMx CR2 */
04730   TIMx->CR2  = tmpcr2;
04731 
04732   /* Write to TIMx CCMR1 */
04733   TIMx->CCMR1  = tmpccmrx;
04734 
04735   /* Set the Capture Compare Register value */
04736   TIMx->CCR2  = OC_Config->Pulse;
04737 
04738   /* Write to TIMx CCER */
04739   TIMx->CCER  = tmpccer;
04740 }
04741 
04742 /**
04743   * @brief  Time Ouput Compare 3 configuration
04744   * @param  TIMx  to select the TIM peripheral
04745   * @param  OC_Config : The ouput configuration structure
04746   * @retval None
04747   */
04748 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04749 {
04750   uint32_t tmpccmrx = 0;
04751   uint32_t tmpccer = 0;
04752   uint32_t tmpcr2 = 0;
04753 
04754   /* Disable the Channel 3: Reset the CC2E Bit */
04755   TIMx->CCER  &= ~TIM_CCER_CC3E;
04756 
04757   /* Get the TIMx CCER register value */
04758   tmpccer = TIMx->CCER ;
04759   /* Get the TIMx CR2 register value */
04760   tmpcr2 =  TIMx->CR2 ;
04761 
04762   /* Get the TIMx CCMR2 register value */
04763   tmpccmrx = TIMx->CCMR2 ;
04764 
04765   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04766   tmpccmrx &= ~TIM_CCMR2_OC3M;
04767   tmpccmrx &= ~TIM_CCMR2_CC3S;
04768   /* Select the Output Compare Mode */
04769   tmpccmrx |= OC_Config->OCMode;
04770 
04771   /* Reset the Output Polarity level */
04772   tmpccer &= ~TIM_CCER_CC3P;
04773   /* Set the Output Compare Polarity */
04774   tmpccer |= (OC_Config->OCPolarity << 8);
04775 
04776   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
04777   {
04778     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04779 
04780     /* Reset the Output N Polarity level */
04781     tmpccer &= ~TIM_CCER_CC3NP;
04782     /* Set the Output N Polarity */
04783     tmpccer |= (OC_Config->OCNPolarity << 8);
04784     /* Reset the Output N State */
04785     tmpccer &= ~TIM_CCER_CC3NE;
04786   }
04787 
04788   if(IS_TIM_BREAK_INSTANCE(TIMx))
04789   {
04790     /* Check parameters */
04791     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04792     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04793 
04794     /* Reset the Output Compare and Output Compare N IDLE State */
04795     tmpcr2 &= ~TIM_CR2_OIS3;
04796     tmpcr2 &= ~TIM_CR2_OIS3N;
04797     /* Set the Output Idle state */
04798     tmpcr2 |= (OC_Config->OCIdleState << 4);
04799     /* Set the Output N Idle state */
04800     tmpcr2 |= (OC_Config->OCNIdleState << 4);
04801   }
04802 
04803   /* Write to TIMx CR2 */
04804   TIMx->CR2  = tmpcr2;
04805 
04806   /* Write to TIMx CCMR2 */
04807   TIMx->CCMR2  = tmpccmrx;
04808 
04809   /* Set the Capture Compare Register value */
04810   TIMx->CCR3  = OC_Config->Pulse;
04811 
04812   /* Write to TIMx CCER */
04813   TIMx->CCER  = tmpccer;
04814 }
04815 
04816 /**
04817   * @brief  Time Ouput Compare 4 configuration
04818   * @param  TIMx  to select the TIM peripheral
04819   * @param  OC_Config : The ouput configuration structure
04820   * @retval None
04821   */
04822 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04823 {
04824   uint32_t tmpccmrx = 0;
04825   uint32_t tmpccer = 0;
04826   uint32_t tmpcr2 = 0;
04827 
04828   /* Disable the Channel 4: Reset the CC4E Bit */
04829   TIMx->CCER  &= ~TIM_CCER_CC4E;
04830 
04831   /* Get the TIMx CCER register value */
04832   tmpccer = TIMx->CCER ;
04833   /* Get the TIMx CR2 register value */
04834   tmpcr2 =  TIMx->CR2 ;
04835 
04836   /* Get the TIMx CCMR2 register value */
04837   tmpccmrx = TIMx->CCMR2 ;
04838 
04839   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04840   tmpccmrx &= ~TIM_CCMR2_OC4M;
04841   tmpccmrx &= ~TIM_CCMR2_CC4S;
04842 
04843   /* Select the Output Compare Mode */
04844   tmpccmrx |= (OC_Config->OCMode << 8);
04845 
04846   /* Reset the Output Polarity level */
04847   tmpccer &= ~TIM_CCER_CC4P;
04848   /* Set the Output Compare Polarity */
04849   tmpccer |= (OC_Config->OCPolarity << 12);
04850 
04851   if(IS_TIM_BREAK_INSTANCE(TIMx))
04852   {
04853     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04854 
04855    /* Reset the Output Compare IDLE State */
04856     tmpcr2 &= ~TIM_CR2_OIS4;
04857     /* Set the Output Idle state */
04858     tmpcr2 |= (OC_Config->OCIdleState << 6);
04859   }
04860 
04861   /* Write to TIMx CR2 */
04862   TIMx->CR2  = tmpcr2;
04863 
04864   /* Write to TIMx CCMR2 */
04865   TIMx->CCMR2  = tmpccmrx;
04866 
04867   /* Set the Capture Compare Register value */
04868   TIMx->CCR4  = OC_Config->Pulse;
04869 
04870   /* Write to TIMx CCER */
04871   TIMx->CCER  = tmpccer;
04872 }
04873 
04874 
04875 /**
04876   * @brief  Time Slave configuration
04877   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04878   *                the configuration information for TIM module.
04879   * @param  sSlaveConfig: The slave configuration structure
04880   * @retval None
04881   */
04882 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
04883                               TIM_SlaveConfigTypeDef * sSlaveConfig)
04884 {
04885   uint32_t tmpsmcr = 0;
04886   uint32_t tmpccmr1 = 0;
04887   uint32_t tmpccer = 0;
04888 
04889   /* Get the TIMx SMCR register value */
04890   tmpsmcr = htim->Instance->SMCR;
04891 
04892   /* Reset the Trigger Selection Bits */
04893   tmpsmcr &= ~TIM_SMCR_TS;
04894   /* Set the Input Trigger source */
04895   tmpsmcr |= sSlaveConfig->InputTrigger;
04896 
04897   /* Reset the slave mode Bits */
04898   tmpsmcr &= ~TIM_SMCR_SMS;
04899   /* Set the slave mode */
04900   tmpsmcr |= sSlaveConfig->SlaveMode;
04901 
04902   /* Write to TIMx SMCR */
04903   htim->Instance->SMCR = tmpsmcr;
04904 
04905   /* Configure the trigger prescaler, filter, and polarity */
04906   switch (sSlaveConfig->InputTrigger)
04907   {
04908   case TIM_TS_ETRF:
04909     {
04910       /* Check the parameters */
04911       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04912       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
04913       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04914       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04915       /* Configure the ETR Trigger source */
04916       TIM_ETR_SetConfig(htim->Instance,
04917                         sSlaveConfig->TriggerPrescaler,
04918                         sSlaveConfig->TriggerPolarity,
04919                         sSlaveConfig->TriggerFilter);
04920     }
04921     break;
04922 
04923   case TIM_TS_TI1F_ED:
04924     {
04925       /* Check the parameters */
04926       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04927       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04928 
04929       /* Disable the Channel 1: Reset the CC1E Bit */
04930       tmpccer = htim->Instance->CCER;
04931       htim->Instance->CCER &= ~TIM_CCER_CC1E;
04932       tmpccmr1 = htim->Instance->CCMR1;
04933 
04934       /* Set the filter */
04935       tmpccmr1 &= ~TIM_CCMR1_IC1F;
04936       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
04937 
04938       /* Write to TIMx CCMR1 and CCER registers */
04939       htim->Instance->CCMR1 = tmpccmr1;
04940       htim->Instance->CCER = tmpccer;
04941 
04942     }
04943     break;
04944 
04945   case TIM_TS_TI1FP1:
04946     {
04947       /* Check the parameters */
04948       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04949       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04950       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04951 
04952       /* Configure TI1 Filter and Polarity */
04953       TIM_TI1_ConfigInputStage(htim->Instance,
04954                                sSlaveConfig->TriggerPolarity,
04955                                sSlaveConfig->TriggerFilter);
04956     }
04957     break;
04958 
04959   case TIM_TS_TI2FP2:
04960     {
04961       /* Check the parameters */
04962       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04963       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04964       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04965 
04966       /* Configure TI2 Filter and Polarity */
04967       TIM_TI2_ConfigInputStage(htim->Instance,
04968                                 sSlaveConfig->TriggerPolarity,
04969                                 sSlaveConfig->TriggerFilter);
04970     }
04971     break;
04972 
04973   case TIM_TS_ITR0:
04974     {
04975       /* Check the parameter */
04976       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04977     }
04978     break;
04979 
04980   case TIM_TS_ITR1:
04981     {
04982       /* Check the parameter */
04983       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04984     }
04985     break;
04986 
04987   case TIM_TS_ITR2:
04988     {
04989       /* Check the parameter */
04990       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04991     }
04992     break;
04993 
04994   case TIM_TS_ITR3:
04995     {
04996       /* Check the parameter */
04997       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04998     }
04999     break;
05000 
05001   default:
05002     break;
05003   }
05004 }
05005 
05006 /**
05007   * @brief  Configure the TI1 as Input.
05008   * @param  TIMx  to select the TIM peripheral.
05009   * @param  TIM_ICPolarity : The Input Polarity.
05010   *          This parameter can be one of the following values:
05011   *            @arg TIM_ICPOLARITY_RISING
05012   *            @arg TIM_ICPOLARITY_FALLING
05013   *            @arg TIM_ICPOLARITY_BOTHEDGE
05014   * @param  TIM_ICSelection : specifies the input to be used.
05015   *          This parameter can be one of the following values:
05016   *            @arg TIM_ICSELECTION_DIRECTTI:    TIM Input 1 is selected to be connected to IC1.
05017   *            @arg TIM_ICSELECTION_INDIRECTTI:  TIM Input 1 is selected to be connected to IC2.
05018   *            @arg TIM_ICSELECTION_TRC:         TIM Input 1 is selected to be connected to TRC.
05019   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05020   *          This parameter must be a value between 0x00 and 0x0F.
05021   * @retval None
05022   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 
05023   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be 
05024   *        protected against un-initialized filter and polarity values.
05025   */
05026 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05027                        uint32_t TIM_ICFilter)
05028 {
05029   uint32_t tmpccmr1 = 0;
05030   uint32_t tmpccer = 0;
05031 
05032   /* Disable the Channel 1: Reset the CC1E Bit */
05033   TIMx->CCER  &= ~TIM_CCER_CC1E;
05034   tmpccmr1 = TIMx->CCMR1 ;
05035   tmpccer = TIMx->CCER ;
05036 
05037   /* Select the Input */
05038   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05039   {
05040     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05041     tmpccmr1 |= TIM_ICSelection;
05042   }
05043   else
05044   {
05045     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05046   }
05047 
05048   /* Set the filter */
05049   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05050   tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
05051 
05052   /* Select the Polarity and set the CC1E Bit */
05053   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05054   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05055 
05056   /* Write to TIMx CCMR1 and CCER registers */
05057   TIMx->CCMR1  = tmpccmr1;
05058   TIMx->CCER  = tmpccer;
05059 }
05060 
05061 /**
05062   * @brief  Configure the Polarity and Filter for TI1.
05063   * @param  TIMx  to select the TIM peripheral.
05064   * @param  TIM_ICPolarity : The Input Polarity.
05065   *          This parameter can be one of the following values:
05066   *            @arg TIM_ICPOLARITY_RISING   
05067   *            @arg TIM_ICPOLARITY_FALLING  
05068   *            @arg TIM_ICPOLARITY_BOTHEDGE 
05069   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05070   *          This parameter must be a value between 0x00 and 0x0F.
05071   * @retval None
05072   */
05073 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05074 {
05075   uint32_t tmpccmr1 = 0;
05076   uint32_t tmpccer = 0;
05077 
05078   /* Disable the Channel 1: Reset the CC1E Bit */
05079   tmpccer = TIMx->CCER ;
05080   TIMx->CCER  &= ~TIM_CCER_CC1E;
05081   tmpccmr1 = TIMx->CCMR1 ;
05082 
05083   /* Set the filter */
05084   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05085   tmpccmr1 |= (TIM_ICFilter << 4);
05086 
05087   /* Select the Polarity and set the CC1E Bit */
05088   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05089   tmpccer |= TIM_ICPolarity;
05090 
05091   /* Write to TIMx CCMR1 and CCER registers */
05092   TIMx->CCMR1  = tmpccmr1;
05093   TIMx->CCER  = tmpccer;
05094 }
05095 
05096 /**
05097   * @brief  Configure the TI2 as Input.
05098   * @param  TIMx  to select the TIM peripheral
05099   * @param  TIM_ICPolarity : The Input Polarity.
05100   *          This parameter can be one of the following values:
05101   *            @arg TIM_ICPOLARITY_RISING   
05102   *            @arg TIM_ICPOLARITY_FALLING  
05103   *            @arg TIM_ICPOLARITY_BOTHEDGE 
05104   * @param  TIM_ICSelection : specifies the input to be used.
05105   *          This parameter can be one of the following values:
05106   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 2 is selected to be connected to IC2.
05107   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
05108   *            @arg TIM_ICSELECTION_TRC:        TIM Input 2 is selected to be connected to TRC.
05109   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05110   *          This parameter must be a value between 0x00 and 0x0F.
05111   * @retval None
05112   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 
05113   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be 
05114   *        protected against un-initialized filter and polarity values.
05115   */
05116 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05117                        uint32_t TIM_ICFilter)
05118 {
05119   uint32_t tmpccmr1 = 0;
05120   uint32_t tmpccer = 0;
05121 
05122   /* Disable the Channel 2: Reset the CC2E Bit */
05123   TIMx->CCER  &= ~TIM_CCER_CC2E;
05124   tmpccmr1 = TIMx->CCMR1 ;
05125   tmpccer = TIMx->CCER ;
05126 
05127   /* Select the Input */
05128   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05129   tmpccmr1 |= (TIM_ICSelection << 8);
05130 
05131   /* Set the filter */
05132   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05133   tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
05134 
05135   /* Select the Polarity and set the CC2E Bit */
05136   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05137   tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05138 
05139   /* Write to TIMx CCMR1 and CCER registers */
05140   TIMx->CCMR1  = tmpccmr1 ;
05141   TIMx->CCER  = tmpccer;
05142 }
05143 
05144 /**
05145   * @brief  Configure the Polarity and Filter for TI2.
05146   * @param  TIMx  to select the TIM peripheral.
05147   * @param  TIM_ICPolarity : The Input Polarity.
05148   *          This parameter can be one of the following values:
05149   *            @arg TIM_ICPOLARITY_RISING  
05150   *            @arg TIM_ICPOLARITY_FALLING 
05151   *            @arg TIM_ICPOLARITY_BOTHEDGE
05152   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05153   *          This parameter must be a value between 0x00 and 0x0F.
05154   * @retval None
05155   */
05156 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05157 {
05158   uint32_t tmpccmr1 = 0;
05159   uint32_t tmpccer = 0;
05160 
05161   /* Disable the Channel 2: Reset the CC2E Bit */
05162   TIMx->CCER  &= ~TIM_CCER_CC2E;
05163   tmpccmr1 = TIMx->CCMR1 ;
05164   tmpccer = TIMx->CCER ;
05165 
05166   /* Set the filter */
05167   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05168   tmpccmr1 |= (TIM_ICFilter << 12);
05169 
05170   /* Select the Polarity and set the CC2E Bit */
05171   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05172   tmpccer |= (TIM_ICPolarity << 4);
05173 
05174   /* Write to TIMx CCMR1 and CCER registers */
05175   TIMx->CCMR1  = tmpccmr1 ;
05176   TIMx->CCER  = tmpccer;
05177 }
05178 
05179 /**
05180   * @brief  Configure the TI3 as Input.
05181   * @param  TIMx  to select the TIM peripheral
05182   * @param  TIM_ICPolarity : The Input Polarity.
05183   *          This parameter can be one of the following values:
05184   *            @arg TIM_ICPOLARITY_RISING  
05185   *            @arg TIM_ICPOLARITY_FALLING 
05186   *            @arg TIM_ICPOLARITY_BOTHEDGE
05187   * @param  TIM_ICSelection : specifies the input to be used.
05188   *          This parameter can be one of the following values:
05189   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 3 is selected to be connected to IC3.
05190   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
05191   *            @arg TIM_ICSELECTION_TRC:        TIM Input 3 is selected to be connected to TRC.
05192   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05193   *          This parameter must be a value between 0x00 and 0x0F.
05194   * @retval None
05195   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 
05196   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be 
05197   *        protected against un-initialized filter and polarity values.
05198   */
05199 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05200                        uint32_t TIM_ICFilter)
05201 {
05202   uint32_t tmpccmr2 = 0;
05203   uint32_t tmpccer = 0;
05204 
05205   /* Disable the Channel 3: Reset the CC3E Bit */
05206   TIMx->CCER  &= ~TIM_CCER_CC3E;
05207   tmpccmr2 = TIMx->CCMR2 ;
05208   tmpccer = TIMx->CCER ;
05209 
05210   /* Select the Input */
05211   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05212   tmpccmr2 |= TIM_ICSelection;
05213 
05214   /* Set the filter */
05215   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05216   tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
05217 
05218   /* Select the Polarity and set the CC3E Bit */
05219   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05220   tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05221 
05222   /* Write to TIMx CCMR2 and CCER registers */
05223   TIMx->CCMR2  = tmpccmr2;
05224   TIMx->CCER  = tmpccer;
05225 }
05226 
05227 /**
05228   * @brief  Configure the TI4 as Input.
05229   * @param  TIMx to select the TIM peripheral
05230   * @param  TIM_ICPolarity : The Input Polarity.
05231   *          This parameter can be one of the following values:
05232   *            @arg TIM_ICPOLARITY_RISING  
05233   *            @arg TIM_ICPOLARITY_FALLING 
05234   *            @arg TIM_ICPOLARITY_BOTHEDGE
05235   * @param  TIM_ICSelection : specifies the input to be used.
05236   *          This parameter can be one of the following values:
05237   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 4 is selected to be connected to IC4.
05238   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
05239   *            @arg TIM_ICSELECTION_TRC:        TIM Input 4 is selected to be connected to TRC.
05240   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05241   *          This parameter must be a value between 0x00 and 0x0F.
05242   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 
05243   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be 
05244   *        protected against un-initialized filter and polarity values.
05245   * @retval None
05246   */
05247 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05248                        uint32_t TIM_ICFilter)
05249 {
05250   uint32_t tmpccmr2 = 0;
05251   uint32_t tmpccer = 0;
05252 
05253   /* Disable the Channel 4: Reset the CC4E Bit */
05254   TIMx->CCER  &= ~TIM_CCER_CC4E;
05255   tmpccmr2 = TIMx->CCMR2 ;
05256   tmpccer = TIMx->CCER ;
05257 
05258   /* Select the Input */
05259   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05260   tmpccmr2 |= (TIM_ICSelection << 8);
05261 
05262   /* Set the filter */
05263   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05264   tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
05265 
05266   /* Select the Polarity and set the CC4E Bit */
05267   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05268   tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05269 
05270   /* Write to TIMx CCMR2 and CCER registers */
05271   TIMx->CCMR2  = tmpccmr2;
05272   TIMx->CCER  = tmpccer ;
05273 }
05274 
05275 /**
05276   * @brief  Selects the Input Trigger source
05277   * @param  TIMx  to select the TIM peripheral
05278   * @param  InputTriggerSource : The Input Trigger source.
05279   *          This parameter can be one of the following values:
05280   *            @arg TIM_TS_ITR0 : Internal Trigger 0
05281   *            @arg TIM_TS_ITR1 : Internal Trigger 1
05282   *            @arg TIM_TS_ITR2 : Internal Trigger 2
05283   *            @arg TIM_TS_ITR3 : Internal Trigger 3
05284   *            @arg TIM_TS_TI1F_ED : TI1 Edge Detector
05285   *            @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
05286   *            @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
05287   *            @arg TIM_TS_ETRF : External Trigger input
05288   * @retval None
05289   */
05290 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
05291 {
05292   uint32_t tmpsmcr = 0;
05293 
05294    /* Get the TIMx SMCR register value */
05295    tmpsmcr = TIMx->SMCR ;
05296    /* Reset the TS Bits */
05297    tmpsmcr &= ~TIM_SMCR_TS;
05298    /* Set the Input Trigger source and the slave mode*/
05299    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
05300    /* Write to TIMx SMCR */
05301    TIMx->SMCR  = tmpsmcr;
05302 }
05303 /**
05304   * @brief  Configures the TIMx External Trigger (ETR).
05305   * @param  TIMx  to select the TIM peripheral
05306   * @param  TIM_ExtTRGPrescaler : The external Trigger Prescaler.
05307   *          This parameter can be one of the following values:
05308   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
05309   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
05310   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
05311   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
05312   * @param  TIM_ExtTRGPolarity : The external Trigger Polarity.
05313   *          This parameter can be one of the following values:
05314   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
05315   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
05316   * @param  ExtTRGFilter : External Trigger Filter.
05317   *          This parameter must be a value between 0x00 and 0x0F
05318   * @retval None
05319   */
05320 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05321                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05322 {
05323   uint32_t tmpsmcr = 0;
05324 
05325   tmpsmcr = TIMx->SMCR ;
05326 
05327   /* Reset the ETR Bits */
05328   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05329 
05330   /* Set the Prescaler, the Filter value and the Polarity */
05331   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
05332 
05333   /* Write to TIMx SMCR */
05334   TIMx->SMCR  = tmpsmcr;
05335 }
05336 
05337 /**
05338   * @brief  Enables or disables the TIM Capture Compare Channel x.
05339   * @param  TIMx  to select the TIM peripheral
05340   * @param  Channel : specifies the TIM Channel
05341   *          This parameter can be one of the following values:
05342   *            @arg TIM_CHANNEL_1: TIM Channel 1
05343   *            @arg TIM_CHANNEL_2: TIM Channel 2
05344   *            @arg TIM_CHANNEL_3: TIM Channel 3
05345   *            @arg TIM_CHANNEL_4: TIM Channel 4
05346   * @param  ChannelState : specifies the TIM Channel CCxE bit new state.
05347   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05348   * @retval None
05349   */
05350 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05351 {
05352   uint32_t tmp = 0;
05353 
05354   /* Check the parameters */
05355   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05356   assert_param(IS_TIM_CHANNELS(Channel));
05357 
05358   tmp = TIM_CCER_CC1E << Channel;
05359 
05360   /* Reset the CCxE Bit */
05361   TIMx->CCER  &= ~tmp;
05362 
05363   /* Set or reset the CCxE Bit */
05364   TIMx->CCER  |=  (uint32_t)(ChannelState << Channel);
05365 }
05366 
05367 /**
05368   * @}
05369   */
05370 
05371 #endif /* HAL_TIM_MODULE_ENABLED */
05372 /**
05373   * @}
05374   */
05375 
05376 /**
05377   * @}
05378   */
05379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/