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stm32f1xx_hal_rcc.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_rcc.c 00004 * @author MCD Application Team 00005 * @version V1.0.4 00006 * @date 29-April-2016 00007 * @brief RCC HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the Reset and Clock Control (RCC) peripheral: 00010 * + Initialization and de-initialization functions 00011 * + Peripheral Control functions 00012 * 00013 @verbatim 00014 ============================================================================== 00015 ##### RCC specific features ##### 00016 ============================================================================== 00017 [..] 00018 After reset the device is running from Internal High Speed oscillator 00019 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, 00020 and all peripherals are off except internal SRAM, Flash and JTAG. 00021 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; 00022 all peripherals mapped on these buses are running at HSI speed. 00023 (+) The clock for all peripherals is switched off, except the SRAM and FLASH. 00024 (+) All GPIOs are in input floating state, except the JTAG pins which 00025 are assigned to be used for debug purpose. 00026 [..] Once the device started from reset, the user application has to: 00027 (+) Configure the clock source to be used to drive the System clock 00028 (if the application needs higher frequency/performance) 00029 (+) Configure the System clock frequency and Flash settings 00030 (+) Configure the AHB and APB buses prescalers 00031 (+) Enable the clock for the peripheral(s) to be used 00032 (+) Configure the clock source(s) for peripherals whose clocks are not 00033 derived from the System clock (I2S, RTC, ADC, USB OTG FS) 00034 00035 ##### RCC Limitations ##### 00036 ============================================================================== 00037 [..] 00038 A delay between an RCC peripheral clock enable and the effective peripheral 00039 enabling should be taken into account in order to manage the peripheral read/write 00040 from/to registers. 00041 (+) This delay depends on the peripheral mapping. 00042 (++) AHB & APB peripherals, 1 dummy read is necessary 00043 00044 [..] 00045 Workarounds: 00046 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00047 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. 00048 00049 @endverbatim 00050 ****************************************************************************** 00051 * @attention 00052 * 00053 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00054 * 00055 * Redistribution and use in source and binary forms, with or without modification, 00056 * are permitted provided that the following conditions are met: 00057 * 1. Redistributions of source code must retain the above copyright notice, 00058 * this list of conditions and the following disclaimer. 00059 * 2. Redistributions in binary form must reproduce the above copyright notice, 00060 * this list of conditions and the following disclaimer in the documentation 00061 * and/or other materials provided with the distribution. 00062 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00063 * may be used to endorse or promote products derived from this software 00064 * without specific prior written permission. 00065 * 00066 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00067 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00068 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00069 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00070 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00071 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00072 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00073 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00074 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00075 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00076 * 00077 ****************************************************************************** 00078 */ 00079 00080 /* Includes ------------------------------------------------------------------*/ 00081 #include "stm32f1xx_hal.h" 00082 00083 /** @addtogroup STM32F1xx_HAL_Driver 00084 * @{ 00085 */ 00086 00087 /** @defgroup RCC RCC 00088 * @brief RCC HAL module driver 00089 * @{ 00090 */ 00091 00092 #ifdef HAL_RCC_MODULE_ENABLED 00093 00094 /* Private typedef -----------------------------------------------------------*/ 00095 /* Private define ------------------------------------------------------------*/ 00096 /** @defgroup RCC_Private_Constants RCC Private Constants 00097 * @{ 00098 */ 00099 /* Bits position in in the CFGR register */ 00100 #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) 00101 #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) 00102 #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) 00103 /** 00104 * @} 00105 */ 00106 /* Private macro -------------------------------------------------------------*/ 00107 /** @defgroup RCC_Private_Macros RCC Private Macros 00108 * @{ 00109 */ 00110 00111 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 00112 #define MCO1_GPIO_PORT GPIOA 00113 #define MCO1_PIN GPIO_PIN_8 00114 00115 /** 00116 * @} 00117 */ 00118 00119 /* Private variables ---------------------------------------------------------*/ 00120 /** @defgroup RCC_Private_Variables RCC Private Variables 00121 * @{ 00122 */ 00123 /** 00124 * @} 00125 */ 00126 00127 /* Private function prototypes -----------------------------------------------*/ 00128 /* Exported functions ---------------------------------------------------------*/ 00129 00130 /** @defgroup RCC_Exported_Functions RCC Exported Functions 00131 * @{ 00132 */ 00133 00134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 00135 * @brief Initialization and Configuration functions 00136 * 00137 @verbatim 00138 =============================================================================== 00139 ##### Initialization and de-initialization functions ##### 00140 =============================================================================== 00141 [..] 00142 This section provides functions allowing to configure the internal/external oscillators 00143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 00144 and APB2). 00145 00146 [..] Internal/external clock and PLL configuration 00147 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through 00148 the PLL as System clock source. 00149 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC 00150 clock source. 00151 00152 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or 00153 through the PLL as System clock source. Can be used also as RTC clock source. 00154 00155 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 00156 00157 (#) PLL (clocked by HSI or HSE), featuring different output clocks: 00158 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) 00159 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) 00160 00161 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() 00162 and if a HSE clock failure occurs(HSE used directly or through PLL as System 00163 clock source), the System clocks automatically switched to HSI and an interrupt 00164 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI 00165 (Non-Maskable Interrupt) exception vector. 00166 00167 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, 00168 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x 00169 00170 [..] System, AHB and APB buses clocks configuration 00171 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, 00172 HSE and PLL. 00173 The AHB clock (HCLK) is derived from System clock through configurable 00174 prescaler and used to clock the CPU, memory and peripherals mapped 00175 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 00176 from AHB clock through configurable prescalers and used to clock 00177 the peripherals mapped on these buses. You can use 00178 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. 00179 00180 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: 00181 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock 00182 divided by 128. 00183 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz 00184 to work correctly. This clock is derived of the main PLL through PLL Multiplier. 00185 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK 00186 (+@) IWDG clock which is always the LSI clock. 00187 00188 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. 00189 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. 00190 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. 00191 @endverbatim 00192 * @{ 00193 */ 00194 00195 /* 00196 Additional consideration on the SYSCLK based on Latency settings: 00197 +-----------------------------------------------+ 00198 | Latency | SYSCLK clock frequency (MHz) | 00199 |---------------|-------------------------------| 00200 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | 00201 |---------------|-------------------------------| 00202 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | 00203 |---------------|-------------------------------| 00204 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | 00205 +-----------------------------------------------+ 00206 */ 00207 00208 /** 00209 * @brief Resets the RCC clock configuration to the default reset state. 00210 * @note The default reset state of the clock configuration is given below: 00211 * - HSI ON and used as system clock source 00212 * - HSE and PLL OFF 00213 * - AHB, APB1 and APB2 prescaler set to 1. 00214 * - CSS and MCO1 OFF 00215 * - All interrupts disabled 00216 * @note This function does not modify the configuration of the 00217 * - Peripheral clocks 00218 * - LSI, LSE and RTC clocks 00219 * @retval None 00220 */ 00221 void HAL_RCC_DeInit(void) 00222 { 00223 /* Switch SYSCLK to HSI */ 00224 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); 00225 00226 /* Reset HSEON, CSSON, & PLLON bits */ 00227 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); 00228 00229 /* Reset HSEBYP bit */ 00230 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 00231 00232 /* Reset CFGR register */ 00233 CLEAR_REG(RCC->CFGR); 00234 00235 /* Set HSITRIM bits to the reset value */ 00236 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); 00237 00238 #if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)) 00239 /* Reset CFGR2 register */ 00240 CLEAR_REG(RCC->CFGR2); 00241 00242 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 00243 /* Disable all interrupts */ 00244 CLEAR_REG(RCC->CIR); 00245 00246 /* Update the SystemCoreClock global variable */ 00247 SystemCoreClock = HSI_VALUE; 00248 } 00249 00250 /** 00251 * @brief Initializes the RCC Oscillators according to the specified parameters in the 00252 * RCC_OscInitTypeDef. 00253 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 00254 * contains the configuration information for the RCC Oscillators. 00255 * @note The PLL is not disabled when used as system clock. 00256 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) 00257 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 00258 * supported by this macro. User should request a transition to LSE Off 00259 * first and then LSE On or LSE Bypass. 00260 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 00261 * supported by this macro. User should request a transition to HSE Off 00262 * first and then HSE On or HSE Bypass. 00263 * @retval HAL status 00264 */ 00265 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 00266 { 00267 uint32_t tickstart = 0; 00268 00269 /* Check the parameters */ 00270 assert_param(RCC_OscInitStruct != NULL); 00271 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); 00272 00273 /*------------------------------- HSE Configuration ------------------------*/ 00274 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 00275 { 00276 /* Check the parameters */ 00277 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); 00278 00279 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ 00280 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 00281 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 00282 { 00283 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 00284 { 00285 return HAL_ERROR; 00286 } 00287 } 00288 else 00289 { 00290 /* Set the new HSE configuration ---------------------------------------*/ 00291 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 00292 00293 00294 /* Check the HSE State */ 00295 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 00296 { 00297 /* Get Start Tick */ 00298 tickstart = HAL_GetTick(); 00299 00300 /* Wait till HSE is ready */ 00301 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 00302 { 00303 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 00304 { 00305 return HAL_TIMEOUT; 00306 } 00307 } 00308 } 00309 else 00310 { 00311 /* Get Start Tick */ 00312 tickstart = HAL_GetTick(); 00313 00314 /* Wait till HSE is disabled */ 00315 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 00316 { 00317 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 00318 { 00319 return HAL_TIMEOUT; 00320 } 00321 } 00322 } 00323 } 00324 } 00325 /*----------------------------- HSI Configuration --------------------------*/ 00326 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 00327 { 00328 /* Check the parameters */ 00329 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); 00330 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); 00331 00332 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 00333 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 00334 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 00335 { 00336 /* When HSI is used as system clock it will not disabled */ 00337 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 00338 { 00339 return HAL_ERROR; 00340 } 00341 /* Otherwise, just the calibration is allowed */ 00342 else 00343 { 00344 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 00345 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 00346 } 00347 } 00348 else 00349 { 00350 /* Check the HSI State */ 00351 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 00352 { 00353 /* Enable the Internal High Speed oscillator (HSI). */ 00354 __HAL_RCC_HSI_ENABLE(); 00355 00356 /* Get Start Tick */ 00357 tickstart = HAL_GetTick(); 00358 00359 /* Wait till HSI is ready */ 00360 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 00361 { 00362 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 00363 { 00364 return HAL_TIMEOUT; 00365 } 00366 } 00367 00368 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 00369 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 00370 } 00371 else 00372 { 00373 /* Disable the Internal High Speed oscillator (HSI). */ 00374 __HAL_RCC_HSI_DISABLE(); 00375 00376 /* Get Start Tick */ 00377 tickstart = HAL_GetTick(); 00378 00379 /* Wait till HSI is disabled */ 00380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 00381 { 00382 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 00383 { 00384 return HAL_TIMEOUT; 00385 } 00386 } 00387 } 00388 } 00389 } 00390 /*------------------------------ LSI Configuration -------------------------*/ 00391 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 00392 { 00393 /* Check the parameters */ 00394 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); 00395 00396 /* Check the LSI State */ 00397 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 00398 { 00399 /* Enable the Internal Low Speed oscillator (LSI). */ 00400 __HAL_RCC_LSI_ENABLE(); 00401 00402 /* Get Start Tick */ 00403 tickstart = HAL_GetTick(); 00404 00405 /* Wait till LSI is ready */ 00406 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 00407 { 00408 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 00409 { 00410 return HAL_TIMEOUT; 00411 } 00412 } 00413 /* To have a fully stabilized clock in the specified range, a software delay of 1ms 00414 should be added.*/ 00415 HAL_Delay(1); 00416 } 00417 else 00418 { 00419 /* Disable the Internal Low Speed oscillator (LSI). */ 00420 __HAL_RCC_LSI_DISABLE(); 00421 00422 /* Get Start Tick */ 00423 tickstart = HAL_GetTick(); 00424 00425 /* Wait till LSI is disabled */ 00426 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 00427 { 00428 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 00429 { 00430 return HAL_TIMEOUT; 00431 } 00432 } 00433 } 00434 } 00435 /*------------------------------ LSE Configuration -------------------------*/ 00436 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 00437 { 00438 /* Check the parameters */ 00439 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); 00440 00441 /* Enable Power Clock*/ 00442 __HAL_RCC_PWR_CLK_ENABLE(); 00443 00444 /* Enable write access to Backup domain */ 00445 SET_BIT(PWR->CR, PWR_CR_DBP); 00446 00447 /* Wait for Backup domain Write protection disable */ 00448 tickstart = HAL_GetTick(); 00449 00450 while((PWR->CR & PWR_CR_DBP) == RESET) 00451 { 00452 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 00453 { 00454 return HAL_TIMEOUT; 00455 } 00456 } 00457 00458 /* Set the new LSE configuration -----------------------------------------*/ 00459 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 00460 /* Check the LSE State */ 00461 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 00462 { 00463 /* Get Start Tick */ 00464 tickstart = HAL_GetTick(); 00465 00466 /* Wait till LSE is ready */ 00467 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 00468 { 00469 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 00470 { 00471 return HAL_TIMEOUT; 00472 } 00473 } 00474 } 00475 else 00476 { 00477 /* Get Start Tick */ 00478 tickstart = HAL_GetTick(); 00479 00480 /* Wait till LSE is disabled */ 00481 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 00482 { 00483 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 00484 { 00485 return HAL_TIMEOUT; 00486 } 00487 } 00488 } 00489 } 00490 00491 #if defined(RCC_CR_PLL2ON) 00492 /*-------------------------------- PLL2 Configuration -----------------------*/ 00493 /* Check the parameters */ 00494 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); 00495 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 00496 { 00497 /* This bit can not be cleared if the PLL2 clock is used indirectly as system 00498 clock (i.e. it is used as PLL clock entry that is used as system clock). */ 00499 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 00500 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 00501 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 00502 { 00503 return HAL_ERROR; 00504 } 00505 else 00506 { 00507 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 00508 { 00509 /* Check the parameters */ 00510 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); 00511 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); 00512 00513 /* Prediv2 can be written only when the PLLI2S is disabled. */ 00514 /* Return an error only if new value is different from the programmed value */ 00515 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \ 00516 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 00517 { 00518 return HAL_ERROR; 00519 } 00520 00521 /* Disable the main PLL2. */ 00522 __HAL_RCC_PLL2_DISABLE(); 00523 00524 /* Get Start Tick */ 00525 tickstart = HAL_GetTick(); 00526 00527 /* Wait till PLL2 is disabled */ 00528 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 00529 { 00530 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 00531 { 00532 return HAL_TIMEOUT; 00533 } 00534 } 00535 00536 /* Configure the HSE prediv2 factor --------------------------------*/ 00537 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 00538 00539 /* Configure the main PLL2 multiplication factors. */ 00540 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 00541 00542 /* Enable the main PLL2. */ 00543 __HAL_RCC_PLL2_ENABLE(); 00544 00545 /* Get Start Tick */ 00546 tickstart = HAL_GetTick(); 00547 00548 /* Wait till PLL2 is ready */ 00549 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 00550 { 00551 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 00552 { 00553 return HAL_TIMEOUT; 00554 } 00555 } 00556 } 00557 else 00558 { 00559 /* Set PREDIV1 source to HSE */ 00560 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 00561 00562 /* Disable the main PLL2. */ 00563 __HAL_RCC_PLL2_DISABLE(); 00564 00565 /* Get Start Tick */ 00566 tickstart = HAL_GetTick(); 00567 00568 /* Wait till PLL2 is disabled */ 00569 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 00570 { 00571 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 00572 { 00573 return HAL_TIMEOUT; 00574 } 00575 } 00576 } 00577 } 00578 } 00579 00580 #endif /* RCC_CR_PLL2ON */ 00581 /*-------------------------------- PLL Configuration -----------------------*/ 00582 /* Check the parameters */ 00583 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); 00584 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 00585 { 00586 /* Check if the PLL is used as system clock or not */ 00587 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 00588 { 00589 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 00590 { 00591 /* Check the parameters */ 00592 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); 00593 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); 00594 00595 /* Disable the main PLL. */ 00596 __HAL_RCC_PLL_DISABLE(); 00597 00598 /* Get Start Tick */ 00599 tickstart = HAL_GetTick(); 00600 00601 /* Wait till PLL is disabled */ 00602 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 00603 { 00604 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 00605 { 00606 return HAL_TIMEOUT; 00607 } 00608 } 00609 00610 /* Configure the HSE prediv factor --------------------------------*/ 00611 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ 00612 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 00613 { 00614 /* Check the parameter */ 00615 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); 00616 #if defined(RCC_CFGR2_PREDIV1SRC) 00617 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); 00618 00619 /* Set PREDIV1 source */ 00620 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 00621 #endif /* RCC_CFGR2_PREDIV1SRC */ 00622 00623 /* Set PREDIV1 Value */ 00624 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 00625 } 00626 00627 /* Configure the main PLL clock source and multiplication factors. */ 00628 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 00629 RCC_OscInitStruct->PLL.PLLMUL); 00630 /* Enable the main PLL. */ 00631 __HAL_RCC_PLL_ENABLE(); 00632 00633 /* Get Start Tick */ 00634 tickstart = HAL_GetTick(); 00635 00636 /* Wait till PLL is ready */ 00637 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 00638 { 00639 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 00640 { 00641 return HAL_TIMEOUT; 00642 } 00643 } 00644 } 00645 else 00646 { 00647 /* Disable the main PLL. */ 00648 __HAL_RCC_PLL_DISABLE(); 00649 00650 /* Get Start Tick */ 00651 tickstart = HAL_GetTick(); 00652 00653 /* Wait till PLL is disabled */ 00654 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 00655 { 00656 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 00657 { 00658 return HAL_TIMEOUT; 00659 } 00660 } 00661 } 00662 } 00663 else 00664 { 00665 return HAL_ERROR; 00666 } 00667 } 00668 00669 return HAL_OK; 00670 } 00671 00672 /** 00673 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified 00674 * parameters in the RCC_ClkInitStruct. 00675 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that 00676 * contains the configuration information for the RCC peripheral. 00677 * @param FLatency FLASH Latency 00678 * The value of this parameter depend on device used within the same series 00679 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency 00680 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function 00681 * 00682 * @note The HSI is used (enabled by hardware) as system clock source after 00683 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case 00684 * of failure of the HSE used directly or indirectly as system clock 00685 * (if the Clock Security System CSS is enabled). 00686 * 00687 * @note A switch from one clock source to another occurs only if the target 00688 * clock source is ready (clock stable after start-up delay or PLL locked). 00689 * If a clock source which is not yet ready is selected, the switch will 00690 * occur when the clock source will be ready. 00691 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is 00692 * currently used as system clock source. 00693 * @retval HAL status 00694 */ 00695 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) 00696 { 00697 uint32_t tickstart = 0; 00698 00699 /* Check the parameters */ 00700 assert_param(RCC_ClkInitStruct != NULL); 00701 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); 00702 assert_param(IS_FLASH_LATENCY(FLatency)); 00703 00704 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 00705 must be correctly programmed according to the frequency of the CPU clock 00706 (HCLK) of the device. */ 00707 00708 #if defined(FLASH_ACR_LATENCY) 00709 /* Increasing the number of wait states because of higher CPU frequency */ 00710 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 00711 { 00712 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 00713 __HAL_FLASH_SET_LATENCY(FLatency); 00714 00715 /* Check that the new number of wait states is taken into account to access the Flash 00716 memory by reading the FLASH_ACR register */ 00717 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 00718 { 00719 return HAL_ERROR; 00720 } 00721 } 00722 00723 #endif /* FLASH_ACR_LATENCY */ 00724 /*-------------------------- HCLK Configuration --------------------------*/ 00725 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 00726 { 00727 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); 00728 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 00729 } 00730 00731 /*------------------------- SYSCLK Configuration ---------------------------*/ 00732 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 00733 { 00734 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); 00735 00736 /* HSE is selected as System Clock Source */ 00737 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 00738 { 00739 /* Check the HSE ready flag */ 00740 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 00741 { 00742 return HAL_ERROR; 00743 } 00744 } 00745 /* PLL is selected as System Clock Source */ 00746 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 00747 { 00748 /* Check the PLL ready flag */ 00749 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 00750 { 00751 return HAL_ERROR; 00752 } 00753 } 00754 /* HSI is selected as System Clock Source */ 00755 else 00756 { 00757 /* Check the HSI ready flag */ 00758 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 00759 { 00760 return HAL_ERROR; 00761 } 00762 } 00763 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 00764 00765 /* Get Start Tick */ 00766 tickstart = HAL_GetTick(); 00767 00768 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 00769 { 00770 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 00771 { 00772 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 00773 { 00774 return HAL_TIMEOUT; 00775 } 00776 } 00777 } 00778 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 00779 { 00780 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 00781 { 00782 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 00783 { 00784 return HAL_TIMEOUT; 00785 } 00786 } 00787 } 00788 else 00789 { 00790 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 00791 { 00792 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 00793 { 00794 return HAL_TIMEOUT; 00795 } 00796 } 00797 } 00798 } 00799 #if defined(FLASH_ACR_LATENCY) 00800 /* Decreasing the number of wait states because of lower CPU frequency */ 00801 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) 00802 { 00803 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 00804 __HAL_FLASH_SET_LATENCY(FLatency); 00805 00806 /* Check that the new number of wait states is taken into account to access the Flash 00807 memory by reading the FLASH_ACR register */ 00808 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 00809 { 00810 return HAL_ERROR; 00811 } 00812 } 00813 #endif /* FLASH_ACR_LATENCY */ 00814 00815 /*-------------------------- PCLK1 Configuration ---------------------------*/ 00816 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 00817 { 00818 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); 00819 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 00820 } 00821 00822 /*-------------------------- PCLK2 Configuration ---------------------------*/ 00823 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 00824 { 00825 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); 00826 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 00827 } 00828 00829 /* Update the SystemCoreClock global variable */ 00830 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 00831 00832 /* Configure the source of time base considering new system clocks settings*/ 00833 HAL_InitTick (TICK_INT_PRIORITY); 00834 00835 return HAL_OK; 00836 } 00837 00838 /** 00839 * @} 00840 */ 00841 00842 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 00843 * @brief RCC clocks control functions 00844 * 00845 @verbatim 00846 =============================================================================== 00847 ##### Peripheral Control functions ##### 00848 =============================================================================== 00849 [..] 00850 This subsection provides a set of functions allowing to control the RCC Clocks 00851 frequencies. 00852 00853 @endverbatim 00854 * @{ 00855 */ 00856 00857 /** 00858 * @brief Selects the clock source to output on MCO pin. 00859 * @note MCO pin should be configured in alternate function mode. 00860 * @param RCC_MCOx specifies the output direction for the clock source. 00861 * This parameter can be one of the following values: 00862 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). 00863 * @param RCC_MCOSource specifies the clock source to output. 00864 * This parameter can be one of the following values: 00865 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 00866 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock 00867 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 00868 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 00869 @if STM32F105xC 00870 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source 00871 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source 00872 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source 00873 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source 00874 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source 00875 @endif 00876 @if STM32F107xC 00877 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source 00878 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source 00879 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source 00880 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source 00881 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source 00882 @endif 00883 * @param RCC_MCODiv specifies the MCO DIV. 00884 * This parameter can be one of the following values: 00885 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock 00886 * @retval None 00887 */ 00888 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) 00889 { 00890 GPIO_InitTypeDef gpio = {0}; 00891 00892 /* Check the parameters */ 00893 assert_param(IS_RCC_MCO(RCC_MCOx)); 00894 assert_param(IS_RCC_MCODIV(RCC_MCODiv)); 00895 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); 00896 00897 /* Configure the MCO1 pin in alternate function mode */ 00898 gpio.Mode = GPIO_MODE_AF_PP; 00899 gpio.Speed = GPIO_SPEED_FREQ_HIGH; 00900 gpio.Pull = GPIO_NOPULL; 00901 gpio.Pin = MCO1_PIN; 00902 00903 /* MCO1 Clock Enable */ 00904 MCO1_CLK_ENABLE(); 00905 00906 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); 00907 00908 /* Configure the MCO clock source */ 00909 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); 00910 } 00911 00912 /** 00913 * @brief Enables the Clock Security System. 00914 * @note If a failure is detected on the HSE oscillator clock, this oscillator 00915 * is automatically disabled and an interrupt is generated to inform the 00916 * software about the failure (Clock Security System Interrupt, CSSI), 00917 * allowing the MCU to perform rescue operations. The CSSI is linked to 00918 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. 00919 * @retval None 00920 */ 00921 void HAL_RCC_EnableCSS(void) 00922 { 00923 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; 00924 } 00925 00926 /** 00927 * @brief Disables the Clock Security System. 00928 * @retval None 00929 */ 00930 void HAL_RCC_DisableCSS(void) 00931 { 00932 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; 00933 } 00934 00935 /** 00936 * @brief Returns the SYSCLK frequency 00937 * @note The system frequency computed by this function is not the real 00938 * frequency in the chip. It is calculated based on the predefined 00939 * constant and the selected clock source: 00940 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) 00941 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE 00942 * divided by PREDIV factor(**) 00943 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE 00944 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. 00945 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value 00946 * 8 MHz) but the real value may vary depending on the variations 00947 * in voltage and temperature. 00948 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value 00949 * 8 MHz), user has to ensure that HSE_VALUE is same as the real 00950 * frequency of the crystal used. Otherwise, this function may 00951 * have wrong result. 00952 * 00953 * @note The result of this function could be not correct when using fractional 00954 * value for HSE crystal. 00955 * 00956 * @note This function can be used by the user application to compute the 00957 * baud-rate for the communication peripherals or configure other parameters. 00958 * 00959 * @note Each time SYSCLK changes, this function must be called to update the 00960 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. 00961 * 00962 * @retval SYSCLK frequency 00963 */ 00964 uint32_t HAL_RCC_GetSysClockFreq(void) 00965 { 00966 #if defined(RCC_CFGR2_PREDIV1SRC) 00967 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13}; 00968 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; 00969 #else 00970 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 00971 #if defined(RCC_CFGR2_PREDIV1) 00972 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; 00973 #else 00974 const uint8_t aPredivFactorTable[2] = { 1, 2}; 00975 #endif /*RCC_CFGR2_PREDIV1*/ 00976 00977 #endif 00978 uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0; 00979 uint32_t sysclockfreq = 0; 00980 #if defined(RCC_CFGR2_PREDIV1SRC) 00981 uint32_t prediv2 = 0, pll2mul = 0; 00982 #endif /*RCC_CFGR2_PREDIV1SRC*/ 00983 00984 tmpreg = RCC->CFGR; 00985 00986 /* Get SYSCLK source -------------------------------------------------------*/ 00987 switch (tmpreg & RCC_CFGR_SWS) 00988 { 00989 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ 00990 { 00991 sysclockfreq = HSE_VALUE; 00992 break; 00993 } 00994 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ 00995 { 00996 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)]; 00997 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 00998 { 00999 #if defined(RCC_CFGR2_PREDIV1) 01000 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)]; 01001 #else 01002 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)]; 01003 #endif /*RCC_CFGR2_PREDIV1*/ 01004 #if defined(RCC_CFGR2_PREDIV1SRC) 01005 01006 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 01007 { 01008 /* PLL2 selected as Prediv1 source */ 01009 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ 01010 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; 01011 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2; 01012 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul); 01013 } 01014 else 01015 { 01016 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ 01017 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul); 01018 } 01019 01020 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ 01021 /* In this case need to divide pllclk by 2 */ 01022 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) 01023 { 01024 pllclk = pllclk / 2; 01025 } 01026 #else 01027 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ 01028 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul); 01029 #endif /*RCC_CFGR2_PREDIV1SRC*/ 01030 } 01031 else 01032 { 01033 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ 01034 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 01035 } 01036 sysclockfreq = pllclk; 01037 break; 01038 } 01039 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ 01040 default: /* HSI used as system clock */ 01041 { 01042 sysclockfreq = HSI_VALUE; 01043 break; 01044 } 01045 } 01046 return sysclockfreq; 01047 } 01048 01049 /** 01050 * @brief Returns the HCLK frequency 01051 * @note Each time HCLK changes, this function must be called to update the 01052 * right HCLK value. Otherwise, any configuration based on this function will be incorrect. 01053 * 01054 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency 01055 * and updated within this function 01056 * @retval HCLK frequency 01057 */ 01058 uint32_t HAL_RCC_GetHCLKFreq(void) 01059 { 01060 return SystemCoreClock; 01061 } 01062 01063 /** 01064 * @brief Returns the PCLK1 frequency 01065 * @note Each time PCLK1 changes, this function must be called to update the 01066 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. 01067 * @retval PCLK1 frequency 01068 */ 01069 uint32_t HAL_RCC_GetPCLK1Freq(void) 01070 { 01071 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ 01072 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); 01073 } 01074 01075 /** 01076 * @brief Returns the PCLK2 frequency 01077 * @note Each time PCLK2 changes, this function must be called to update the 01078 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. 01079 * @retval PCLK2 frequency 01080 */ 01081 uint32_t HAL_RCC_GetPCLK2Freq(void) 01082 { 01083 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ 01084 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); 01085 } 01086 01087 /** 01088 * @brief Configures the RCC_OscInitStruct according to the internal 01089 * RCC configuration registers. 01090 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 01091 * will be configured. 01092 * @retval None 01093 */ 01094 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 01095 { 01096 /* Check the parameters */ 01097 assert_param(RCC_OscInitStruct != NULL); 01098 01099 /* Set all possible values for the Oscillator type parameter ---------------*/ 01100 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ 01101 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; 01102 01103 #if defined(RCC_CFGR2_PREDIV1SRC) 01104 /* Get the Prediv1 source --------------------------------------------------*/ 01105 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC); 01106 #endif /* RCC_CFGR2_PREDIV1SRC */ 01107 01108 /* Get the HSE configuration -----------------------------------------------*/ 01109 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) 01110 { 01111 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; 01112 } 01113 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) 01114 { 01115 RCC_OscInitStruct->HSEState = RCC_HSE_ON; 01116 } 01117 else 01118 { 01119 RCC_OscInitStruct->HSEState = RCC_HSE_OFF; 01120 } 01121 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); 01122 01123 /* Get the HSI configuration -----------------------------------------------*/ 01124 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) 01125 { 01126 RCC_OscInitStruct->HSIState = RCC_HSI_ON; 01127 } 01128 else 01129 { 01130 RCC_OscInitStruct->HSIState = RCC_HSI_OFF; 01131 } 01132 01133 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); 01134 01135 /* Get the LSE configuration -----------------------------------------------*/ 01136 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) 01137 { 01138 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; 01139 } 01140 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) 01141 { 01142 RCC_OscInitStruct->LSEState = RCC_LSE_ON; 01143 } 01144 else 01145 { 01146 RCC_OscInitStruct->LSEState = RCC_LSE_OFF; 01147 } 01148 01149 /* Get the LSI configuration -----------------------------------------------*/ 01150 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) 01151 { 01152 RCC_OscInitStruct->LSIState = RCC_LSI_ON; 01153 } 01154 else 01155 { 01156 RCC_OscInitStruct->LSIState = RCC_LSI_OFF; 01157 } 01158 01159 01160 /* Get the PLL configuration -----------------------------------------------*/ 01161 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) 01162 { 01163 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; 01164 } 01165 else 01166 { 01167 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; 01168 } 01169 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); 01170 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); 01171 #if defined(RCC_CR_PLL2ON) 01172 /* Get the PLL2 configuration -----------------------------------------------*/ 01173 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON) 01174 { 01175 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; 01176 } 01177 else 01178 { 01179 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; 01180 } 01181 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); 01182 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); 01183 #endif /* RCC_CR_PLL2ON */ 01184 } 01185 01186 /** 01187 * @brief Get the RCC_ClkInitStruct according to the internal 01188 * RCC configuration registers. 01189 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that 01190 * contains the current clock configuration. 01191 * @param pFLatency Pointer on the Flash Latency. 01192 * @retval None 01193 */ 01194 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) 01195 { 01196 /* Check the parameters */ 01197 assert_param(RCC_ClkInitStruct != NULL); 01198 assert_param(pFLatency != NULL); 01199 01200 /* Set all possible values for the Clock type parameter --------------------*/ 01201 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 01202 01203 /* Get the SYSCLK configuration --------------------------------------------*/ 01204 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 01205 01206 /* Get the HCLK configuration ----------------------------------------------*/ 01207 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 01208 01209 /* Get the APB1 configuration ----------------------------------------------*/ 01210 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 01211 01212 /* Get the APB2 configuration ----------------------------------------------*/ 01213 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); 01214 01215 #if defined(FLASH_ACR_LATENCY) 01216 /* Get the Flash Wait State (Latency) configuration ------------------------*/ 01217 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 01218 #else 01219 /* For VALUE lines devices, only LATENCY_0 can be set*/ 01220 *pFLatency = (uint32_t)FLASH_LATENCY_0; 01221 #endif 01222 } 01223 01224 /** 01225 * @brief This function handles the RCC CSS interrupt request. 01226 * @note This API should be called under the NMI_Handler(). 01227 * @retval None 01228 */ 01229 void HAL_RCC_NMI_IRQHandler(void) 01230 { 01231 /* Check RCC CSSF flag */ 01232 if(__HAL_RCC_GET_IT(RCC_IT_CSS)) 01233 { 01234 /* RCC Clock Security System interrupt user callback */ 01235 HAL_RCC_CSSCallback(); 01236 01237 /* Clear RCC CSS pending bit */ 01238 __HAL_RCC_CLEAR_IT(RCC_IT_CSS); 01239 } 01240 } 01241 01242 /** 01243 * @brief RCC Clock Security System interrupt callback 01244 * @retval none 01245 */ 01246 __weak void HAL_RCC_CSSCallback(void) 01247 { 01248 /* NOTE : This function Should not be modified, when the callback is needed, 01249 the HAL_RCC_CSSCallback could be implemented in the user file 01250 */ 01251 } 01252 01253 /** 01254 * @} 01255 */ 01256 01257 /** 01258 * @} 01259 */ 01260 01261 #endif /* HAL_RCC_MODULE_ENABLED */ 01262 /** 01263 * @} 01264 */ 01265 01266 /** 01267 * @} 01268 */ 01269 01270 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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