sdk.c

00001 /**
00002  * @file    sdk.c
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #include "NuMicro.h"
00023 #include "DAP_config.h"
00024 #include "gpio.h"
00025 #include "daplink.h"
00026 #include "util.h"
00027 #include "cortex_m.h"
00028 
00029 void sdk_init()
00030 {
00031     uint32_t volatile i;
00032     /* Unlock protected registers */
00033     SYS_UnlockReg();
00034     /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
00035     PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
00036     /* Enable External XTAL (4~24 MHz) */
00037     CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
00038     /* Waiting for 12MHz clock ready */
00039     CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
00040     /* Switch HCLK clock source to HXT */
00041     CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
00042     /* Set core clock as PLL_CLOCK from PLL */
00043     CLK_SetCoreClock(FREQ_192MHZ);
00044     /* Set PCLK0/PCLK1 to HCLK/2 */
00045     CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2);
00046     /* Select HSUSBD */
00047     SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk;
00048     /* Enable USB PHY */
00049     SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk;
00050 
00051     for (i = 0; i < 0x1000; i++); // delay > 10 us
00052 
00053     SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
00054     /* Enable HSUSBD clock */
00055     CLK_EnableModuleClock(HSUSBD_MODULE);
00056     /* Select UART clock source */
00057     CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
00058     /* Enable UART clock */
00059     CLK_EnableModuleClock(UART0_MODULE);
00060     /* Set GPA multi-function pins for UART0 RXD and TXD */
00061     SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk);
00062     SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA0MFP_UART0_RXD | SYS_GPA_MFPL_PA1MFP_UART0_TXD);
00063     /* Update System Core Clock */
00064     /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
00065     SystemCoreClockUpdate();
00066     /* Lock protected registers */
00067     SYS_LockReg();
00068 }